mirror of https://github.com/gnss-sdr/gnss-sdr
120 lines
3.3 KiB
C++
120 lines
3.3 KiB
C++
// SPDX-FileCopyrightText: 2017 Google Inc.
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// SPDX-License-Identifier: Apache-2.0
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#include "cpuinfo_mips.h"
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#include "filesystem_for_testing.h"
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#include "gtest/gtest.h"
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#include "hwcaps_for_testing.h"
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#include "internal/stack_line_reader.h"
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#include "internal/string_view.h"
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namespace cpu_features
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{
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namespace
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{
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void DisableHardwareCapabilities() { SetHardwareCapabilities(0, 0); }
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TEST(CpuinfoMipsTest, FromHardwareCapBoth)
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{
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SetHardwareCapabilities(MIPS_HWCAP_MSA | MIPS_HWCAP_R6, 0);
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GetEmptyFilesystem(); // disabling /proc/cpuinfo
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const auto info = GetMipsInfo();
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EXPECT_TRUE(info.features.msa);
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EXPECT_FALSE(info.features.eva);
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EXPECT_TRUE(info.features.r6);
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}
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TEST(CpuinfoMipsTest, FromHardwareCapOnlyOne)
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{
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SetHardwareCapabilities(MIPS_HWCAP_MSA, 0);
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GetEmptyFilesystem(); // disabling /proc/cpuinfo
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const auto info = GetMipsInfo();
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EXPECT_TRUE(info.features.msa);
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EXPECT_FALSE(info.features.eva);
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}
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TEST(CpuinfoMipsTest, Ci40)
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{
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DisableHardwareCapabilities();
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auto& fs = GetEmptyFilesystem();
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fs.CreateFile("/proc/cpuinfo", R"(system type : IMG Pistachio SoC (B0)
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machine : IMG Marduk – Ci40 with cc2520
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processor : 0
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cpu model : MIPS interAptiv (multi) V2.0 FPU V0.0
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BogoMIPS : 363.72
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wait instruction : yes
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microsecond timers : yes
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tlb_entries : 64
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extra interrupt vector : yes
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hardware watchpoint : yes, count: 4, address/irw mask: [0x0ffc, 0x0ffc, 0x0ffb, 0x0ffb]
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isa : mips1 mips2 mips32r1 mips32r2
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ASEs implemented : mips16 dsp mt eva
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shadow register sets : 1
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kscratch registers : 0
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package : 0
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core : 0
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VCED exceptions : not available
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VCEI exceptions : not available
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VPE : 0
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)");
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const auto info = GetMipsInfo();
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EXPECT_FALSE(info.features.msa);
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EXPECT_TRUE(info.features.eva);
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}
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TEST(CpuinfoMipsTest, AR7161)
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{
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DisableHardwareCapabilities();
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auto& fs = GetEmptyFilesystem();
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fs.CreateFile("/proc/cpuinfo",
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R"(system type : Atheros AR7161 rev 2
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machine : NETGEAR WNDR3700/WNDR3800/WNDRMAC
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processor : 0
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cpu model : MIPS 24Kc V7.4
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BogoMIPS : 452.19
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wait instruction : yes
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microsecond timers : yes
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tlb_entries : 16
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extra interrupt vector : yes
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hardware watchpoint : yes, count: 4, address/irw mask: [0x0000, 0x0f98, 0x0f78, 0x0df8]
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ASEs implemented : mips16
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shadow register sets : 1
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kscratch registers : 0
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core : 0
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VCED exceptions : not available
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VCEI exceptions : not available
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)");
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const auto info = GetMipsInfo();
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EXPECT_FALSE(info.features.msa);
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EXPECT_FALSE(info.features.eva);
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}
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TEST(CpuinfoMipsTest, Goldfish)
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{
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DisableHardwareCapabilities();
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auto& fs = GetEmptyFilesystem();
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fs.CreateFile("/proc/cpuinfo", R"(system type : MIPS-Goldfish
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Hardware : goldfish
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Revison : 1
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processor : 0
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cpu model : MIPS 24Kc V0.0 FPU V0.0
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BogoMIPS : 1042.02
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wait instruction : yes
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microsecond timers : yes
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tlb_entries : 16
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extra interrupt vector : yes
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hardware watchpoint : yes, count: 1, address/irw mask: [0x0ff8]
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ASEs implemented :
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shadow register sets : 1
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core : 0
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VCED exceptions : not available
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VCEI exceptions : not available
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)");
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const auto info = GetMipsInfo();
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EXPECT_FALSE(info.features.msa);
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EXPECT_FALSE(info.features.eva);
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}
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} // namespace
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} // namespace cpu_features
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