mirror of https://github.com/gnss-sdr/gnss-sdr
324 lines
11 KiB
C++
324 lines
11 KiB
C++
/*!
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* \file fpga_acquisition.cc
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* \brief Highly optimized FPGA vector correlator class
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* \authors <ul>
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* <li> Marc Majoral, 2019. mmajoral(at)cttc.cat
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* </ul>
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*
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* Class that controls and executes a highly optimized acquisition HW
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* accelerator in the FPGA
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*
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* -------------------------------------------------------------------------
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*
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* Copyright (C) 2010-2019 (see AUTHORS file for a list of contributors)
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*
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* GNSS-SDR is a software defined Global Navigation
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* Satellite Systems receiver
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*
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* This file is part of GNSS-SDR.
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*
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* GNSS-SDR is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* GNSS-SDR is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNSS-SDR. If not, see <https://www.gnu.org/licenses/>.
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*
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* -------------------------------------------------------------------------
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*/
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#include "fpga_acquisition.h"
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#include "GPS_L1_CA.h" // for GPS_TWO_PI
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#include <glog/logging.h> // for LOG
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#include <cmath> // for log2
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#include <fcntl.h> // libraries used by the GIPO
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#include <iostream> // for operator<<
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#include <sys/mman.h> // libraries used by the GIPO
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#include <unistd.h> // for write, close, read, ssize_t
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#include <utility> // for move
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// FPGA register parameters
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#define PAGE_SIZE 0x10000 // default page size for the multicorrelator memory map
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#define RESET_ACQUISITION 2 // command to reset the multicorrelator
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#define LAUNCH_ACQUISITION 1 // command to launch the multicorrelator
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#define TEST_REG_SANITY_CHECK 0x55AA // value to check the presence of the test register (to detect the hw)
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#define LOCAL_CODE_CLEAR_MEM 0x10000000 // command to clear the internal memory of the multicorrelator
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#define MEM_LOCAL_CODE_WR_ENABLE 0x0C000000 // command to enable the ENA and WR pins of the internal memory of the multicorrelator
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#define POW_2_2 4 // 2^2 (used for the conversion of floating point numbers to integers)
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#define POW_2_31 2147483648 // 2^31 (used for the conversion of floating point numbers to integers)
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#define SELECT_LSBits 0x0000FFFF // Select the 10 LSbits out of a 20-bit word
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#define SELECT_MSBbits 0xFFFF0000 // Select the 10 MSbits out of a 20-bit word
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#define SELECT_ALL_CODE_BITS 0xFFFFFFFF // Select a 20 bit word
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#define SHL_CODE_BITS 65536 // shift left by 10 bits
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#ifndef TEMP_FAILURE_RETRY
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#define TEMP_FAILURE_RETRY(exp) \
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({ \
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decltype(exp) _rc; \
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do \
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{ \
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_rc = (exp); \
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} \
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while (_rc == -1 && errno == EINTR); \
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_rc; \
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})
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#endif
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Fpga_Acquisition::Fpga_Acquisition(std::string device_name,
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uint32_t nsamples,
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uint32_t doppler_max,
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uint32_t nsamples_total,
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int64_t fs_in,
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uint32_t sampled_ms __attribute__((unused)),
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uint32_t select_queue,
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uint32_t *all_fft_codes,
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uint32_t excludelimit)
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{
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uint32_t vector_length = nsamples_total;
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// initial values
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d_device_name = std::move(device_name);
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d_fs_in = fs_in;
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d_vector_length = vector_length;
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d_excludelimit = excludelimit;
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d_nsamples = nsamples; // number of samples not including padding
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d_select_queue = select_queue;
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d_nsamples_total = nsamples_total;
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d_doppler_max = doppler_max;
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d_doppler_step = 0;
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d_fd = 0; // driver descriptor
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d_map_base = nullptr; // driver memory map
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d_all_fft_codes = all_fft_codes;
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Fpga_Acquisition::open_device();
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Fpga_Acquisition::reset_acquisition();
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Fpga_Acquisition::fpga_acquisition_test_register();
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Fpga_Acquisition::close_device();
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d_PRN = 0;
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DLOG(INFO) << "Acquisition FPGA class created";
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}
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bool Fpga_Acquisition::set_local_code(uint32_t PRN)
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{
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// select the code with the chosen PRN
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d_PRN = PRN;
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return true;
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}
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void Fpga_Acquisition::write_local_code()
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{
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d_map_base[9] = LOCAL_CODE_CLEAR_MEM;
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// write local code
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for (uint32_t k = 0; k < d_vector_length; k++)
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{
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d_map_base[6] = d_all_fft_codes[d_nsamples_total * (d_PRN - 1) + k];
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}
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}
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void Fpga_Acquisition::open_device()
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{
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// open communication with HW accelerator
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if ((d_fd = open(d_device_name.c_str(), O_RDWR | O_SYNC)) == -1)
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{
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LOG(WARNING) << "Cannot open deviceio" << d_device_name;
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std::cout << "Acq: cannot open deviceio" << d_device_name << std::endl;
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}
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d_map_base = reinterpret_cast<volatile uint32_t *>(mmap(nullptr, PAGE_SIZE,
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PROT_READ | PROT_WRITE, MAP_SHARED, d_fd, 0));
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if (d_map_base == reinterpret_cast<void *>(-1))
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{
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LOG(WARNING) << "Cannot map the FPGA acquisition module into user memory";
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std::cout << "Acq: cannot map deviceio" << d_device_name << std::endl;
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}
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}
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void Fpga_Acquisition::fpga_acquisition_test_register()
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{
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// sanity check : check test register
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uint32_t writeval = TEST_REG_SANITY_CHECK;
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uint32_t readval;
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// write value to test register
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d_map_base[15] = writeval;
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// read value from test register
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readval = d_map_base[15];
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if (writeval != readval)
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{
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LOG(WARNING) << "Acquisition test register sanity check failed";
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}
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else
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{
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LOG(INFO) << "Acquisition test register sanity check success!";
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}
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}
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void Fpga_Acquisition::run_acquisition(void)
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{
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// enable interrupts
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int32_t reenable = 1;
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//int32_t disable_int = 0;
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ssize_t nbytes = TEMP_FAILURE_RETRY(write(d_fd, reinterpret_cast<void *>(&reenable), sizeof(int32_t)));
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if (nbytes != sizeof(int32_t))
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{
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std::cerr << "Error enabling run in the FPGA." << std::endl;
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}
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// launch the acquisition process
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d_map_base[8] = LAUNCH_ACQUISITION; // writing a 1 to reg 8 launches the acquisition process
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int32_t irq_count;
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ssize_t nb;
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// wait for interrupt
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nb = read(d_fd, &irq_count, sizeof(irq_count));
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if (nb != sizeof(irq_count))
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{
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std::cout << "acquisition module Read failed to retrieve 4 bytes!" << std::endl;
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std::cout << "acquisition module Interrupt number " << irq_count << std::endl;
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}
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// nbytes = TEMP_FAILURE_RETRY(write(d_fd, reinterpret_cast<void *>(&disable_int), sizeof(int32_t)));
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// if (nbytes != sizeof(int32_t))
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// {
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// std::cerr << "Error disabling interruptions in the FPGA." << std::endl;
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// }
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}
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void Fpga_Acquisition::set_block_exp(uint32_t total_block_exp)
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{
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d_map_base[11] = total_block_exp;
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}
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void Fpga_Acquisition::set_doppler_sweep(uint32_t num_sweeps, uint32_t doppler_step, int32_t doppler_min)
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{
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float phase_step_rad_real;
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int32_t phase_step_rad_int;
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// The doppler step can never be outside the range -pi to +pi, otherwise there would be aliasing
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// The FPGA expects phase_step_rad between -1 (-pi) to +1 (+pi)
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phase_step_rad_real = 2.0 * (doppler_min) / static_cast<float>(d_fs_in);
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phase_step_rad_int = static_cast<int32_t>(phase_step_rad_real * (POW_2_31));
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d_map_base[3] = phase_step_rad_int;
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// repeat the calculation with the doppler step
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phase_step_rad_real = 2.0 * (doppler_step) / static_cast<float>(d_fs_in);
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phase_step_rad_int = static_cast<int32_t>(phase_step_rad_real * (POW_2_31)); // * 2^29 (in total it makes x2^31 in two steps to avoid the warnings
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d_map_base[4] = phase_step_rad_int;
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// write number of doppler sweeps
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d_map_base[5] = num_sweeps;
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}
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void Fpga_Acquisition::configure_acquisition()
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{
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//Fpga_Acquisition::open_device();
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d_map_base[0] = d_select_queue;
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d_map_base[1] = d_vector_length;
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d_map_base[2] = d_nsamples;
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d_map_base[7] = static_cast<int32_t>(log2(static_cast<float>(d_vector_length))); // log2 FFTlength
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d_map_base[12] = d_excludelimit;
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}
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void Fpga_Acquisition::read_acquisition_results(uint32_t *max_index,
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float *firstpeak, float *secondpeak, uint64_t *initial_sample, float *power_sum, uint32_t *doppler_index, uint32_t *total_blk_exp)
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{
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uint64_t initial_sample_tmp = 0;
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uint32_t readval = 0;
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uint64_t readval_long = 0;
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uint64_t readval_long_shifted = 0;
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readval = d_map_base[1]; // read sample counter (LSW)
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initial_sample_tmp = readval;
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readval_long = d_map_base[2]; // read sample counter (MSW)
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readval_long_shifted = readval_long << 32; // 2^32
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initial_sample_tmp = initial_sample_tmp + readval_long_shifted; // 2^32
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*initial_sample = initial_sample_tmp;
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readval = d_map_base[3]; // read first peak value
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*firstpeak = static_cast<float>(readval);
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readval = d_map_base[4]; // read second peak value
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*secondpeak = static_cast<float>(readval);
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readval = d_map_base[5]; // read max index position
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*max_index = readval;
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*power_sum = 0; // power sum is not used
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readval = d_map_base[7]; // read doppler index -- this read releases the interrupt line
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*doppler_index = readval;
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readval = d_map_base[8]; // read FFT block exponent
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*total_blk_exp = readval;
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}
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void Fpga_Acquisition::block_samples()
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{
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d_map_base[14] = 1; // block the samples
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}
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void Fpga_Acquisition::unblock_samples()
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{
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d_map_base[14] = 0; // unblock the samples
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}
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void Fpga_Acquisition::close_device()
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{
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auto *aux = const_cast<uint32_t *>(d_map_base);
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if (munmap(static_cast<void *>(aux), PAGE_SIZE) == -1)
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{
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std::cout << "Failed to unmap memory uio" << std::endl;
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}
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close(d_fd);
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}
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void Fpga_Acquisition::reset_acquisition(void)
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{
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d_map_base[8] = RESET_ACQUISITION; // writing a 2 to d_map_base[8] resets the acquisition. This causes a reset of all
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// the FPGA HW modules including the multicorrelators
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}
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// this function is only used for the unit tests
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void Fpga_Acquisition::read_fpga_total_scale_factor(uint32_t *total_scale_factor, uint32_t *fw_scale_factor)
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{
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uint32_t readval = 0;
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readval = d_map_base[8];
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*total_scale_factor = readval;
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// only the total scale factor is used for the tests (fw scale factor to be removed)
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*fw_scale_factor = 0;
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}
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void Fpga_Acquisition::read_result_valid(uint32_t *result_valid)
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{
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uint32_t readval = 0;
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readval = d_map_base[0];
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*result_valid = readval;
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}
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