mirror of https://github.com/gnss-sdr/gnss-sdr
148 lines
5.0 KiB
C++
148 lines
5.0 KiB
C++
/*!
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* \file fpga_multicorrelator.h
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* \brief FPGA vector correlator class
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* \authors <ul>
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* <li> Marc Majoral, 2019. mmajoral(at)cttc.cat
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* <li> Javier Arribas, 2019. jarribas(at)cttc.es
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* </ul>
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*
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* Class that controls and executes a highly optimized vector correlator
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* class in the FPGA
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*
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* -------------------------------------------------------------------------
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*
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* Copyright (C) 2010-2019 (see AUTHORS file for a list of contributors)
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*
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* GNSS-SDR is a software defined Global Navigation
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* Satellite Systems receiver
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*
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* This file is part of GNSS-SDR.
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*
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* GNSS-SDR is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* GNSS-SDR is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNSS-SDR. If not, see <http://www.gnu.org/licenses/>.
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*
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* -------------------------------------------------------------------------
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*/
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#ifndef GNSS_SDR_FPGA_MULTICORRELATOR_8SC_H_
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#define GNSS_SDR_FPGA_MULTICORRELATOR_8SC_H_
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#include <gnuradio/block.h>
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#include <volk_gnsssdr/volk_gnsssdr.h>
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#include <cstdint>
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// FPGA register addresses
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// write addresses
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#define CODE_PHASE_STEP_CHIPS_NUM_REG_ADDR 0
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#define INITIAL_INDEX_REG_BASE_ADDR 1
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#define INITIAL_INTERP_COUNTER_REG_BASE_ADDR 7
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#define NSAMPLES_MINUS_1_REG_ADDR 13
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#define CODE_LENGTH_MINUS_1_REG_ADDR 14
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#define REM_CARR_PHASE_RAD_REG_ADDR 15
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#define PHASE_STEP_RAD_REG_ADDR 16
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#define PROG_MEMS_ADDR 17
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#define DROP_SAMPLES_REG_ADDR 18
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#define INITIAL_COUNTER_VALUE_REG_ADDR_LSW 19
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#define INITIAL_COUNTER_VALUE_REG_ADDR_MSW 20
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#define STOP_TRACKING_REG_ADDR 23
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#define START_FLAG_ADDR 30
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// read-write addresses
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#define TEST_REG_ADDR 31
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// read addresses
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#define RESULT_REG_REAL_BASE_ADDR 1
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#define RESULT_REG_IMAG_BASE_ADDR 7
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#define SAMPLE_COUNTER_REG_ADDR_LSW 13
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#define SAMPLE_COUNTER_REG_ADDR_MSW 14
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/*!
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* \brief Class that implements carrier wipe-off and correlators.
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*/
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class Fpga_Multicorrelator_8sc
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{
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public:
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Fpga_Multicorrelator_8sc(int32_t n_correlators, std::string device_name,
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uint32_t device_base, int32_t *ca_codes, int32_t *data_codes, uint32_t code_length_chips, bool track_pilot, uint32_t multicorr_type, uint32_t code_samples_per_chip);
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~Fpga_Multicorrelator_8sc();
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void set_output_vectors(gr_complex *corr_out, gr_complex *Prompt_Data);
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void set_local_code_and_taps(
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float *shifts_chips, float *prompt_data_shift, int32_t PRN);
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void update_local_code(float rem_code_phase_chips);
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void Carrier_wipeoff_multicorrelator_resampler(
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float rem_carrier_phase_in_rad, float phase_step_rad,
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float carrier_phase_rate_step_rad,
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float rem_code_phase_chips, float code_phase_step_chips,
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float code_phase_rate_step_chips,
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int32_t signal_length_samples);
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bool free();
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void set_channel(uint32_t channel);
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void set_initial_sample(uint64_t samples_offset);
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uint64_t read_sample_counter();
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void lock_channel(void);
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void unlock_channel(void);
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private:
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gr_complex *d_corr_out;
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gr_complex *d_Prompt_Data;
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float *d_shifts_chips;
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float *d_prompt_data_shift;
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int32_t d_code_length_chips;
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int32_t d_n_correlators; // number of correlators
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// data related to the hardware module and the driver
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int32_t d_device_descriptor; // driver descriptor
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volatile uint32_t *d_map_base; // driver memory map
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// configuration data received from the interface
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uint32_t d_channel; // channel number
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uint32_t d_correlator_length_samples;
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float d_rem_code_phase_chips;
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float d_code_phase_step_chips;
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float d_rem_carrier_phase_in_rad;
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float d_phase_step_rad;
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// configuration data computed in the format that the FPGA expects
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uint32_t *d_initial_index;
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uint32_t *d_initial_interp_counter;
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uint32_t d_code_phase_step_chips_num;
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int32_t d_rem_carr_phase_rad_int;
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int32_t d_phase_step_rad_int;
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uint64_t d_initial_sample_counter;
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// driver
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std::string d_device_name;
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uint32_t d_device_base;
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int32_t *d_ca_codes;
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int32_t *d_data_codes;
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uint32_t d_code_samples_per_chip;
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bool d_track_pilot;
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uint32_t d_multicorr_type;
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// private functions
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uint32_t fpga_acquisition_test_register(uint32_t writeval);
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void fpga_configure_tracking_gps_local_code(int32_t PRN);
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void fpga_compute_code_shift_parameters(void);
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void fpga_configure_code_parameters_in_fpga(void);
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void fpga_compute_signal_parameters_in_fpga(void);
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void fpga_configure_signal_parameters_in_fpga(void);
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void fpga_launch_multicorrelator_fpga(void);
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void read_tracking_gps_results(void);
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void close_device(void);
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};
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#endif /* GNSS_SDR_FPGA_MULTICORRELATOR_H_ */
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