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Carles Fernandez
4d3ad83957
Follow-ups to the frequency-error-reduction merge (tracking state 5): - Anchor Flag_PLL_180_deg_phase_locked to the sign of the last Prompt symbol. The differential bit/secondary-code detector reconstructs bits relative to an arbitrary first bit, so the previous corr_value sign rule was independent of the actual carrier polarity. - Do not feed the deliberate Doppler bin hops of the scan into the high_dyn carrier/code phase-rate smoothers: clear the histories and zero the rate steps while scanning. - Start the pull_in_time_s and bit_synchronization_time_limit_s budgets at the first sample after the scan instead of at acquisition, so long scans no longer consume the FLL pull-in or the sync time limit. Scan completion re-arms pull-in and resets the lock-fail counters. The non-scan path keeps the acquisition time origin. - Clamp f_error_accumulation to at least 1, both when parsed from the configuration and in the block constructor, to avoid an out-of-bounds write and a scan that never advances. - Add unit tests for polarity, rate suppression, timers, and a full L2C scan, and document the new options in the CHANGELOG.