mirror of https://github.com/gnss-sdr/gnss-sdr
424 lines
18 KiB
C++
424 lines
18 KiB
C++
/*!
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* \file fpga_acquisition.cc
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* \brief High optimized FPGA vector correlator class
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* \authors <ul>
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* <li> Marc Majoral, 2018. mmajoral(at)cttc.cat
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* </ul>
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*
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* Class that controls and executes a high optimized acquisition HW
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* accelerator in the FPGA
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*
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* -------------------------------------------------------------------------
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*
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* Copyright (C) 2010-2018 (see AUTHORS file for a list of contributors)
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*
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* GNSS-SDR is a software defined Global Navigation
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* Satellite Systems receiver
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*
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* This file is part of GNSS-SDR.
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*
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* GNSS-SDR is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* GNSS-SDR is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNSS-SDR. If not, see <https://www.gnu.org/licenses/>.
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*
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* -------------------------------------------------------------------------
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*/
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#include "fpga_acquisition.h"
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#include "GPS_L1_CA.h"
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#include "gps_sdr_signal_processing.h"
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#include <glog/logging.h>
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#include <fcntl.h> // libraries used by the GIPO
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#include <iostream>
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#include <sys/mman.h> // libraries used by the GIPO
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#define PAGE_SIZE 0x10000 // default page size for the multicorrelator memory map
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#define MAX_PHASE_STEP_RAD 0.999999999534339 // 1 - pow(2,-31);
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#define RESET_ACQUISITION 2 // command to reset the multicorrelator
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#define LAUNCH_ACQUISITION 1 // command to launch the multicorrelator
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#define TEST_REG_SANITY_CHECK 0x55AA // value to check the presence of the test register (to detect the hw)
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#define LOCAL_CODE_CLEAR_MEM 0x10000000 // command to clear the internal memory of the multicorrelator
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#define MEM_LOCAL_CODE_WR_ENABLE 0x0C000000 // command to enable the ENA and WR pins of the internal memory of the multicorrelator
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#define POW_2_2 4 // 2^2 (used for the conversion of floating point numbers to integers)
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#define POW_2_29 536870912 // 2^29 (used for the conversion of floating point numbers to integers)
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#define SELECT_LSB 0x00FF // value to select the least significant byte
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#define SELECT_MSB 0XFF00 // value to select the most significant byte
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#define SELECT_16_BITS 0xFFFF // value to select 16 bits
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#define SHL_8_BITS 256 // value used to shift a value 8 bits to the left
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// 12-bits
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//#define SELECT_LSBits 0x0FFF
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//#define SELECT_MSBbits 0x00FFF000
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//#define SELECT_24_BITS 0x00FFFFFF
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//#define SHL_12_BITS 4096
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// 16-bits
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#define SELECT_LSBits 0x0FFFF
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#define SELECT_MSBbits 0xFFFF0000
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#define SELECT_32_BITS 0xFFFFFFFF
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#define SHL_16_BITS 65536
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bool fpga_acquisition::init()
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{
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// configure the acquisition with the main initialization values
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fpga_acquisition::configure_acquisition();
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return true;
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}
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bool fpga_acquisition::set_local_code(uint32_t PRN)
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{
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// select the code with the chosen PRN
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fpga_acquisition::fpga_configure_acquisition_local_code(
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&d_all_fft_codes[d_nsamples_total * (PRN - 1)]);
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//fpga_acquisition::fpga_configure_acquisition_local_code(
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// &d_all_fft_codes[0]);
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return true;
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}
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fpga_acquisition::fpga_acquisition(std::string device_name,
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uint32_t nsamples,
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uint32_t doppler_max,
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uint32_t nsamples_total, int64_t fs_in,
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uint32_t sampled_ms, uint32_t select_queue,
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lv_16sc_t *all_fft_codes)
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{
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//printf("AAA- sampled_ms = %d\n ", sampled_ms);
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uint32_t vector_length = nsamples_total; // * sampled_ms;
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//printf("AAA- vector_length = %d\n ", vector_length);
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// initial values
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d_device_name = device_name;
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//d_freq = freq;
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d_fs_in = fs_in;
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d_vector_length = vector_length;
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d_nsamples = nsamples; // number of samples not including padding
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d_select_queue = select_queue;
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d_nsamples_total = nsamples_total;
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d_doppler_max = doppler_max;
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d_doppler_step = 0;
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d_fd = 0; // driver descriptor
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d_map_base = nullptr; // driver memory map
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d_all_fft_codes = all_fft_codes;
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// open communication with HW accelerator
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if ((d_fd = open(d_device_name.c_str(), O_RDWR | O_SYNC)) == -1)
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{
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LOG(WARNING) << "Cannot open deviceio" << d_device_name;
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std::cout << "Acq: cannot open deviceio" << d_device_name << std::endl;
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}
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d_map_base = reinterpret_cast<volatile uint32_t *>(mmap(NULL, PAGE_SIZE,
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PROT_READ | PROT_WRITE, MAP_SHARED, d_fd, 0));
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if (d_map_base == reinterpret_cast<void *>(-1))
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{
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LOG(WARNING) << "Cannot map the FPGA acquisition module into user memory";
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std::cout << "Acq: cannot map deviceio" << d_device_name << std::endl;
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}
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// sanity check : check test register
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uint32_t writeval = TEST_REG_SANITY_CHECK;
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uint32_t readval;
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readval = fpga_acquisition::fpga_acquisition_test_register(writeval);
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if (writeval != readval)
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{
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LOG(WARNING) << "Acquisition test register sanity check failed";
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}
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else
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{
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LOG(INFO) << "Acquisition test register sanity check success!";
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//std::cout << "Acquisition test register sanity check success!" << std::endl;
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}
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fpga_acquisition::reset_acquisition();
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DLOG(INFO) << "Acquisition FPGA class created";
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}
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fpga_acquisition::~fpga_acquisition()
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{
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close_device();
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}
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bool fpga_acquisition::free()
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{
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return true;
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}
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uint32_t fpga_acquisition::fpga_acquisition_test_register(uint32_t writeval)
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{
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uint32_t readval;
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// write value to test register
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d_map_base[15] = writeval;
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// read value from test register
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readval = d_map_base[15];
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// return read value
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return readval;
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}
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void fpga_acquisition::fpga_configure_acquisition_local_code(lv_16sc_t fft_local_code[])
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{
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uint32_t local_code;
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uint32_t k, tmp, tmp2;
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uint32_t fft_data;
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// clear memory address counter
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//d_map_base[6] = LOCAL_CODE_CLEAR_MEM;
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d_map_base[9] = LOCAL_CODE_CLEAR_MEM;
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// write local code
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for (k = 0; k < d_vector_length; k++)
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{
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tmp = fft_local_code[k].real();
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tmp2 = fft_local_code[k].imag();
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//tmp = k;
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//tmp2 = k;
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//local_code = (tmp & SELECT_LSB) | ((tmp2 * SHL_8_BITS) & SELECT_MSB); // put together the real part and the imaginary part
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//fft_data = MEM_LOCAL_CODE_WR_ENABLE | (local_code & SELECT_16_BITS);
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//local_code = (tmp & SELECT_LSBits) | ((tmp2 * SHL_12_BITS) & SELECT_MSBbits); // put together the real part and the imaginary part
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local_code = (tmp & SELECT_LSBits) | ((tmp2 * SHL_16_BITS) & SELECT_MSBbits); // put together the real part and the imaginary part
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//fft_data = MEM_LOCAL_CODE_WR_ENABLE | (local_code & SELECT_24_BITS);
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fft_data = local_code & SELECT_32_BITS;
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d_map_base[6] = fft_data;
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//printf("debug local code %d real = %d imag = %d local_code = %d fft_data = %d\n", k, tmp, tmp2, local_code, fft_data);
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//printf("debug local code %d real = 0x%08X imag = 0x%08X local_code = 0x%08X fft_data = 0x%08X\n", k, tmp, tmp2, local_code, fft_data);
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}
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//printf("d_vector_length = %d\n", d_vector_length);
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//while(1);
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}
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void fpga_acquisition::run_acquisition(void)
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{
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// enable interrupts
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int32_t reenable = 1;
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write(d_fd, reinterpret_cast<void *>(&reenable), sizeof(int32_t));
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// launch the acquisition process
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//printf("launchin acquisition ...\n");
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d_map_base[8] = LAUNCH_ACQUISITION; // writing a 1 to reg 8 launches the acquisition process
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int32_t irq_count;
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ssize_t nb;
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// wait for interrupt
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nb = read(d_fd, &irq_count, sizeof(irq_count));
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//printf("interrupt received\n");
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if (nb != sizeof(irq_count))
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{
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printf("acquisition module Read failed to retrieve 4 bytes!\n");
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printf("acquisition module Interrupt number %d\n", irq_count);
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}
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}
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void fpga_acquisition::set_doppler_sweep(uint32_t num_sweeps)
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{
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float phase_step_rad_real;
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float phase_step_rad_int_temp;
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int32_t phase_step_rad_int;
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//int32_t doppler = static_cast<int32_t>(-d_doppler_max) + d_doppler_step * doppler_index;
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int32_t doppler = static_cast<int32_t>(-d_doppler_max);
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//float phase_step_rad = GPS_TWO_PI * (d_freq + doppler) / static_cast<float>(d_fs_in);
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float phase_step_rad = GPS_TWO_PI * (doppler) / static_cast<float>(d_fs_in);
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// The doppler step can never be outside the range -pi to +pi, otherwise there would be aliasing
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// The FPGA expects phase_step_rad between -1 (-pi) to +1 (+pi)
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// The FPGA also expects the phase to be negative since it produces cos(x) -j*sin(x)
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// while the gnss-sdr software (volk_gnsssdr_s32f_sincos_32fc) generates cos(x) + j*sin(x)
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phase_step_rad_real = phase_step_rad / (GPS_TWO_PI / 2);
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// avoid saturation of the fixed point representation in the fpga
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// (only the positive value can saturate due to the 2's complement representation)
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//printf("AAA phase_step_rad_real for initial doppler = %f\n", phase_step_rad_real);
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if (phase_step_rad_real >= 1.0)
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{
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phase_step_rad_real = MAX_PHASE_STEP_RAD;
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}
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//printf("AAA phase_step_rad_real for initial doppler after checking = %f\n", phase_step_rad_real);
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phase_step_rad_int_temp = phase_step_rad_real * POW_2_2; // * 2^2
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phase_step_rad_int = static_cast<int32_t>(phase_step_rad_int_temp * (POW_2_29)); // * 2^29 (in total it makes x2^31 in two steps to avoid the warnings
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//printf("AAA writing phase_step_rad_int for initial doppler = %d to d map base 3\n", phase_step_rad_int);
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d_map_base[3] = phase_step_rad_int;
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// repeat the calculation with the doppler step
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doppler = static_cast<int32_t>(d_doppler_step);
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phase_step_rad = GPS_TWO_PI * (doppler) / static_cast<float>(d_fs_in);
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phase_step_rad_real = phase_step_rad / (GPS_TWO_PI / 2);
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//printf("AAA phase_step_rad_real for doppler step = %f\n", phase_step_rad_real);
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if (phase_step_rad_real >= 1.0)
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{
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phase_step_rad_real = MAX_PHASE_STEP_RAD;
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}
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//printf("AAA phase_step_rad_real for doppler step after checking = %f\n", phase_step_rad_real);
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phase_step_rad_int_temp = phase_step_rad_real * POW_2_2; // * 2^2
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phase_step_rad_int = static_cast<int32_t>(phase_step_rad_int_temp * (POW_2_29)); // * 2^29 (in total it makes x2^31 in two steps to avoid the warnings
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//printf("AAA writing phase_step_rad_int for doppler step = %d to d map base 4\n", phase_step_rad_int);
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d_map_base[4] = phase_step_rad_int;
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//printf("AAA writing num sweeps to d map base 5 = %d\n", num_sweeps);
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d_map_base[5] = num_sweeps;
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}
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void fpga_acquisition::set_doppler_sweep_debug(uint32_t num_sweeps, uint32_t doppler_index)
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{
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float phase_step_rad_real;
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float phase_step_rad_int_temp;
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int32_t phase_step_rad_int;
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int32_t doppler = -static_cast<int32_t>(d_doppler_max) + d_doppler_step * doppler_index;
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//int32_t doppler = static_cast<int32_t>(-d_doppler_max);
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//float phase_step_rad = GPS_TWO_PI * (d_freq + doppler) / static_cast<float>(d_fs_in);
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float phase_step_rad = GPS_TWO_PI * (doppler) / static_cast<float>(d_fs_in);
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// The doppler step can never be outside the range -pi to +pi, otherwise there would be aliasing
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// The FPGA expects phase_step_rad between -1 (-pi) to +1 (+pi)
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// The FPGA also expects the phase to be negative since it produces cos(x) -j*sin(x)
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// while the gnss-sdr software (volk_gnsssdr_s32f_sincos_32fc) generates cos(x) + j*sin(x)
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phase_step_rad_real = phase_step_rad / (GPS_TWO_PI / 2);
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// avoid saturation of the fixed point representation in the fpga
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// (only the positive value can saturate due to the 2's complement representation)
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//printf("AAAh phase_step_rad_real for initial doppler = %f\n", phase_step_rad_real);
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if (phase_step_rad_real >= 1.0)
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{
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phase_step_rad_real = MAX_PHASE_STEP_RAD;
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}
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//printf("AAAh phase_step_rad_real for initial doppler after checking = %f\n", phase_step_rad_real);
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phase_step_rad_int_temp = phase_step_rad_real * POW_2_2; // * 2^2
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phase_step_rad_int = static_cast<int32_t>(phase_step_rad_int_temp * (POW_2_29)); // * 2^29 (in total it makes x2^31 in two steps to avoid the warnings
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//printf("AAAh writing phase_step_rad_int for initial doppler = %d to d map base 3\n", phase_step_rad_int);
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d_map_base[3] = phase_step_rad_int;
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// repeat the calculation with the doppler step
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doppler = static_cast<int32_t>(d_doppler_step);
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phase_step_rad = GPS_TWO_PI * (doppler) / static_cast<float>(d_fs_in);
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phase_step_rad_real = phase_step_rad / (GPS_TWO_PI / 2);
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//printf("AAAh phase_step_rad_real for doppler step = %f\n", phase_step_rad_real);
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if (phase_step_rad_real >= 1.0)
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{
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phase_step_rad_real = MAX_PHASE_STEP_RAD;
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}
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//printf("AAAh phase_step_rad_real for doppler step after checking = %f\n", phase_step_rad_real);
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phase_step_rad_int_temp = phase_step_rad_real * POW_2_2; // * 2^2
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phase_step_rad_int = static_cast<int32_t>(phase_step_rad_int_temp * (POW_2_29)); // * 2^29 (in total it makes x2^31 in two steps to avoid the warnings
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//printf("AAAh writing phase_step_rad_int for doppler step = %d to d map base 4\n", phase_step_rad_int);
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d_map_base[4] = phase_step_rad_int;
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//printf("AAAh writing num sweeps to d map base 5 = %d\n", num_sweeps);
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d_map_base[5] = num_sweeps;
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}
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void fpga_acquisition::configure_acquisition()
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{
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//printf("AAA d_select_queue = %d\n", d_select_queue);
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d_map_base[0] = d_select_queue;
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//printf("AAA writing d_vector_length = %d to d map base 1\n ", d_vector_length);
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d_map_base[1] = d_vector_length;
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//printf("AAA writing d_nsamples = %d to d map base 2\n ", d_nsamples);
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d_map_base[2] = d_nsamples;
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//printf("AAA writing LOG2 d_vector_length = %d to d map base 7\n ", (int)log2((float)d_vector_length));
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d_map_base[7] = static_cast<int32_t>(log2(static_cast<float>(d_vector_length))); // log2 FFTlength
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//printf("acquisition debug vector length = %d\n", d_vector_length);
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//printf("acquisition debug vector length = %d\n", (int)log2((float)d_vector_length));
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}
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void fpga_acquisition::set_phase_step(uint32_t doppler_index)
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{
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float phase_step_rad_real;
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float phase_step_rad_int_temp;
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int32_t phase_step_rad_int;
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int32_t doppler = -static_cast<int32_t>(d_doppler_max) + d_doppler_step * doppler_index;
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//float phase_step_rad = GPS_TWO_PI * (d_freq + doppler) / static_cast<float>(d_fs_in);
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float phase_step_rad = GPS_TWO_PI * (doppler) / static_cast<float>(d_fs_in);
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// The doppler step can never be outside the range -pi to +pi, otherwise there would be aliasing
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// The FPGA expects phase_step_rad between -1 (-pi) to +1 (+pi)
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// The FPGA also expects the phase to be negative since it produces cos(x) -j*sin(x)
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// while the gnss-sdr software (volk_gnsssdr_s32f_sincos_32fc) generates cos(x) + j*sin(x)
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phase_step_rad_real = phase_step_rad / (GPS_TWO_PI / 2);
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// avoid saturation of the fixed point representation in the fpga
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// (only the positive value can saturate due to the 2's complement representation)
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//printf("AAA+ phase_step_rad_real = %f\n", phase_step_rad_real);
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if (phase_step_rad_real >= 1.0)
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{
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phase_step_rad_real = MAX_PHASE_STEP_RAD;
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}
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//printf("AAA+ phase_step_rad_real after checking = %f\n", phase_step_rad_real);
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phase_step_rad_int_temp = phase_step_rad_real * POW_2_2; // * 2^2
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phase_step_rad_int = static_cast<int32_t>(phase_step_rad_int_temp * (POW_2_29)); // * 2^29 (in total it makes x2^31 in two steps to avoid the warnings
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//printf("writing phase_step_rad_int = %d to d_map_base 3\n", phase_step_rad_int);
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d_map_base[3] = phase_step_rad_int;
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}
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void fpga_acquisition::read_acquisition_results(uint32_t *max_index,
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float *max_magnitude, uint64_t *initial_sample, float *power_sum, uint32_t *doppler_index)
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{
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uint64_t initial_sample_tmp = 0;
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uint32_t readval = 0;
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uint64_t readval_long = 0;
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uint64_t readval_long_shifted = 0;
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readval = d_map_base[1];
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initial_sample_tmp = readval;
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readval_long = d_map_base[2];
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readval_long_shifted = readval_long << 32; // 2^32
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initial_sample_tmp = initial_sample_tmp + readval_long_shifted; // 2^32
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//printf("----------------------------------------------------------------> acq initial sample TOTAL = %llu\n", initial_sample_tmp);
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*initial_sample = initial_sample_tmp;
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readval = d_map_base[6];
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*max_magnitude = static_cast<float>(readval);
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//printf("read max_magnitude dmap 2 = %d\n", readval);
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readval = d_map_base[4];
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*power_sum = static_cast<float>(readval);
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//printf("read power sum dmap 4 = %d\n", readval);
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readval = d_map_base[5]; // read doppler index
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*doppler_index = readval;
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//printf("read doppler_index dmap 5 = %d\n", readval);
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readval = d_map_base[3];
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*max_index = readval;
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//printf("read max index dmap 3 = %d\n", readval);
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}
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void fpga_acquisition::block_samples()
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{
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d_map_base[14] = 1; // block the samples
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}
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void fpga_acquisition::unblock_samples()
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{
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d_map_base[14] = 0; // unblock the samples
|
|
}
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void fpga_acquisition::close_device()
|
|
{
|
|
uint32_t *aux = const_cast<uint32_t *>(d_map_base);
|
|
if (munmap(static_cast<void *>(aux), PAGE_SIZE) == -1)
|
|
{
|
|
printf("Failed to unmap memory uio\n");
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|
}
|
|
close(d_fd);
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|
}
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void fpga_acquisition::reset_acquisition(void)
|
|
{
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|
d_map_base[8] = RESET_ACQUISITION; // writing a 2 to d_map_base[8] resets the multicorrelator
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}
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