mirror of https://github.com/gnss-sdr/gnss-sdr
207 lines
6.4 KiB
C++
207 lines
6.4 KiB
C++
/*!
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* \file gps_l1_ca_dll_pll_tracking_fpga.h
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* \brief Interface of a code DLL + carrier PLL tracking block
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* \author Marc Majoral, 2018. marc.majoral(at)cttc.es
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* Carlos Aviles, 2010. carlos.avilesr(at)googlemail.com
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* Javier Arribas, 2011. jarribas(at)cttc.es
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* Cillian O'Driscoll, 2017. cillian.odriscoll(at)gmail.com
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*
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* Code DLL + carrier PLL according to the algorithms described in:
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* K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen,
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* A Software-Defined GPS and Galileo Receiver. A Single-Frequency Approach,
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* Birkhauser, 2007
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*
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* -------------------------------------------------------------------------
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*
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* Copyright (C) 2010-2015 (see AUTHORS file for a list of contributors)
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*
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* GNSS-SDR is a software defined Global Navigation
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* Satellite Systems receiver
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*
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* This file is part of GNSS-SDR.
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*
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* GNSS-SDR is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* GNSS-SDR is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNSS-SDR. If not, see <http://www.gnu.org/licenses/>.
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*
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* -------------------------------------------------------------------------
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*/
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#ifndef GNSS_SDR_DLL_PLL_VEML_TRACKING_FPGA_H
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#define GNSS_SDR_DLL_PLL_VEML_TRACKING_FPGA_H
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#include "dll_pll_conf_fpga.h"
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#include "gnss_synchro.h"
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#include "tracking_2nd_DLL_filter.h"
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#include "tracking_2nd_PLL_filter.h"
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#include "fpga_multicorrelator.h"
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#include <gnuradio/block.h>
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#include <fstream>
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#include <string>
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#include <map>
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#include <queue>
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#include <boost/circular_buffer.hpp>
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#include "fpga_multicorrelator.h"
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class dll_pll_veml_tracking_fpga;
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typedef boost::shared_ptr<dll_pll_veml_tracking_fpga>
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dll_pll_veml_tracking_fpga_sptr;
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dll_pll_veml_tracking_fpga_sptr dll_pll_veml_make_tracking_fpga(const Dll_Pll_Conf_Fpga &conf_);
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/*!
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* \brief This class implements a DLL + PLL tracking loop block
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*/
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class dll_pll_veml_tracking_fpga : public gr::block
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{
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public:
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~dll_pll_veml_tracking_fpga();
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void set_channel(uint32_t channel);
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void set_gnss_synchro(Gnss_Synchro *p_gnss_synchro);
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void start_tracking();
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void stop_tracking();
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int general_work(int noutput_items, gr_vector_int &ninput_items,
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gr_vector_const_void_star &input_items, gr_vector_void_star &output_items);
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void reset(void);
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private:
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friend dll_pll_veml_tracking_fpga_sptr dll_pll_veml_make_tracking_fpga(const Dll_Pll_Conf_Fpga &conf_);
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dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &conf_);
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void msg_handler_preamble_index(pmt::pmt_t msg);
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bool cn0_and_tracking_lock_status(double coh_integration_time_s);
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bool acquire_secondary();
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void run_dll_pll();
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void update_tracking_vars();
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void clear_tracking_vars();
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void save_correlation_results();
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void log_data(bool integrating);
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int32_t save_matfile();
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// tracking configuration vars
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Dll_Pll_Conf_Fpga trk_parameters;
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//dllpllconf_fpga_t trk_parameters;
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bool d_veml;
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bool d_cloop;
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uint32_t d_channel;
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Gnss_Synchro *d_acquisition_gnss_synchro;
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//Signal parameters
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bool d_secondary;
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bool interchange_iq;
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double d_signal_carrier_freq;
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double d_code_period;
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double d_code_chip_rate;
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uint32_t d_secondary_code_length;
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uint32_t d_code_length_chips;
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uint32_t d_code_samples_per_chip; // All signals have 1 sample per chip code except Gal. E1 which has 2 (CBOC disabled) or 12 (CBOC enabled)
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int32_t d_symbols_per_bit;
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std::string systemName;
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std::string signal_type;
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std::string *d_secondary_code_string;
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std::string signal_pretty_name;
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int32_t *d_gps_l1ca_preambles_symbols;
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boost::circular_buffer<float> d_symbol_history;
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//tracking state machine
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int32_t d_state;
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bool d_synchonizing;
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//Integration period in samples
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int32_t d_correlation_length_ms;
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int32_t d_n_correlator_taps;
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float *d_local_code_shift_chips;
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float *d_prompt_data_shift;
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std::shared_ptr<fpga_multicorrelator_8sc> multicorrelator_fpga;
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gr_complex *d_correlator_outs;
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gr_complex *d_Very_Early;
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gr_complex *d_Early;
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gr_complex *d_Prompt;
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gr_complex *d_Late;
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gr_complex *d_Very_Late;
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bool d_enable_extended_integration;
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int32_t d_extend_correlation_symbols_count;
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int32_t d_current_symbol;
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gr_complex d_VE_accu;
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gr_complex d_E_accu;
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gr_complex d_P_accu;
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gr_complex d_L_accu;
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gr_complex d_VL_accu;
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gr_complex d_last_prompt;
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gr_complex *d_Prompt_Data;
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double d_code_phase_step_chips;
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double d_carrier_phase_step_rad;
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// remaining code phase and carrier phase between tracking loops
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double d_rem_code_phase_samples;
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double d_rem_carr_phase_rad;
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// PLL and DLL filter library
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Tracking_2nd_DLL_filter d_code_loop_filter;
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Tracking_2nd_PLL_filter d_carrier_loop_filter;
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// acquisition
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double d_acq_code_phase_samples;
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double d_acq_carrier_doppler_hz;
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// tracking vars
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double d_carr_error_hz;
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double d_carr_error_filt_hz;
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double d_code_error_chips;
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double d_code_error_filt_chips;
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double d_K_blk_samples;
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double d_code_freq_chips;
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double d_carrier_doppler_hz;
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double d_acc_carrier_phase_rad;
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double d_rem_code_phase_chips;
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double d_code_phase_samples;
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double T_chip_seconds;
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double T_prn_seconds;
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double T_prn_samples;
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double K_blk_samples;
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// PRN period in samples
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int32_t d_current_prn_length_samples;
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// processing samples counters
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uint64_t d_sample_counter;
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uint64_t d_acq_sample_stamp;
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uint64_t d_absolute_samples_offset;
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// CN0 estimation and lock detector
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int32_t d_cn0_estimation_counter;
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int32_t d_carrier_lock_fail_counter;
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double d_carrier_lock_test;
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double d_CN0_SNV_dB_Hz;
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double d_carrier_lock_threshold;
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std::deque<gr_complex> d_Prompt_buffer_deque;
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gr_complex *d_Prompt_buffer;
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// file dump
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std::ofstream d_dump_file;
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// extra
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int32_t d_correlation_length_samples;
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int32_t d_next_prn_length_samples;
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uint64_t d_sample_counter_next;
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uint32_t d_pull_in = 0U;
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};
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#endif //GNSS_SDR_DLL_PLL_VEML_TRACKING_FPGA_H
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