mirror of https://github.com/gnss-sdr/gnss-sdr
77 lines
3.2 KiB
C++
77 lines
3.2 KiB
C++
/*!
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* \file acq_conf_fpga.cc
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* \brief Class that contains all the configuration parameters for generic
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* acquisition block based on the PCPS algorithm running in the FPGA.
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* \author Marc Majoral, 2022. mmajoral(at)cttc.es
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*
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* -----------------------------------------------------------------------------
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*
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* GNSS-SDR is a Global Navigation Satellite System software-defined receiver.
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* This file is part of GNSS-SDR.
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*
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* Copyright (C) 2010-2022 (see AUTHORS file for a list of contributors)
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* SPDX-License-Identifier: GPL-3.0-or-later
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*
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* -----------------------------------------------------------------------------
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*/
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#include "acq_conf_fpga.h"
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#include "item_type_helpers.h"
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#include "uio_fpga.h"
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#include <glog/logging.h>
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#include <cmath>
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#include <iostream>
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#include <utility>
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void Acq_Conf_Fpga::SetFromConfiguration(const ConfigurationInterface *configuration,
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const std::string &role, uint32_t sel_queue_fpga, uint32_t blk_exp, uint32_t downsampling_factor_default, double chip_rate, double code_length_chips)
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{
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// sampling frequency
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const int64_t fs_in_deprecated = configuration->property("GNSS-SDR.internal_fs_hz", fs_in);
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fs_in = configuration->property("GNSS-SDR.internal_fs_sps", fs_in_deprecated);
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// max doppler
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doppler_max = configuration->property(role + ".doppler_max", doppler_max);
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// downsampling factor
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downsampling_factor = configuration->property(role + ".downsampling_factor", downsampling_factor_default);
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fs_in = fs_in / downsampling_factor;
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// code length in samples
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code_length = static_cast<uint32_t>(std::round(static_cast<double>(fs_in) / (chip_rate / code_length_chips)));
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// The FPGA can only use FFT lengths that are a power of two.
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float nbits = ceilf(log2f(static_cast<float>(code_length) * 2.0F));
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samples_per_code = pow(2, nbits);
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// repeat satellite
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repeat_satellite = configuration->property(role + ".repeat_satellite", false);
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// FPGA buffer number
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select_queue_Fpga = configuration->property(role + ".select_queue_Fpga", sel_queue_fpga);
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// UIO device file
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std::string device_io_name;
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// find the uio device file corresponding to the acquisition
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if (find_uio_dev_file_name(device_io_name, acquisition_device_name, 0) < 0)
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{
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std::cout << "Cannot find the FPGA uio device file corresponding to device name " << acquisition_device_name << std::endl;
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throw std::exception();
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}
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device_name = std::move(device_io_name);
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// exclusion limit
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excludelimit = static_cast<unsigned int>(1 + ceil((1.0 / chip_rate) * static_cast<float>(fs_in)));
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// acquisition step 2 parameters
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num_doppler_bins_step2 = configuration->property(role + ".second_nbins", num_doppler_bins_step2);
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doppler_step2 = configuration->property(role + ".second_doppler_step", doppler_step2);
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doppler_step = configuration->property(role + ".doppler_step", doppler_step);
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make_2_steps = configuration->property(role + ".make_two_steps", make_2_steps);
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max_num_acqs = configuration->property(role + ".max_num_acqs", 2);
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// reference for the FPGA FFT-IFFT attenuation factor
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total_block_exp = configuration->property(role + ".total_block_exp", blk_exp);
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}
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