mirror of
https://github.com/gnss-sdr/gnss-sdr
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294 lines
10 KiB
C++
294 lines
10 KiB
C++
/*!
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* \file galileo_e5a_pcps_acquisition_fpga.cc
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* \brief Adapts a PCPS acquisition block to an AcquisitionInterface for
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* Galileo E5a data and pilot Signals for the FPGA
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* \author Marc Majoral, 2019. mmajoral(at)cttc.es
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*
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* -----------------------------------------------------------------------------
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*
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* GNSS-SDR is a Global Navigation Satellite System software-defined receiver.
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* This file is part of GNSS-SDR.
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*
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* Copyright (C) 2010-2020 (see AUTHORS file for a list of contributors)
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* SPDX-License-Identifier: GPL-3.0-or-later
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*
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* -----------------------------------------------------------------------------
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*/
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#include "galileo_e5a_pcps_acquisition_fpga.h"
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#include "Galileo_E5a.h"
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#include "configuration_interface.h"
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#include "galileo_e5_signal_replica.h"
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#include "gnss_sdr_fft.h"
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#include "gnss_sdr_flags.h"
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#include "uio_fpga.h"
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#include <glog/logging.h>
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#include <gnuradio/gr_complex.h> // for gr_complex
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#include <volk/volk.h> // for volk_32fc_conjugate_32fc
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#include <volk_gnsssdr/volk_gnsssdr_alloc.h>
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#include <algorithm> // for copy_n
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#include <cmath> // for abs, pow, floor
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#include <complex> // for complex
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GalileoE5aPcpsAcquisitionFpga::GalileoE5aPcpsAcquisitionFpga(
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const ConfigurationInterface* configuration,
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const std::string& role,
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unsigned int in_streams,
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unsigned int out_streams) : role_(role),
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in_streams_(in_streams),
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out_streams_(out_streams)
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{
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pcpsconf_fpga_t acq_parameters;
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const std::string default_dump_filename("../data/acquisition.dat");
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DLOG(INFO) << "Role " << role;
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int64_t fs_in_deprecated = configuration->property("GNSS-SDR.internal_fs_hz", 32000000);
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int64_t fs_in = configuration->property("GNSS-SDR.internal_fs_sps", fs_in_deprecated);
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acq_parameters.repeat_satellite = configuration->property(role + ".repeat_satellite", false);
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DLOG(INFO) << role << " satellite repeat = " << acq_parameters.repeat_satellite;
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uint32_t downsampling_factor = configuration->property(role + ".downsampling_factor", 1);
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acq_parameters.downsampling_factor = downsampling_factor;
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fs_in = fs_in / downsampling_factor;
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acq_parameters.fs_in = fs_in;
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doppler_max_ = configuration->property(role + ".doppler_max", 5000);
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if (FLAGS_doppler_max != 0)
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{
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doppler_max_ = FLAGS_doppler_max;
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}
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acq_parameters.doppler_max = doppler_max_;
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acq_pilot_ = configuration->property(role + ".acquire_pilot", false);
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acq_iq_ = configuration->property(role + ".acquire_iq", false);
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if (acq_iq_)
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{
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acq_pilot_ = false;
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}
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auto code_length = static_cast<uint32_t>(std::round(static_cast<double>(fs_in) / GALILEO_E5A_CODE_CHIP_RATE_CPS * static_cast<double>(GALILEO_E5A_CODE_LENGTH_CHIPS)));
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acq_parameters.code_length = code_length;
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// The FPGA can only use FFT lengths that are a power of two.
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float nbits = ceilf(log2f(static_cast<float>(code_length) * 2.0F));
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uint32_t nsamples_total = pow(2, nbits);
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uint32_t select_queue_Fpga = configuration->property(role + ".select_queue_Fpga", 1);
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acq_parameters.select_queue_Fpga = select_queue_Fpga;
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// UIO device file
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std::string device_io_name;
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// find the uio device file corresponding to the acquisition
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if (find_uio_dev_file_name(device_io_name, acquisition_device_name, 0) < 0)
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{
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std::cout << "Cannot find the FPGA uio device file corresponding to device name " << acquisition_device_name << std::endl;
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throw std::exception();
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}
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acq_parameters.device_name = device_io_name;
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acq_parameters.samples_per_code = nsamples_total;
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acq_parameters.excludelimit = static_cast<unsigned int>(1 + ceil((1.0 / GALILEO_E5A_CODE_CHIP_RATE_CPS) * static_cast<float>(fs_in)));
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// compute all the GALILEO E5 PRN Codes (this is done only once in the class constructor in order to avoid re-computing the PRN codes every time
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// a channel is assigned)
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auto fft_if = gnss_fft_fwd_make_unique(nsamples_total); // Direct FFT
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volk_gnsssdr::vector<std::complex<float>> code(nsamples_total);
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volk_gnsssdr::vector<std::complex<float>> fft_codes_padded(nsamples_total);
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d_all_fft_codes_ = std::vector<uint32_t>(nsamples_total * GALILEO_E5A_NUMBER_OF_CODES); // memory containing all the possible fft codes for PRN 0 to 32
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float max; // temporary maxima search
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int32_t tmp;
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int32_t tmp2;
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int32_t local_code;
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int32_t fft_data;
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for (uint32_t PRN = 1; PRN <= GALILEO_E5A_NUMBER_OF_CODES; PRN++)
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{
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std::array<char, 3> signal_;
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signal_[0] = '5';
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signal_[2] = '\0';
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if (acq_iq_)
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{
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signal_[1] = 'X';
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}
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else if (acq_pilot_)
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{
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signal_[1] = 'Q';
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}
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else
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{
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signal_[1] = 'I';
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}
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galileo_e5_a_code_gen_complex_sampled(code, PRN, signal_, fs_in, 0);
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for (uint32_t s = code_length; s < 2 * code_length; s++)
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{
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code[s] = code[s - code_length];
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}
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// fill in zero padding
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for (uint32_t s = 2 * code_length; s < nsamples_total; s++)
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{
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code[s] = std::complex<float>(0.0, 0.0);
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}
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std::copy_n(code.data(), nsamples_total, fft_if->get_inbuf()); // copy to FFT buffer
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fft_if->execute(); // Run the FFT of local code
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volk_32fc_conjugate_32fc(fft_codes_padded.data(), fft_if->get_outbuf(), nsamples_total); // conjugate values
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max = 0; // initialize maximum value
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for (uint32_t i = 0; i < nsamples_total; i++) // search for maxima
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{
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if (std::abs(fft_codes_padded[i].real()) > max)
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{
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max = std::abs(fft_codes_padded[i].real());
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}
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if (std::abs(fft_codes_padded[i].imag()) > max)
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{
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max = std::abs(fft_codes_padded[i].imag());
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}
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}
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// map the FFT to the dynamic range of the fixed point values an copy to buffer containing all FFTs
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// and package codes in a format that is ready to be written to the FPGA
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for (uint32_t i = 0; i < nsamples_total; i++)
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{
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tmp = static_cast<int32_t>(floor(fft_codes_padded[i].real() * (pow(2, quant_bits_local_code - 1) - 1) / max));
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tmp2 = static_cast<int32_t>(floor(fft_codes_padded[i].imag() * (pow(2, quant_bits_local_code - 1) - 1) / max));
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local_code = (tmp & select_lsbits) | ((tmp2 * shl_code_bits) & select_msbits); // put together the real part and the imaginary part
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fft_data = local_code & select_all_code_bits;
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d_all_fft_codes_[i + (nsamples_total * (PRN - 1))] = fft_data;
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}
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}
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acq_parameters.all_fft_codes = d_all_fft_codes_.data();
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// reference for the FPGA FFT-IFFT attenuation factor
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acq_parameters.total_block_exp = configuration->property(role + ".total_block_exp", 13);
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acq_parameters.num_doppler_bins_step2 = configuration->property(role + ".second_nbins", 4);
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acq_parameters.doppler_step2 = configuration->property(role + ".second_doppler_step", static_cast<float>(125.0));
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acq_parameters.make_2_steps = configuration->property(role + ".make_two_steps", false);
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acq_parameters.max_num_acqs = configuration->property(role + ".max_num_acqs", 2);
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acquisition_fpga_ = pcps_make_acquisition_fpga(acq_parameters);
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channel_ = 0;
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doppler_step_ = 0;
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gnss_synchro_ = nullptr;
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if (in_streams_ > 1)
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{
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LOG(ERROR) << "This implementation only supports one input stream";
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}
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if (out_streams_ > 0)
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{
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LOG(ERROR) << "This implementation does not provide an output stream";
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}
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}
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void GalileoE5aPcpsAcquisitionFpga::stop_acquisition()
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{
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// stop the acquisition and the other FPGA modules.
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acquisition_fpga_->stop_acquisition();
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}
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void GalileoE5aPcpsAcquisitionFpga::set_threshold(float threshold)
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{
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DLOG(INFO) << "Channel " << channel_ << " Threshold = " << threshold;
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acquisition_fpga_->set_threshold(threshold);
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}
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void GalileoE5aPcpsAcquisitionFpga::set_doppler_max(unsigned int doppler_max)
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{
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doppler_max_ = doppler_max;
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acquisition_fpga_->set_doppler_max(doppler_max_);
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}
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void GalileoE5aPcpsAcquisitionFpga::set_doppler_step(unsigned int doppler_step)
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{
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doppler_step_ = doppler_step;
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acquisition_fpga_->set_doppler_step(doppler_step_);
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}
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void GalileoE5aPcpsAcquisitionFpga::set_doppler_center(int doppler_center)
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{
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doppler_center_ = doppler_center;
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acquisition_fpga_->set_doppler_center(doppler_center_);
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}
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void GalileoE5aPcpsAcquisitionFpga::set_gnss_synchro(Gnss_Synchro* gnss_synchro)
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{
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gnss_synchro_ = gnss_synchro;
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acquisition_fpga_->set_gnss_synchro(gnss_synchro_);
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}
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signed int GalileoE5aPcpsAcquisitionFpga::mag()
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{
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return acquisition_fpga_->mag();
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}
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void GalileoE5aPcpsAcquisitionFpga::init()
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{
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acquisition_fpga_->init();
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}
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void GalileoE5aPcpsAcquisitionFpga::set_local_code()
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{
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acquisition_fpga_->set_local_code();
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}
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void GalileoE5aPcpsAcquisitionFpga::reset()
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{
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acquisition_fpga_->set_active(true);
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}
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void GalileoE5aPcpsAcquisitionFpga::set_state(int state)
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{
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acquisition_fpga_->set_state(state);
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}
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void GalileoE5aPcpsAcquisitionFpga::connect(gr::top_block_sptr top_block)
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{
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if (top_block)
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{ /* top_block is not null */
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};
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// Nothing to connect
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}
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void GalileoE5aPcpsAcquisitionFpga::disconnect(gr::top_block_sptr top_block)
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{
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if (top_block)
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{ /* top_block is not null */
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};
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// Nothing to disconnect
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}
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gr::basic_block_sptr GalileoE5aPcpsAcquisitionFpga::get_left_block()
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{
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return nullptr;
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}
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gr::basic_block_sptr GalileoE5aPcpsAcquisitionFpga::get_right_block()
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{
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return nullptr;
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}
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