mirror of https://github.com/gnss-sdr/gnss-sdr
102 lines
2.8 KiB
C++
102 lines
2.8 KiB
C++
/*!
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* \file dll_pll_conf_fpga.h
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* \brief Class that contains all the configuration parameters for generic
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* tracking block based on a DLL and a PLL for the FPGA.
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* \author Marc Majoral, 2019. mmajoral(at)cttc.cat
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* \author Javier Arribas, 2018. jarribas(at)cttc.es
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*
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* Class that contains all the configuration parameters for generic tracking block based on a DLL and a PLL.
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*
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* -------------------------------------------------------------------------
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*
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* Copyright (C) 2010-2019 (see AUTHORS file for a list of contributors)
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*
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* GNSS-SDR is a software defined Global Navigation
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* Satellite Systems receiver
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*
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* This file is part of GNSS-SDR.
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*
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* SPDX-License-Identifier: GPL-3.0-or-later
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*
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* -------------------------------------------------------------------------
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*/
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#ifndef GNSS_SDR_DLL_PLL_CONF_FPGA_H
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#define GNSS_SDR_DLL_PLL_CONF_FPGA_H
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#include "configuration_interface.h"
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#include <cstdint>
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#include <string>
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class Dll_Pll_Conf_Fpga
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{
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public:
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Dll_Pll_Conf_Fpga();
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void SetFromConfiguration(ConfigurationInterface* configuration, const std::string& role);
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/* DLL/PLL tracking configuration */
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std::string device_name;
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std::string dump_filename;
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double fs_in;
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double carrier_lock_th;
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float pll_pull_in_bw_hz;
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float dll_pull_in_bw_hz;
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float fll_bw_hz;
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float pll_bw_hz;
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float dll_bw_hz;
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float pll_bw_narrow_hz;
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float dll_bw_narrow_hz;
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float early_late_space_chips;
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float very_early_late_space_chips;
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float early_late_space_narrow_chips;
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float very_early_late_space_narrow_chips;
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float slope;
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float spc;
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float y_intercept;
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float cn0_smoother_alpha;
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float carrier_lock_test_smoother_alpha;
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uint32_t pull_in_time_s; // signed integer, when pull in time is not yet reached it has to be compared against a negative number
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uint32_t bit_synchronization_time_limit_s;
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uint32_t vector_length;
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uint32_t smoother_length;
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uint32_t dev_file_num;
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uint32_t num_prev_assigned_ch;
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uint32_t code_length_chips;
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uint32_t code_samples_per_chip;
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uint32_t extend_fpga_integration_periods;
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uint32_t fpga_integration_period;
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int32_t fll_filter_order;
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int32_t pll_filter_order;
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int32_t dll_filter_order;
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int32_t extend_correlation_symbols;
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int32_t cn0_samples;
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int32_t cn0_min;
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int32_t max_code_lock_fail;
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int32_t max_carrier_lock_fail;
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int32_t cn0_smoother_samples;
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int32_t carrier_lock_test_smoother_samples;
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// int32_t max_lock_fail;
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int32_t* ca_codes;
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int32_t* data_codes;
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char signal[3];
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char system;
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bool extended_correlation_in_fpga;
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bool track_pilot;
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bool enable_doppler_correction;
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bool enable_fll_pull_in;
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bool enable_fll_steady_state;
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bool carrier_aiding;
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bool high_dyn;
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bool dump;
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bool dump_mat;
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};
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#endif
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