mirror of https://github.com/gnss-sdr/gnss-sdr
256 lines
9.7 KiB
C++
256 lines
9.7 KiB
C++
/*!
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* \file fpga_multicorrelator.h
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* \brief FPGA vector correlator class
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* \authors <ul>
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* <li> Marc Majoral, 2019. mmajoral(at)cttc.cat
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* <li> Javier Arribas, 2019. jarribas(at)cttc.es
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* </ul>
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*
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* Class that controls and executes a highly optimized vector correlator
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* class in the FPGA
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*
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* -----------------------------------------------------------------------------
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*
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* GNSS-SDR is a Global Navigation Satellite System software-defined receiver.
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* This file is part of GNSS-SDR.
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*
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* Copyright (C) 2010-2020 (see AUTHORS file for a list of contributors)
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* SPDX-License-Identifier: GPL-3.0-or-later
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*
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* -----------------------------------------------------------------------------
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*/
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#ifndef GNSS_SDR_FPGA_MULTICORRELATOR_H
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#define GNSS_SDR_FPGA_MULTICORRELATOR_H
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#include <gnuradio/block.h>
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#include <volk_gnsssdr/volk_gnsssdr_alloc.h>
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#include <cstdint>
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#include <string>
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/** \addtogroup Tracking
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* \{ */
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/** \addtogroup Tracking_libs
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* \{ */
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/*!
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* \brief Class that implements carrier wipe-off and correlators.
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*/
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class Fpga_Multicorrelator_8sc
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{
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public:
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/*!
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* \brief Constructor
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*/
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Fpga_Multicorrelator_8sc(int32_t n_correlators,
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int32_t *ca_codes,
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int32_t *data_codes,
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uint32_t code_length_chips,
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bool track_pilot,
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uint32_t code_samples_per_chip);
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/*!
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* \brief Destructor
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*/
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~Fpga_Multicorrelator_8sc();
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/*!
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* \brief Configure pointers to the FPGA multicorrelator results
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*/
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void set_output_vectors(gr_complex *corr_out, gr_complex *Prompt_Data);
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/*!
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* \brief Configure the local code in the FPGA multicorrelator
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*/
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void set_local_code_and_taps(
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float *shifts_chips, float *prompt_data_shift, int32_t PRN);
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/*!
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* \brief Configure code phase and code rate parameters in the FPGA
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*/
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void update_local_code();
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/*!
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* \brief Perform a multicorrelation
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*/
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void Carrier_wipeoff_multicorrelator_resampler(
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float rem_carrier_phase_in_rad,
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float phase_step_rad,
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float carrier_phase_rate_step_rad,
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float rem_code_phase_chips,
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float code_phase_step_chips,
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float code_phase_rate_step_chips,
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int32_t signal_length_samples);
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/*!
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* \brief Stop the correlation process in the FPGA and free code phase and code rate parameters
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*/
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bool free();
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/*!
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* \brief Open the FPGA device driver
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*/
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void open_channel(const std::string &device_io_name, uint32_t channel);
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/*!
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* \brief Set the initial sample number where the tracking process begins
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*/
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void set_initial_sample(uint64_t samples_offset);
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/*!
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* \brief Read the sample counter in the FPGA
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*/
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uint64_t read_sample_counter();
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/*!
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* \brief Start the tracking process in the FPGA
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*/
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void lock_channel();
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/*!
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* \brief finish the tracking process in the FPGA
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*/
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void unlock_channel();
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/*!
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* \brief Set the secondary code length in the FPGA. This is only used when extended coherent integration
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* is enabled in the FPGA. If tracking the pilot is enabled then secondary_code_0_length is the length of the pilot
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* secondary code and secondary_code_1_length is the length of the data secondary code. If tracking the pilot is disabled
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* then secondary_code_0_length is the length of the data secondary code, and secondary_code_1_length must be set to zero.
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*/
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void set_secondary_code_lengths(uint32_t secondary_code_0_length, uint32_t secondary_code_1_length);
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/*!
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* \brief Initialize the secondary code in the FPGA. If tracking the pilot is enabled then the pilot secondary code is
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* configured when secondary_code = 0 and the data secondary code is configured when secondary_code = 1. If tracking the
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* pilot is disabled then the data secondary code is configured when secondary code = 0.
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*/
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void initialize_secondary_code(uint32_t secondary_code, std::string *secondary_code_string);
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/*!
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* \brief Set the PRN length in the FPGA in number of samples. This function is only used then extended coherent integration is enabled in the
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* FPGA. The FPGA allows for the configuration of two PRN lengths. When the length of the extended coherent integration is bigger than the
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* length of the PRN code, the FPGA uses the first_length_secondary_code as the length of the PRN code immediately following the beginning
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* of the extended coherent integration, and the next_length_secondary_code as the length of the remaining PRN codes.
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* The purpose of this is to have the option to allow the FPGA to compensate for a possible deviation between the nominal value of the PRN
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* code length and the measured PRN code length in the PRN immediately following the start of the coherent integration only.
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* If this option is not used then write the same value to first_length_secondary_code and next_length_secondary_code.
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*/
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void update_prn_code_length(uint32_t first_prn_length, uint32_t next_prn_length);
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/*!
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* \brief Enable the use of secondary codes in the FPGA
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*/
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void enable_secondary_codes();
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/*!
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* \brief Disable the use of secondary codes in the FPGA
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*/
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void disable_secondary_codes();
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private:
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// FPGA register addresses
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// write addresses
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static const uint32_t code_phase_step_chips_num_reg_addr = 0;
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static const uint32_t initial_index_reg_base_addr = 1;
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static const uint32_t initial_interp_counter_reg_base_addr = 7;
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static const uint32_t nsamples_minus_1_reg_addr = 13;
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static const uint32_t code_length_minus_1_reg_addr = 14;
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static const uint32_t rem_carr_phase_rad_reg_addr = 15;
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static const uint32_t phase_step_rad_reg_addr = 16;
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static const uint32_t prog_mems_addr = 17;
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static const uint32_t drop_samples_reg_addr = 18;
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static const uint32_t initial_counter_value_reg_addr_lsw = 19;
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static const uint32_t initial_counter_value_reg_addr_msw = 20;
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static const uint32_t code_phase_step_chips_rate_reg_addr = 21;
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static const uint32_t phase_step_rate_reg_addr = 22;
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static const uint32_t stop_tracking_reg_addr = 23;
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static const uint32_t secondary_code_lengths_reg_addr = 25;
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static const uint32_t prog_secondary_code_0_data_reg_addr = 26;
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static const uint32_t prog_secondary_code_1_data_reg_addr = 27;
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static const uint32_t first_prn_length_minus_1_reg_addr = 28;
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static const uint32_t next_prn_length_minus_1_reg_addr = 29;
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static const uint32_t start_flag_addr = 30;
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// read-write addresses
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static const uint32_t test_reg_addr = 31;
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// read addresses
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static const uint32_t result_reg_real_base_addr = 1;
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static const uint32_t result_reg_imag_base_addr = 7;
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static const uint32_t sample_counter_reg_addr_lsw = 13;
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static const uint32_t sample_counter_reg_addr_msw = 14;
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// FPGA-related constants
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static const uint32_t secondary_code_word_size = 20; // the secondary codes are written in to the FPGA in words of secondary_code_word_size bits
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static const uint32_t secondary_code_wr_strobe = 0x800000; // write strobe position in the secondary code write register
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static const uint32_t secondary_code_addr_bits = 0x100000; // memory address position in the secondary code write register
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static const uint32_t drop_samples = 1; // bit 0 of drop_samples_reg_addr
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static const uint32_t enable_secondary_code = 2; // bit 1 of drop_samples_reg_addr
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static const uint32_t init_secondary_code_addresses = 4; // bit 2 of drop_samples_reg_addr
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static const uint32_t FPGA_PAGE_SIZE = 0x1000;
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static const uint32_t max_code_resampler_counter = 1 << 31; // 2^(number of bits of precision of the code resampler)
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static const uint32_t local_code_fpga_clear_address_counter = 0x10000000;
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static const uint32_t test_register_track_writeval = 0x55AA;
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// private functions
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uint32_t fpga_acquisition_test_register(uint32_t writeval);
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void fpga_configure_tracking_gps_local_code(int32_t PRN);
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void fpga_compute_code_shift_parameters();
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void fpga_configure_code_parameters_in_fpga();
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void fpga_compute_signal_parameters_in_fpga();
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void fpga_configure_signal_parameters_in_fpga();
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void fpga_launch_multicorrelator_fpga();
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void read_tracking_gps_results();
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void close_device(void);
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void write_secondary_code(uint32_t secondary_code_length, std::string *secondary_code_string, uint32_t reg_addr);
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volk_gnsssdr::vector<uint32_t> d_initial_index;
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volk_gnsssdr::vector<uint32_t> d_initial_interp_counter;
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uint64_t d_initial_sample_counter;
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gr_complex *d_corr_out;
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gr_complex *d_Prompt_Data;
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float *d_shifts_chips;
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float *d_prompt_data_shift;
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float d_rem_code_phase_chips;
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float d_code_phase_step_chips;
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float d_code_phase_rate_step_chips;
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float d_rem_carrier_phase_in_rad;
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float d_phase_step_rad;
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float d_carrier_phase_rate_step_rad;
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uint32_t d_code_length_samples;
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uint32_t d_n_correlators; // number of correlators
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// data related to the hardware module and the driver
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int32_t d_device_descriptor; // driver descriptor
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volatile uint32_t *d_map_base; // driver memory map
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// configuration data received from the interface
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uint32_t d_correlator_length_samples;
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uint32_t d_code_phase_step_chips_num;
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uint32_t d_code_phase_rate_step_chips_num;
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int32_t d_rem_carr_phase_rad_int;
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int32_t d_phase_step_rad_int;
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int32_t d_carrier_phase_rate_step_rad_int;
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// PRN codes
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int32_t *d_ca_codes;
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int32_t *d_data_codes;
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// secondary code configuration
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uint32_t d_secondary_code_0_length;
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uint32_t d_secondary_code_1_length;
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bool d_track_pilot;
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bool d_secondary_code_enabled;
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};
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/** \} */
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/** \} */
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#endif // GNSS_SDR_FPGA_MULTICORRELATOR_H
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