Marc Majoral
fe5f3f5328
now the FPGA Galileo E1 tracking pull-in tests work successfully
2018-11-12 17:44:42 +01:00
Marc Majoral
f150fe02c7
solved a bug which caused the tracking pull-in test not to work correctly with Galileo E1 when using the downsampling filter in the acquisition.
2018-11-09 20:50:32 +01:00
Marc Majoral
047807ba0c
solved a bug that caused the tracking pull-in test in the FPGA not to work when using the downsampling filter in the acquisition.
2018-11-08 19:19:39 +01:00
Marc Majoral
1c80eaa50c
corrected a bug in the fpga tracking pull-in test where a parameter was rewritten with an incorrect value
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modified the fpga tracking pull-in test to take into account the downsampling factor in the L1/E1 queue
2018-11-07 20:21:05 +01:00
Marc Majoral
0d9b08df70
updated the tracking pull-in test for the FPGA. To be tested.
2018-11-05 19:50:40 +01:00
Marc Majoral
8e6370e133
changed the downsampling factor of the L1 and E1 acquisition from /2 to /4
2018-10-17 15:45:08 +02:00
Marc Majoral
2826dd21d3
use of the :2 decimator in the GPS L1/Galileo E1 frequency band
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added methods to the L1 and E1 FPGA acquisition classes for the unit tests to be able to control the doppler sweep from the SW instead of the HW. In this way we can produce more detailed results.
2018-10-04 17:49:09 +02:00
Marc Majoral
f333c05305
saving temporary changes before merging with usptream next branch
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added functions that allow the tests to read the scaling factor used by the FFT and the IFFT during acquisition
2018-09-18 11:36:12 +02:00
Marc Majoral
1b0568e0e9
implemented hybrid observables tests using the FPGA. The hybrid observables test funtions are not tested yet.
2018-09-13 16:36:21 +02:00
Marc Majoral
5b9b63cc77
implemented tracking pull-in tests for the FPGA
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solved a bug in which the SW was using the doppler shift index reported by the HW acquisition accelerator plus one, instead of using the doppler shift index as such.
2018-09-12 16:02:23 +02:00
Marc Majoral
2b15343a6a
started tracking pull-in test implementation for the FPGA
2018-08-29 18:20:41 +02:00
Carles Fernandez
d41ed73a00
Add more extensive use of cstdint typenames
2018-08-11 13:12:33 +02:00
Marc Majoral
b1524a3afe
implemented 64-bit global sample counter
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started programming the FPGA tracking unit tests
2018-08-10 13:12:06 +02:00
