Sample values are ORed into the output buffer because they may need a few read/write operations depending on alignment.
So, if we don't set the value to 0 before doing this, all samples quickly become 0xFF after a few cycles of the output buffer.
Header file paths were being appended to the source files list.
This is not that important since, in general, you don't need to add the header files to the cmake target.
* Decouple the FPGA DMA signal source from the AD9361 FPGA signal source.
* Add the MAX2771_EVKIT FPGA signal source and the ENABLE_FPGA_MAX2771_EVKIT flag to enable it.
* Adjust cross-compilation flags to properly support FPGA signal sources
* fix signal source names for consistency
* Detect if the spidev driver is installed when the ENABLE_MAX2771 flag is set. Detect if the DMA proxy driver is installed when the ENABLE_DMA_PROXY flag is set. Check if ENABLE_FPGA is set when either ENABLE_MAX2771 or ENABLE_DMA_PROXY is set.
* fix FPGA signal source names for consistency
* Fix FPGA-related CMakefile flags
* make cpplint happy
* make cpplint happy
* make cmakelint happy
* make clang-format happy
* Replaced the AD9361 FPGA signal source with the ADRV9361_Z7035 FPGA and the FMCOMMS5 FPGA signal sources.
* Bump local version of GoogleTest to 1.15.2 and Protocol Buffers to 27.3
* Avoid code duplication in CMake modules
* Update clang-tidy job
* Clang Tidy fixes
* Improve efficiency of Concurrent_Map and Concurrent_Queue classes
* Fix segmentation fault if the SignalSource implementation is not available
* Moved decimation factor count variable to the class
* Avoid possible runtime error when PVT.enable_rx_clock_correction=true
* Fix formatting
* Fix clang-tidy job
* Capitalize FPGA in class implementation names
* Capitalize acronyms in FPGA-related class names
* Instantiate sources only once
* Update changelog
* Fix building in some environments and fix CI jobs
* Fix clang-tidy complain
---------
Co-authored-by: Marc Majoral <majoralmarc@gmail.com>
Co-authored-by: cesaaargm <cesare.martinez@proton.me>
Co-authored-by: Xavier Guerrero-Pau <xguerrero@cttc.es>
* revocation sucessfully tested.
* Diagram of step 1 is wrong in that KROOT with CID=0 also received after entering step 1.
* Duration of CREV=2.75h
* All tags verified succesffully.
