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mirror of https://github.com/gnss-sdr/gnss-sdr synced 2024-06-16 10:09:58 +00:00
Commit Graph

73 Commits

Author SHA1 Message Date
Marc Majoral
e4de9c54de do not stop the receiver when buffer overflow is detected. 2021-02-18 12:32:44 +01:00
Carles Fernandez
73a728b3f6
Merge branch 'feature/signal_source_interface' of https://github.com/jwmelto/gnss-sdr into jwmelto-feature/signal_source_interface 2021-02-18 09:03:03 +01:00
Carles Fernandez
f703990a09
Fix building when using C++11
Update changelog
2021-02-17 09:43:05 +01:00
Jim Melton
6e04a42c8a
clang-format
This was much worse than I thought. I had run clang-format at some point, but
apparently I subsequently made some non-compliant changes in pretty much every
file I touched.
2021-02-15 15:34:48 -07:00
Marc Majoral
b279c3bcbd replace exception by receiver stop command 2021-02-15 21:44:05 +01:00
Jim Melton
78362e7cba add signal_source_interface
also adds a base implementation that most signal sources should inherit from.
The gen_signal_source is inexplicably different (probably as a test fixture,
commonality was not valued).

Only the file_signal_source has been tested; all the sources are modified in the same
way, but we all know the only proof of correctness is testing.

The block factory was simplified a bit. Handling for legacy config files was pulled out
of the flowgraph; now when the "0" instance of a component (Foo0) is created, if there is
no config for it, then the legacy version (Foo) will be tried. This is different from
passing -1 for the item number (which is still supported). Theoretically, all existing
config files should still work.
2021-02-15 11:47:13 -07:00
Marc Majoral
c0e4b2aee5 dump the buffer monitor results to a file 2021-02-15 11:53:16 +01:00
Marc Majoral
03e8f97d2e real-time FPGA receiver buffer monitoring 2021-02-13 17:10:43 +01:00
Carles Fernandez
7308745f05
Apply more concise file header format
Re-license CMake scripts with BSD-3-Clause
2020-12-30 13:35:06 +01:00
Marc Majoral
312e8c6c9c cleaned comments 2020-11-27 12:21:10 +01:00
Marc Majoral
3047051835 The dynamic bit selector modules determine the uio device file that is assigned to them using the hardware accelerator device name in the FPGA. The Switch device name is not configurable. 2020-11-27 11:24:44 +01:00
Marc Majoral
a53109c718 The sample counter, the Acquisition and the Switch determine the uio device file that is assigned to them using the hardware accelerator device name in the FPGA 2020-11-26 17:07:15 +01:00
Marc Majoral
beddfb6f73 close the DMA descriptor properly. 2020-10-16 09:05:10 +02:00
Marc Majoral
933873c265 When using the FPGA in post-processing mode, start the DMA after instantiating the complete flowgraph, not before. 2020-09-10 10:08:25 +02:00
Carles Fernandez
a9472dea30
Remove redundant void (clang-tidy modernize-redundant-void-arg) 2020-08-27 12:48:20 +02:00
Carles Fernandez
499de7a9f1
Update file headers 2020-07-28 16:57:15 +02:00
Carles Fernandez
8633c03cf9
Remove unused lines
Some more const correctness
2020-07-28 01:33:26 +02:00
Carles Fernandez
7bececeef6
Improve const correctness
Remove all buprone conversions from signal_generator module
2020-07-17 09:11:42 +02:00
Marc Majoral
98f1287f0e dynamic bit selection based on the estimated power of the received signal. 2020-07-16 15:42:55 +02:00
Carles Fernandez
c04948fd02
Reduce number of warnings raised by bugprone-* clang-tidy checks 2020-07-10 00:37:55 +02:00
Carles Fernandez
09bcd1981c Replace std::endl by \n character. There is no need to always flush the stream. 2020-07-07 18:53:50 +02:00
Carles Fernandez
fcf1b97c30
Fix call to overloded property in GCC 2020-07-03 21:52:40 +02:00
Carles Fernandez
fb8e5e5c47
Fix a bug in signal sources that made the number of samples parameter ignored when too large (Fixes: #396) 2020-07-03 20:18:42 +02:00
Carles Fernandez
c412d0a3f5
Fix clang warning: equality comparison with extraneous parentheses 2020-07-02 10:53:51 +02:00
Marc Majoral
6ae4ddb3b8 init nread_elements to prevent compiler warning. 2020-07-02 10:33:36 +02:00
Carles Fernandez
7634934995
Fix ccplint job 2020-07-01 20:04:40 +02:00
Marc Majoral
975f22f53d fixed program termination when using the FPGA in post-processing mode: the DMA process was not properly checking enable_DMA. 2020-07-01 17:42:40 +02:00
Carles Fernandez
2b3d4b321d
Make the adapters take the configuration pointer as const 2020-06-29 09:07:41 +02:00
Carles Fernandez
df7c466de0
Sort data members in headers 2020-06-24 22:27:51 +02:00
Carles Fernandez
81af1a531b
Redesign of pointer management
Avoid indirection caused by passing shared_ptr by reference

The block factory does not have responsability on the lifetime of their inputs

Define std::make_unique when using C++11 and make use of it

Printers are turned into unique_ptr to express ownership

Printers do not participate on the lifelime of the data, so they take const raw pointers

Modernize tests code
2020-06-18 11:49:28 +02:00
Carles Fernandez
2df45a2d06
Remove tabs 2020-03-31 00:34:26 +02:00
Marc Majoral
0a14a1aa42 fixed DMA input file configuration options 2020-03-30 17:43:09 +02:00
Carles Fernandez
4d0d263280
Make the software package compliant with the REUSE Specification v3.0 (see https://reuse.software/spec/)
Update license headers to SPDX format (see https://spdx.org/)
Add license to all files
Add CI job in GitHub Actions to ensure compliance
2020-02-08 01:20:02 +01:00
Carles Fernandez
37f427844d Apply clang-format 2019-10-28 13:00:18 +01:00
Marc Majoral
f3485bb39b Throttle the DMA to give more time to other signal processing tasks. 2019-10-28 12:51:11 +01:00
Carles Fernandez
a9b0ff184d
Add energy-saving options for AD9361
New flag rf_shutdown, true by default, allows setting the RX and TX streams ON when set to false.
New parameters rx1_enable and rx2_enable, true by default, allow to disable the secondary RX channel when not used
2019-10-13 23:38:06 +02:00
Carles Fernandez
61c22ed53b
Set default freq_dds_tx_hz parameter to 10 kHz 2019-10-11 12:02:53 +02:00
Carles Fernandez
e4a39188f5
Implement FIR filter configuration 2019-10-09 20:50:06 +02:00
Carles Fernandez
0dbba0500d Add more parameter guards 2019-10-08 16:38:30 +02:00
Carles Fernandez
daa30c992c Remove unused parameters 2019-10-08 14:47:28 +02:00
Carles Fernandez
bdabbf7f85 Implement phase_dds_deg parameter, fix guard for tx_bandwidth 2019-10-08 12:57:37 +02:00
Carles Fernandez
48a62594eb
Add work on RF configuration parameters for AD9361 2019-10-07 22:45:09 +02:00
Carles Fernandez
b5c253fd8f
Implement more configuration options for AD9361 2019-10-06 19:07:24 +02:00
Marc Majoral
d20284fbc0 removed unused parameters 2019-10-02 15:25:46 +02:00
Marc Majoral
3a9e48c31c applied clang-format 2019-10-01 23:44:07 +02:00
Marc Majoral
e9470f566e fixed L1 and L2/L5 frequency band selection. 2019-10-01 23:13:28 +02:00
Marc Majoral
b932c5ef98 added the enable_DMA_ flag, which is used to stop the DMA when the user quits gnss-sdr, and the receiver is using the FPGA and the receiver is working in post-processing mode. 2019-10-01 22:26:30 +02:00
Marc Majoral
03cc2698bd removed the assert() function, which did not work properly. 2019-10-01 15:53:45 +02:00
Carles Fernandez
453c0cd249
Inject file(s) via DMA if switch_position=0 in Ad9361_Fpga_Signal_Source 2019-09-28 21:59:05 +02:00
Carles Fernandez
4dc30da649 Remove unused variables 2019-09-23 14:34:44 +02:00