diff --git a/src/algorithms/acquisition/adapters/galileo_e1_pcps_ambiguous_acquisition_fpga.cc b/src/algorithms/acquisition/adapters/galileo_e1_pcps_ambiguous_acquisition_fpga.cc index 307c754af..bdfc0bed7 100644 --- a/src/algorithms/acquisition/adapters/galileo_e1_pcps_ambiguous_acquisition_fpga.cc +++ b/src/algorithms/acquisition/adapters/galileo_e1_pcps_ambiguous_acquisition_fpga.cc @@ -44,7 +44,8 @@ #include // for complex #include // for memcpy - +// the following flags are FPGA-specific and they are using arrange the values of the fft of the local code in the way the FPGA +// expects. This arrangement is done in the initialisation to avoid consuming unnecessary clock cycles during tracking. #define QUANT_BITS_LOCAL_CODE 16 #define SELECT_LSBits 0x0000FFFF // Select the 10 LSbits out of a 20-bit word #define SELECT_MSBbits 0xFFFF0000 // Select the 10 MSbits out of a 20-bit word @@ -110,7 +111,6 @@ GalileoE1PcpsAmbiguousAcquisitionFpga::GalileoE1PcpsAmbiguousAcquisitionFpga( auto* fft_if = new gr::fft::fft_complex(nsamples_total, true); // Direct FFT auto* code = new std::complex[nsamples_total]; // buffer for the local code auto* fft_codes_padded = static_cast(volk_gnsssdr_malloc(nsamples_total * sizeof(gr_complex), volk_gnsssdr_get_alignment())); - //d_all_fft_codes_ = new lv_16sc_t[nsamples_total * GALILEO_E1_NUMBER_OF_CODES]; // memory containing all the possible fft codes for PRN 0 to 32 d_all_fft_codes_ = new uint32_t[(nsamples_total * GALILEO_E1_NUMBER_OF_CODES)]; // memory containing all the possible fft codes for PRN 0 to 32 float max; // temporary maxima search int32_t tmp, tmp2, local_code, fft_data; @@ -170,9 +170,6 @@ GalileoE1PcpsAmbiguousAcquisitionFpga::GalileoE1PcpsAmbiguousAcquisitionFpga( local_code = (tmp & SELECT_LSBits) | ((tmp2 * SHL_CODE_BITS) & SELECT_MSBbits); // put together the real part and the imaginary part fft_data = local_code & SELECT_ALL_CODE_BITS; d_all_fft_codes_[i + (nsamples_total * (PRN - 1))] = fft_data; - - // d_all_fft_codes_[i + nsamples_total * (PRN - 1)] = lv_16sc_t(static_cast(floor(fft_codes_padded[i].real() * (pow(2, QUANT_BITS_LOCAL_CODE - 1) - 1) / max)), - // static_cast(floor(fft_codes_padded[i].imag() * (pow(2, QUANT_BITS_LOCAL_CODE - 1) - 1) / max))); } } diff --git a/src/algorithms/acquisition/adapters/galileo_e1_pcps_ambiguous_acquisition_fpga.h b/src/algorithms/acquisition/adapters/galileo_e1_pcps_ambiguous_acquisition_fpga.h index 72f9bf831..f83af091f 100644 --- a/src/algorithms/acquisition/adapters/galileo_e1_pcps_ambiguous_acquisition_fpga.h +++ b/src/algorithms/acquisition/adapters/galileo_e1_pcps_ambiguous_acquisition_fpga.h @@ -165,7 +165,6 @@ private: unsigned int in_streams_; unsigned int out_streams_; - //lv_16sc_t* d_all_fft_codes_; // memory that contains all the code ffts uint32_t* d_all_fft_codes_; // memory that contains all the code ffts }; diff --git a/src/algorithms/acquisition/adapters/galileo_e5a_pcps_acquisition_fpga.cc b/src/algorithms/acquisition/adapters/galileo_e5a_pcps_acquisition_fpga.cc index 18f9aaa30..ed47a80ce 100644 --- a/src/algorithms/acquisition/adapters/galileo_e5a_pcps_acquisition_fpga.cc +++ b/src/algorithms/acquisition/adapters/galileo_e5a_pcps_acquisition_fpga.cc @@ -44,6 +44,8 @@ #include // for complex #include // for strcpy, memcpy +// the following flags are FPGA-specific and they are using arrange the values of the fft of the local code in the way the FPGA +// expects. This arrangement is done in the initialisation to avoid consuming unnecessary clock cycles during tracking. #define QUANT_BITS_LOCAL_CODE 16 #define SELECT_LSBits 0x0000FFFF // Select the 10 LSbits out of a 20-bit word #define SELECT_MSBbits 0xFFFF0000 // Select the 10 MSbits out of a 20-bit word @@ -110,7 +112,6 @@ GalileoE5aPcpsAcquisitionFpga::GalileoE5aPcpsAcquisitionFpga(ConfigurationInterf auto* fft_if = new gr::fft::fft_complex(nsamples_total, true); // Direct FFT auto* code = new std::complex[nsamples_total]; // buffer for the local code auto* fft_codes_padded = static_cast(volk_gnsssdr_malloc(nsamples_total * sizeof(gr_complex), volk_gnsssdr_get_alignment())); - //d_all_fft_codes_ = new lv_16sc_t[nsamples_total * GALILEO_E5A_NUMBER_OF_CODES]; // memory containing all the possible fft codes for PRN 0 to 32 d_all_fft_codes_ = new uint32_t[(nsamples_total * GALILEO_E5A_NUMBER_OF_CODES)]; // memory containing all the possible fft codes for PRN 0 to 32 float max; // temporary maxima search @@ -171,9 +172,6 @@ GalileoE5aPcpsAcquisitionFpga::GalileoE5aPcpsAcquisitionFpga(ConfigurationInterf local_code = (tmp & SELECT_LSBits) | ((tmp2 * SHL_CODE_BITS) & SELECT_MSBbits); // put together the real part and the imaginary part fft_data = local_code & SELECT_ALL_CODE_BITS; d_all_fft_codes_[i + (nsamples_total * (PRN - 1))] = fft_data; - - // d_all_fft_codes_[i + nsamples_total * (PRN - 1)] = lv_16sc_t(static_cast(floor(fft_codes_padded[i].real() * (pow(2, QUANT_BITS_LOCAL_CODE - 1) - 1) / max)), - // static_cast(floor(fft_codes_padded[i].imag() * (pow(2, QUANT_BITS_LOCAL_CODE - 1) - 1) / max))); } } diff --git a/src/algorithms/acquisition/adapters/galileo_e5a_pcps_acquisition_fpga.h b/src/algorithms/acquisition/adapters/galileo_e5a_pcps_acquisition_fpga.h index 8c0641aad..0510dcb97 100644 --- a/src/algorithms/acquisition/adapters/galileo_e5a_pcps_acquisition_fpga.h +++ b/src/algorithms/acquisition/adapters/galileo_e5a_pcps_acquisition_fpga.h @@ -182,7 +182,6 @@ private: Gnss_Synchro* gnss_synchro_; - //lv_16sc_t* d_all_fft_codes_; // memory that contains all the code ffts uint32_t* d_all_fft_codes_; // memory that contains all the code ffts }; diff --git a/src/algorithms/acquisition/adapters/gps_l1_ca_pcps_acquisition_fpga.cc b/src/algorithms/acquisition/adapters/gps_l1_ca_pcps_acquisition_fpga.cc index a0b6fc063..9cb95ba34 100644 --- a/src/algorithms/acquisition/adapters/gps_l1_ca_pcps_acquisition_fpga.cc +++ b/src/algorithms/acquisition/adapters/gps_l1_ca_pcps_acquisition_fpga.cc @@ -48,6 +48,9 @@ #include // for memcpy #define NUM_PRNs 32 + +// the following flags are FPGA-specific and they are using arrange the values of the fft of the local code in the way the FPGA +// expects. This arrangement is done in the initialisation to avoid consuming unnecessary clock cycles during tracking. #define QUANT_BITS_LOCAL_CODE 16 #define SELECT_LSBits 0x0000FFFF // Select the 10 LSbits out of a 20-bit word #define SELECT_MSBbits 0xFFFF0000 // Select the 10 MSbits out of a 20-bit word @@ -104,7 +107,6 @@ GpsL1CaPcpsAcquisitionFpga::GpsL1CaPcpsAcquisitionFpga( // allocate memory to compute all the PRNs and compute all the possible codes auto* code = new std::complex[nsamples_total]; // buffer for the local code auto* fft_codes_padded = static_cast(volk_gnsssdr_malloc(nsamples_total * sizeof(gr_complex), volk_gnsssdr_get_alignment())); - //d_all_fft_codes_ = new lv_16sc_t[nsamples_total * NUM_PRNs]; // memory containing all the possible fft codes for PRN 0 to 32 d_all_fft_codes_ = new uint32_t[(nsamples_total * NUM_PRNs)]; // memory containing all the possible fft codes for PRN 0 to 32 float max; int32_t tmp, tmp2, local_code, fft_data; @@ -149,9 +151,6 @@ GpsL1CaPcpsAcquisitionFpga::GpsL1CaPcpsAcquisitionFpga( local_code = (tmp & SELECT_LSBits) | ((tmp2 * SHL_CODE_BITS) & SELECT_MSBbits); // put together the real part and the imaginary part fft_data = local_code & SELECT_ALL_CODE_BITS; d_all_fft_codes_[i + (nsamples_total * (PRN - 1))] = fft_data; - - // d_all_fft_codes_[i + nsamples_total * (PRN - 1)] = lv_16sc_t(static_cast(floor(fft_codes_padded[i].real() * (pow(2, QUANT_BITS_LOCAL_CODE - 1) - 1) / max)), - // static_cast(floor(fft_codes_padded[i].imag() * (pow(2, QUANT_BITS_LOCAL_CODE - 1) - 1) / max))); } } diff --git a/src/algorithms/acquisition/adapters/gps_l1_ca_pcps_acquisition_fpga.h b/src/algorithms/acquisition/adapters/gps_l1_ca_pcps_acquisition_fpga.h index 2eb595ebe..150dd1c08 100644 --- a/src/algorithms/acquisition/adapters/gps_l1_ca_pcps_acquisition_fpga.h +++ b/src/algorithms/acquisition/adapters/gps_l1_ca_pcps_acquisition_fpga.h @@ -166,7 +166,6 @@ private: std::string role_; unsigned int in_streams_; unsigned int out_streams_; - //lv_16sc_t* d_all_fft_codes_; // memory that contains all the code ffts uint32_t* d_all_fft_codes_; // memory that contains all the code ffts }; diff --git a/src/algorithms/acquisition/adapters/gps_l5i_pcps_acquisition_fpga.cc b/src/algorithms/acquisition/adapters/gps_l5i_pcps_acquisition_fpga.cc index 1f972b17c..75632fd8b 100644 --- a/src/algorithms/acquisition/adapters/gps_l5i_pcps_acquisition_fpga.cc +++ b/src/algorithms/acquisition/adapters/gps_l5i_pcps_acquisition_fpga.cc @@ -48,6 +48,9 @@ #include // for memcpy #define NUM_PRNs 32 + +// the following flags are FPGA-specific and they are using arrange the values of the fft of the local code in the way the FPGA +// expects. This arrangement is done in the initialisation to avoid consuming unnecessary clock cycles during tracking. #define QUANT_BITS_LOCAL_CODE 16 #define SELECT_LSBits 0x0000FFFF // Select the 10 LSbits out of a 20-bit word #define SELECT_MSBbits 0xFFFF0000 // Select the 10 MSbits out of a 20-bit word @@ -108,7 +111,6 @@ GpsL5iPcpsAcquisitionFpga::GpsL5iPcpsAcquisitionFpga( auto* fft_if = new gr::fft::fft_complex(nsamples_total, true); // Direct FFT auto* code = new gr_complex[nsamples_total]; auto* fft_codes_padded = static_cast(volk_gnsssdr_malloc(nsamples_total * sizeof(gr_complex), volk_gnsssdr_get_alignment())); - //d_all_fft_codes_ = new lv_16sc_t[nsamples_total * NUM_PRNs]; // memory containing all the possible fft codes for PRN 0 to 32 d_all_fft_codes_ = new uint32_t[(nsamples_total * NUM_PRNs)]; // memory containing all the possible fft codes for PRN 0 to 32 float max; // temporary maxima search @@ -153,9 +155,6 @@ GpsL5iPcpsAcquisitionFpga::GpsL5iPcpsAcquisitionFpga( local_code = (tmp & SELECT_LSBits) | ((tmp2 * SHL_CODE_BITS) & SELECT_MSBbits); // put together the real part and the imaginary part fft_data = local_code & SELECT_ALL_CODE_BITS; d_all_fft_codes_[i + (nsamples_total * (PRN - 1))] = fft_data; - - // d_all_fft_codes_[i + nsamples_total * (PRN - 1)] = lv_16sc_t(static_cast(floor(fft_codes_padded[i].real() * (pow(2, QUANT_BITS_LOCAL_CODE - 1) - 1) / max)), - // static_cast(floor(fft_codes_padded[i].imag() * (pow(2, QUANT_BITS_LOCAL_CODE - 1) - 1) / max))); } } diff --git a/src/algorithms/acquisition/adapters/gps_l5i_pcps_acquisition_fpga.h b/src/algorithms/acquisition/adapters/gps_l5i_pcps_acquisition_fpga.h index f93573df1..3e3b91da7 100644 --- a/src/algorithms/acquisition/adapters/gps_l5i_pcps_acquisition_fpga.h +++ b/src/algorithms/acquisition/adapters/gps_l5i_pcps_acquisition_fpga.h @@ -167,7 +167,6 @@ private: unsigned int in_streams_; unsigned int out_streams_; - //lv_16sc_t* d_all_fft_codes_; // memory that contains all the code ffts uint32_t* d_all_fft_codes_; // memory that contains all the code ffts float calculate_threshold(float pfa); diff --git a/src/algorithms/acquisition/gnuradio_blocks/pcps_acquisition_fpga.cc b/src/algorithms/acquisition/gnuradio_blocks/pcps_acquisition_fpga.cc index 435eb75f1..db0872c1d 100644 --- a/src/algorithms/acquisition/gnuradio_blocks/pcps_acquisition_fpga.cc +++ b/src/algorithms/acquisition/gnuradio_blocks/pcps_acquisition_fpga.cc @@ -52,7 +52,7 @@ pcps_acquisition_fpga_sptr pcps_make_acquisition_fpga(pcpsconf_fpga_t conf_) pcps_acquisition_fpga::pcps_acquisition_fpga(pcpsconf_fpga_t conf_) { acq_parameters = std::move(conf_); - d_sample_counter = 0ULL; // SAMPLE COUNTER + d_sample_counter = 0ULL; // Sample Counter d_active = false; d_state = 0; d_fft_size = acq_parameters.samples_per_code; @@ -111,8 +111,6 @@ void pcps_acquisition_fpga::init() d_input_power = 0.0; d_num_doppler_bins = static_cast(std::ceil(static_cast(static_cast(d_doppler_max) - static_cast(-d_doppler_max)) / static_cast(d_doppler_step))) + 1; - - // acquisition_fpga->init(); } @@ -323,41 +321,6 @@ void pcps_acquisition_fpga::set_active(bool active) d_active = false; send_negative_acquisition(); } - - - // if (d_test_statistics > d_threshold) - // { - // d_doppler_center_step_two = static_cast(d_gnss_synchro->Acq_doppler_hz); - // //acquisition_fpga->open_device(); - // //boost::chrono::high_resolution_clock::time_point start = boost::chrono::high_resolution_clock::now(); - // - // acquisition_core(d_num_doppler_bins_step2, d_doppler_step2, d_doppler_center_step_two - static_cast(floor(d_num_doppler_bins_step2 / 2.0)) * d_doppler_step2); - // - // acquisition_fpga->close_device(); - // - // if (d_test_statistics > d_threshold) - // { - // d_active = false; - // send_positive_acquisition(); - // d_state = 0; // Positive acquisition - // } - // else - // { - // d_state = 0; - // d_active = false; - // send_negative_acquisition(); - // } - // //boost::chrono::nanoseconds ns = boost::chrono::high_resolution_clock::now() - start; - // //auto val = ns.count(); - // //std::cout << "Count ns: " << val << std::endl; - // } - // else - // { - // acquisition_fpga->close_device(); - // d_state = 0; - // d_active = false; - // send_negative_acquisition(); - // } } } @@ -369,9 +332,3 @@ void pcps_acquisition_fpga::reset_acquisition(void) acquisition_fpga->reset_acquisition(); acquisition_fpga->close_device(); } - - -//void pcps_acquisition_fpga::read_fpga_total_scale_factor(uint32_t* total_scale_factor, uint32_t* fw_scale_factor) -//{ -// acquisition_fpga->read_fpga_total_scale_factor(total_scale_factor, fw_scale_factor); -//} diff --git a/src/algorithms/acquisition/gnuradio_blocks/pcps_acquisition_fpga.h b/src/algorithms/acquisition/gnuradio_blocks/pcps_acquisition_fpga.h index d9605f229..80009b1be 100644 --- a/src/algorithms/acquisition/gnuradio_blocks/pcps_acquisition_fpga.h +++ b/src/algorithms/acquisition/gnuradio_blocks/pcps_acquisition_fpga.h @@ -231,11 +231,6 @@ public: * \brief This funciton triggers a HW reset of the FPGA PL. */ void reset_acquisition(void); - - /*! - * \brief This funciton is only used for the unit tests - */ - //void read_fpga_total_scale_factor(uint32_t* total_scale_factor, uint32_t* fw_scale_factor); }; #endif /* GNSS_SDR_PCPS_ACQUISITION_FPGA_H_*/ diff --git a/src/algorithms/acquisition/libs/fpga_acquisition.cc b/src/algorithms/acquisition/libs/fpga_acquisition.cc index 21822384a..29c8c0537 100644 --- a/src/algorithms/acquisition/libs/fpga_acquisition.cc +++ b/src/algorithms/acquisition/libs/fpga_acquisition.cc @@ -106,19 +106,12 @@ Fpga_Acquisition::Fpga_Acquisition(std::string device_name, Fpga_Acquisition::close_device(); d_PRN = 0; DLOG(INFO) << "Acquisition FPGA class created"; - //printf("d_excludelimit = %d\n", d_excludelimit); } Fpga_Acquisition::~Fpga_Acquisition() = default; -//bool Fpga_Acquisition::init() -//{ -// return true; -//} - - bool Fpga_Acquisition::set_local_code(uint32_t PRN) { // select the code with the chosen PRN @@ -169,8 +162,6 @@ void Fpga_Acquisition::fpga_acquisition_test_register() uint32_t writeval = TEST_REG_SANITY_CHECK; uint32_t readval; - //Fpga_Acquisition::open_device(); - // write value to test register d_map_base[15] = writeval; // read value from test register @@ -184,8 +175,6 @@ void Fpga_Acquisition::fpga_acquisition_test_register() { LOG(INFO) << "Acquisition test register sanity check success!"; } - - //Fpga_Acquisition::close_device(); } @@ -293,9 +282,7 @@ void Fpga_Acquisition::read_acquisition_results(uint32_t *max_index, readval = d_map_base[7]; // read doppler index -- this read releases the interrupt line *doppler_index = readval; - readval = d_map_base[15]; // read dummy - - //Fpga_Acquisition::close_device(); + readval = d_map_base[15]; // read dummy (to be removed) } @@ -324,9 +311,7 @@ void Fpga_Acquisition::close_device() void Fpga_Acquisition::reset_acquisition(void) { - //Fpga_Acquisition::open_device(); d_map_base[8] = RESET_ACQUISITION; // writing a 2 to d_map_base[8] resets the multicorrelator - //Fpga_Acquisition::close_device(); } @@ -336,8 +321,7 @@ void Fpga_Acquisition::read_fpga_total_scale_factor(uint32_t *total_scale_factor uint32_t readval = 0; readval = d_map_base[8]; *total_scale_factor = readval; - - //readval = d_map_base[8]; + // only the total scale factor is used for the tests (fw scale factor to be removed) *fw_scale_factor = 0; } diff --git a/src/algorithms/acquisition/libs/fpga_acquisition.h b/src/algorithms/acquisition/libs/fpga_acquisition.h index d0fd23582..2ee00e315 100644 --- a/src/algorithms/acquisition/libs/fpga_acquisition.h +++ b/src/algorithms/acquisition/libs/fpga_acquisition.h @@ -53,12 +53,10 @@ public: int64_t fs_in, uint32_t sampled_ms, uint32_t select_queue, - //lv_16sc_t *all_fft_codes, uint32_t *all_fft_codes, uint32_t excludelimit); ~Fpga_Acquisition(); - //bool init(); bool set_local_code(uint32_t PRN); bool free(); void set_doppler_sweep(uint32_t num_sweeps, uint32_t doppler_step, int32_t doppler_min); @@ -111,9 +109,8 @@ private: // data related to the hardware module and the driver int32_t d_fd; // driver descriptor volatile uint32_t *d_map_base; // driver memory map - //lv_16sc_t *d_all_fft_codes; // memory that contains all the code ffts - uint32_t *d_all_fft_codes; // memory that contains all the code ffts - uint32_t d_vector_length; // number of samples incluing padding and number of ms + uint32_t *d_all_fft_codes; // memory that contains all the code ffts + uint32_t d_vector_length; // number of samples incluing padding and number of ms uint32_t d_excludelimit; uint32_t d_nsamples_total; // number of samples including padding uint32_t d_nsamples; // number of samples not including padding diff --git a/src/algorithms/tracking/adapters/galileo_e1_dll_pll_veml_tracking_fpga.cc b/src/algorithms/tracking/adapters/galileo_e1_dll_pll_veml_tracking_fpga.cc index 40df01ce5..7dc64187e 100644 --- a/src/algorithms/tracking/adapters/galileo_e1_dll_pll_veml_tracking_fpga.cc +++ b/src/algorithms/tracking/adapters/galileo_e1_dll_pll_veml_tracking_fpga.cc @@ -48,7 +48,8 @@ #include // for memcpy #include // for operator<<, -// the following flag is FPGA-specific and they are using during the local code initialisation in the SW to save CPU cycles during tracking +// the following flags are FPGA-specific and they are using arrange the values of the local code in the way the FPGA +// expects. This arrangement is done in the initialisation to avoid consuming unnecessary clock cycles during tracking. #define LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY 0x0C000000 // flag that enables WE (Write Enable) of the local code FPGA #define LOCAL_CODE_FPGA_CORRELATOR_SELECT_COUNT 0x20000000 // flag that selects the writing of the pilot code in the FPGA (as opposed to the data code) diff --git a/src/algorithms/tracking/adapters/galileo_e5a_dll_pll_tracking_fpga.cc b/src/algorithms/tracking/adapters/galileo_e5a_dll_pll_tracking_fpga.cc index fa8446996..5f3241696 100644 --- a/src/algorithms/tracking/adapters/galileo_e5a_dll_pll_tracking_fpga.cc +++ b/src/algorithms/tracking/adapters/galileo_e5a_dll_pll_tracking_fpga.cc @@ -45,7 +45,8 @@ #include // for memcpy #include -// the following flag is FPGA-specific and they are using during the local code initialisation in the SW to save CPU cycles during tracking +// the following flags are FPGA-specific and they are using arrange the values of the local code in the way the FPGA +// expects. This arrangement is done in the initialisation to avoid consuming unnecessary clock cycles during tracking. #define LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY 0x0C000000 // flag that enables WE (Write Enable) of the local code FPGA #define LOCAL_CODE_FPGA_CORRELATOR_SELECT_COUNT 0x20000000 // flag that selects the writing of the pilot code in the FPGA (as opposed to the data code) @@ -238,8 +239,6 @@ GalileoE5aDllPllTrackingFpga::GalileoE5aDllPllTrackingFpga( } tmp_value = tmp_value | LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY | LOCAL_CODE_FPGA_CORRELATOR_SELECT_COUNT; d_data_codes[static_cast(code_length_chips) * (PRN - 1) + s] = tmp_value; - //d_ca_codes[static_cast(code_length_chips) * (PRN - 1) + s] = static_cast(aux_code[s].imag()); - //d_data_codes[static_cast(code_length_chips) * (PRN - 1) + s] = static_cast(aux_code[s].real()); } } else @@ -254,7 +253,6 @@ GalileoE5aDllPllTrackingFpga::GalileoE5aDllPllTrackingFpga( } tmp_value = tmp_value | LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY; d_ca_codes[static_cast(code_length_chips) * (PRN - 1) + s] = tmp_value; - //d_ca_codes[static_cast(code_length_chips) * (PRN - 1) + s] = static_cast(aux_code[s].real()); } } } diff --git a/src/algorithms/tracking/adapters/galileo_e5a_dll_pll_tracking_fpga.h b/src/algorithms/tracking/adapters/galileo_e5a_dll_pll_tracking_fpga.h index eeaa1da6c..1950e4630 100644 --- a/src/algorithms/tracking/adapters/galileo_e5a_dll_pll_tracking_fpga.h +++ b/src/algorithms/tracking/adapters/galileo_e5a_dll_pll_tracking_fpga.h @@ -99,7 +99,6 @@ private: std::string role_; uint32_t in_streams_; uint32_t out_streams_; - int32_t* d_ca_codes; int32_t* d_data_codes; bool d_track_pilot; diff --git a/src/algorithms/tracking/adapters/gps_l1_ca_dll_pll_tracking_fpga.cc b/src/algorithms/tracking/adapters/gps_l1_ca_dll_pll_tracking_fpga.cc index ad78b9ae5..e359dba88 100644 --- a/src/algorithms/tracking/adapters/gps_l1_ca_dll_pll_tracking_fpga.cc +++ b/src/algorithms/tracking/adapters/gps_l1_ca_dll_pll_tracking_fpga.cc @@ -50,7 +50,8 @@ #define NUM_PRNs 32 // total number of PRNs -// the following flag is FPGA-specific and they are using during the local code initialisation in the SW to save CPU cycles during tracking +// the following flag is FPGA-specific and they are using arrange the values of the local code in the way the FPGA +// expects. This arrangement is done in the initialisation to avoid consuming unnecessary clock cycles during tracking. #define LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY 0x0C000000 // flag that enables WE (Write Enable) of the local code FPGA GpsL1CaDllPllTrackingFpga::GpsL1CaDllPllTrackingFpga( diff --git a/src/algorithms/tracking/adapters/gps_l5_dll_pll_tracking_fpga.cc b/src/algorithms/tracking/adapters/gps_l5_dll_pll_tracking_fpga.cc index aa31ae122..1dca0c03a 100644 --- a/src/algorithms/tracking/adapters/gps_l5_dll_pll_tracking_fpga.cc +++ b/src/algorithms/tracking/adapters/gps_l5_dll_pll_tracking_fpga.cc @@ -52,7 +52,8 @@ #define NUM_PRNs 32 // number of PRNS -// the following flag is FPGA-specific and they are using during the local code initialisation in the SW to save CPU cycles during tracking +// the following flags are FPGA-specific and they are using arrange the values of the local code in the way the FPGA +// expects. This arrangement is done in the initialisation to avoid consuming unnecessary clock cycles during tracking. #define LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY 0x0C000000 // flag that enables WE (Write Enable) of the local code FPGA #define LOCAL_CODE_FPGA_CORRELATOR_SELECT_COUNT 0x20000000 // flag that selects the writing of the pilot code in the FPGA (as opposed to the data code) @@ -256,9 +257,6 @@ GpsL5DllPllTrackingFpga::GpsL5DllPllTrackingFpga( } tmp_value = tmp_value | LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY | LOCAL_CODE_FPGA_CORRELATOR_SELECT_COUNT; d_data_codes[static_cast(code_length_chips) * (PRN - 1) + s] = tmp_value; - - //d_ca_codes[static_cast(code_length_chips) * (PRN - 1) + s] = static_cast(tracking_code[s]); - //d_data_codes[static_cast(code_length_chips) * (PRN - 1) + s] = static_cast(data_code[s]); } } else @@ -275,7 +273,6 @@ GpsL5DllPllTrackingFpga::GpsL5DllPllTrackingFpga( } tmp_value = tmp_value | LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY; d_ca_codes[static_cast(code_length_chips) * (PRN - 1) + s] = tmp_value; - //d_ca_codes[static_cast(code_length_chips) * (PRN - 1) + s] = static_cast(tracking_code[s]); } } } diff --git a/src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.cc b/src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.cc index 43a15db33..360241991 100644 --- a/src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.cc +++ b/src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.cc @@ -274,10 +274,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga & d_code_loop_filter = Tracking_loop_filter(d_code_period, trk_parameters.dll_bw_hz, trk_parameters.dll_filter_order, false); printf("trk_parameters.fll_bw_hz = %f trk_parameters.pll_bw_hz = %f trk_parameters.pll_filter_order = %d\n", trk_parameters.fll_bw_hz, trk_parameters.pll_bw_hz, trk_parameters.pll_filter_order); d_carrier_loop_filter.set_params(trk_parameters.fll_bw_hz, trk_parameters.pll_bw_hz, trk_parameters.pll_filter_order); - //d_code_loop_filter_old.set_DLL_BW(trk_parameters.dll_bw_hz); - //d_carrier_loop_filter_old.set_PLL_BW(trk_parameters.pll_bw_hz); - //d_code_loop_filter_old = Tracking_2nd_DLL_filter(static_cast(d_code_period)); - //d_carrier_loop_filter_old = Tracking_2nd_PLL_filter(static_cast(d_code_period)); if (d_veml) { @@ -431,7 +427,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga & uint32_t multicorr_type = trk_parameters.multicorr_type; multicorrelator_fpga = std::make_shared(d_n_correlator_taps, device_name, device_base, ca_codes, data_codes, d_code_length_chips, trk_parameters.track_pilot, multicorr_type, d_code_samples_per_chip); multicorrelator_fpga->set_output_vectors(d_correlator_outs, d_Prompt_Data); - //multicorrelator_fpga->fpga_compute_signal_parameters_in_fpga(); d_sample_counter_next = 0ULL; } @@ -469,6 +464,11 @@ void dll_pll_veml_tracking_fpga::msg_handler_telemetry_to_trk(const pmt::pmt_t & void dll_pll_veml_tracking_fpga::start_tracking() { + // all the calculations that do not require the data from the acquisition module are moved to the + // set_gnss_synchro command, which is received with a valid PRN before the acquisition module starts the + // acquisition process. This is done to minimize the time between the end of the acquisition process and + // the beginning of the tracking process. + // correct the code phase according to the delay between acq and trk d_acq_code_phase_samples = d_acquisition_gnss_synchro->Acq_delay_samples; d_acq_carrier_doppler_hz = d_acquisition_gnss_synchro->Acq_doppler_hz; @@ -479,20 +479,10 @@ void dll_pll_veml_tracking_fpga::start_tracking() // filter initialization - //printf("d_carrier_loop_filter init d_acq_carrier_doppler_hz = %lf\n", d_acq_carrier_doppler_hz); d_carrier_loop_filter.initialize(static_cast(d_acq_carrier_doppler_hz)); // initialize the carrier filter - // // DEBUG OUTPUT - // std::cout << "Tracking of " << systemName << " " << signal_pretty_name << " signal started on channel " << d_channel << " for satellite " << Gnss_Satellite(systemName, d_acquisition_gnss_synchro->PRN) << std::endl; - // DLOG(INFO) << "Starting tracking of satellite " << Gnss_Satellite(systemName, d_acquisition_gnss_synchro->PRN) << " on channel " << d_channel; - // enable tracking pull-in d_state = 1; - - //d_pull_in_transitory = true; - - // d_Prompt_buffer_deque.clear(); - // d_last_prompt = gr_complex(0.0, 0.0); } @@ -672,7 +662,6 @@ void dll_pll_veml_tracking_fpga::run_dll_pll() // FLL discriminator d_carr_freq_error_hz = fll_four_quadrant_atan(d_P_accu_old, d_P_accu, 0, d_current_correlation_time_s) / GPS_TWO_PI; d_P_accu_old = d_P_accu; - //std::cout << "d_carr_freq_error_hz: " << d_carr_freq_error_hz << std::endl; // Carrier discriminator filter if ((d_pull_in_transitory == true and trk_parameters.enable_fll_pull_in == true)) { @@ -691,10 +680,7 @@ void dll_pll_veml_tracking_fpga::run_dll_pll() d_carr_error_filt_hz = d_carrier_loop_filter.get_carrier_error(0, d_carr_phase_error_hz, d_current_correlation_time_s); } - //// Carrier discriminator filter - //d_carr_error_filt_hz = d_carrier_loop_filter_old.get_carrier_nco(d_carr_error_hz); // New carrier Doppler frequency estimation - //d_carrier_doppler_hz = d_acq_carrier_doppler_hz + d_carr_error_filt_hz; d_carrier_doppler_hz = d_carr_error_filt_hz; // std::cout << "d_carrier_doppler_hz: " << d_carrier_doppler_hz << std::endl; @@ -711,7 +697,6 @@ void dll_pll_veml_tracking_fpga::run_dll_pll() } // Code discriminator filter d_code_error_filt_chips = d_code_loop_filter.apply(d_code_error_chips); // [chips/second] - //d_code_error_filt_chips = d_code_loop_filter_old.get_code_nco(d_code_error_chips); // [chips/second] // New code Doppler frequency estimation d_code_freq_chips = (1.0 + (d_carrier_doppler_hz / d_signal_carrier_freq)) * d_code_chip_rate - d_code_error_filt_chips; @@ -870,7 +855,6 @@ void dll_pll_veml_tracking_fpga::save_correlation_results() { d_cloop = true; } - //printf("d_cloop = %d\n", d_cloop); } @@ -1285,25 +1269,18 @@ void dll_pll_veml_tracking_fpga::set_gnss_synchro(Gnss_Synchro *p_gnss_synchro) { //std::cout << "Acquisition is about to start " << std::endl; - // When using the FPGA the SW only reads the sample counter during active tracking. - // For the temporary pull-in conditions to work the sample_counter in the SW must be - // cleared before reading the actual sample counter from the FPGA the first time + // When using the FPGA the SW only reads the sample counter during active tracking in order to spare CPU clock cycles. d_sample_counter = 0; d_sample_counter_next = 0; d_carrier_phase_rate_step_rad = 0.0; d_code_ph_history.clear(); + // DLL/PLL filter initialization - // the carrier loop filter uses a variable not available until the start_tracking function is called - //d_carrier_loop_filter.initialize(static_cast(d_acq_carrier_doppler_hz)); // initialize the carrier filter d_code_loop_filter.initialize(); // initialize the code filter - d_carr_ph_history.clear(); - // DLL/PLL filter initialization - //d_carrier_loop_filter_old.initialize(); // initialize the carrier filter - //d_code_loop_filter_old.initialize(); // initialize the code filter if (systemName == "GPS" and signal_type == "L5") { @@ -1328,8 +1305,6 @@ void dll_pll_veml_tracking_fpga::set_gnss_synchro(Gnss_Synchro *p_gnss_synchro) } } - // call this but in FPGA ??? - //multicorrelator_cpu.set_local_code_and_taps(d_code_samples_per_chip * d_code_length_chips, d_tracking_code, d_local_code_shift_chips); std::fill_n(d_correlator_outs, d_n_correlator_taps, gr_complex(0.0, 0.0)); d_carrier_lock_fail_counter = 0; @@ -1356,11 +1331,6 @@ void dll_pll_veml_tracking_fpga::set_gnss_synchro(Gnss_Synchro *p_gnss_synchro) d_current_correlation_time_s = d_code_period; - //d_code_loop_filter_old.set_DLL_BW(trk_parameters.dll_bw_hz); - //d_carrier_loop_filter_old.set_PLL_BW(trk_parameters.pll_bw_hz); - //d_carrier_loop_filter_old.set_pdi(static_cast(d_code_period)); - //d_code_loop_filter_old.set_pdi(static_cast(d_code_period)); - d_code_loop_filter.set_noise_bandwidth(trk_parameters.dll_bw_hz); d_code_loop_filter.set_update_interval(d_code_period); @@ -1784,9 +1754,7 @@ void dll_pll_veml_tracking_fpga::run_state_2(Gnss_Synchro ¤t_synchro_data) // UPDATE INTEGRATION TIME d_extend_correlation_symbols_count = 0; d_current_correlation_time_s = static_cast(trk_parameters.extend_correlation_symbols) * static_cast(d_code_period); - //float new_correlation_time = static_cast(trk_parameters.extend_correlation_symbols) * static_cast(d_code_period); - //d_carrier_loop_filter_old.set_pdi(new_correlation_time); - //d_code_loop_filter_old.set_pdi(new_correlation_time); + d_state = 3; // next state is the extended correlator integrator LOG(INFO) << "Enabled " << trk_parameters.extend_correlation_symbols * static_cast(d_code_period * 1000.0) << " ms extended correlator in channel " << d_channel @@ -1795,8 +1763,6 @@ void dll_pll_veml_tracking_fpga::run_state_2(Gnss_Synchro ¤t_synchro_data) << d_channel << " for satellite " << Gnss_Satellite(systemName, d_acquisition_gnss_synchro->PRN) << std::endl; // Set narrow taps delay values [chips] - //d_code_loop_filter_old.set_DLL_BW(trk_parameters.dll_bw_narrow_hz); - //d_carrier_loop_filter_old.set_PLL_BW(trk_parameters.pll_bw_narrow_hz); d_code_loop_filter.set_update_interval(d_current_correlation_time_s); d_code_loop_filter.set_noise_bandwidth(trk_parameters.dll_bw_narrow_hz); d_carrier_loop_filter.set_params(trk_parameters.fll_bw_hz, trk_parameters.pll_bw_narrow_hz, trk_parameters.pll_filter_order); diff --git a/src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.h b/src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.h index 3abb32b47..349db24f0 100644 --- a/src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.h +++ b/src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.h @@ -33,8 +33,6 @@ #define GNSS_SDR_DLL_PLL_VEML_TRACKING_FPGA_H #include "dll_pll_conf_fpga.h" -//#include "tracking_2nd_DLL_filter.h" -//#include "tracking_2nd_PLL_filter.h" #include "tracking_FLL_PLL_filter.h" // for PLL/FLL filter #include "tracking_loop_filter.h" // for DLL filter #include @@ -131,11 +129,6 @@ private: float *d_local_code_shift_chips; float *d_prompt_data_shift; std::shared_ptr multicorrelator_fpga; - /* TODO: currently the multicorrelator does not support adding extra correlator - with different local code, thus we need extra multicorrelator instance. - Implement this functionality inside multicorrelator class - as an enhancement to increase the performance - */ gr_complex *d_correlator_outs; gr_complex *d_Very_Early; gr_complex *d_Early; @@ -167,13 +160,10 @@ private: double d_rem_code_phase_samples; float d_rem_carr_phase_rad; + // PLL and DLL filter library Tracking_loop_filter d_code_loop_filter; Tracking_FLL_PLL_filter d_carrier_loop_filter; - // PLL and DLL filter library - //Tracking_2nd_DLL_filter d_code_loop_filter_old; - //Tracking_2nd_PLL_filter d_carrier_loop_filter_old; - // acquisition double d_acq_code_phase_samples; double d_acq_carrier_doppler_hz; diff --git a/src/algorithms/tracking/libs/fpga_multicorrelator.cc b/src/algorithms/tracking/libs/fpga_multicorrelator.cc index 4631f6214..f674da1d2 100644 --- a/src/algorithms/tracking/libs/fpga_multicorrelator.cc +++ b/src/algorithms/tracking/libs/fpga_multicorrelator.cc @@ -300,41 +300,17 @@ uint32_t Fpga_Multicorrelator_8sc::fpga_acquisition_test_register( void Fpga_Multicorrelator_8sc::fpga_configure_tracking_gps_local_code(int32_t PRN) { uint32_t k; - //uint32_t code_chip; - //uint32_t select_pilot_corelator = LOCAL_CODE_FPGA_CORRELATOR_SELECT_COUNT; d_map_base[PROG_MEMS_ADDR] = LOCAL_CODE_FPGA_CLEAR_ADDRESS_COUNTER; for (k = 0; k < d_code_length_samples; k++) { - // if (d_ca_codes[(d_code_length_samples * (PRN - 1)) + k] == 1) - // { - // code_chip = 1; - // } - // else - // { - // code_chip = 0; - // } - //code_chip = d_ca_codes[(d_code_length_samples * (PRN - 1)) + k]; - // copy the local code to the FPGA memory one by one - //d_map_base[PROG_MEMS_ADDR] = LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY | code_chip; // | select_fpga_correlator; d_map_base[PROG_MEMS_ADDR] = d_ca_codes[(d_code_length_samples * (PRN - 1)) + k]; - ; // | select_fpga_correlator; } if (d_track_pilot) { d_map_base[PROG_MEMS_ADDR] = LOCAL_CODE_FPGA_CLEAR_ADDRESS_COUNTER; for (k = 0; k < d_code_length_samples; k++) { - // if (d_data_codes[(d_code_length_samples * (PRN - 1)) + k] == 1) - // { - // code_chip = 1; - // } - // else - // { - // code_chip = 0; - // } - //code_chip = d_data_codes[(d_code_length_samples * (PRN - 1)) + k]; - //d_map_base[PROG_MEMS_ADDR] = LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY | code_chip | select_pilot_corelator; d_map_base[PROG_MEMS_ADDR] = d_data_codes[(d_code_length_samples * (PRN - 1)) + k]; } } @@ -348,9 +324,7 @@ void Fpga_Multicorrelator_8sc::fpga_compute_code_shift_parameters(void) float frac_part; // decimal part int32_t dec_part; // fractional part - int32_t i; - - for (i = 0; i < d_n_correlators; i++) + for (uint32_t i = 0; i < d_n_correlators; i++) { dec_part = floor(d_shifts_chips[i] - d_rem_code_phase_chips); @@ -391,8 +365,7 @@ void Fpga_Multicorrelator_8sc::fpga_compute_code_shift_parameters(void) void Fpga_Multicorrelator_8sc::fpga_configure_code_parameters_in_fpga(void) { - int32_t i; - for (i = 0; i < d_n_correlators; i++) + for (uint32_t i = 0; i < d_n_correlators; i++) { d_map_base[INITIAL_INDEX_REG_BASE_ADDR + i] = d_initial_index[i]; d_map_base[INITIAL_INTERP_COUNTER_REG_BASE_ADDR + i] = d_initial_interp_counter[i]; @@ -402,8 +375,6 @@ void Fpga_Multicorrelator_8sc::fpga_configure_code_parameters_in_fpga(void) d_map_base[INITIAL_INDEX_REG_BASE_ADDR + d_n_correlators] = d_initial_index[d_n_correlators]; d_map_base[INITIAL_INTERP_COUNTER_REG_BASE_ADDR + d_n_correlators] = d_initial_interp_counter[d_n_correlators]; } - - //d_map_base[CODE_LENGTH_MINUS_1_REG_ADDR] = (d_code_length_samples)-1; // number of samples - 1 } @@ -461,9 +432,8 @@ void Fpga_Multicorrelator_8sc::read_tracking_gps_results(void) { int32_t readval_real; int32_t readval_imag; - int32_t k; - for (k = 0; k < d_n_correlators; k++) + for (uint32_t k = 0; k < d_n_correlators; k++) { readval_real = d_map_base[RESULT_REG_REAL_BASE_ADDR + k]; readval_imag = d_map_base[RESULT_REG_IMAG_BASE_ADDR + k]; diff --git a/src/algorithms/tracking/libs/fpga_multicorrelator.h b/src/algorithms/tracking/libs/fpga_multicorrelator.h index a931bbd61..c97506839 100644 --- a/src/algorithms/tracking/libs/fpga_multicorrelator.h +++ b/src/algorithms/tracking/libs/fpga_multicorrelator.h @@ -75,7 +75,6 @@ public: uint32_t device_base, int32_t *ca_codes, int32_t *data_codes, uint32_t code_length_chips, bool track_pilot, uint32_t multicorr_type, uint32_t code_samples_per_chip); ~Fpga_Multicorrelator_8sc(); void set_output_vectors(gr_complex *corr_out, gr_complex *Prompt_Data); - //void fpga_compute_signal_parameters_in_fpga(void); void set_local_code_and_taps( float *shifts_chips, float *prompt_data_shift, int32_t PRN); void update_local_code();