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make cpplint happy

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This commit is contained in:
Marc Majoral
2024-07-24 15:28:07 +02:00
parent 468e840eb1
commit ef3afccfbc
5 changed files with 15 additions and 23 deletions
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13
src/algorithms/signal_source/adapters/dma_signal_source_fpga.cc
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@@ -21,12 +21,13 @@
#include "configuration_interface.h"
#include "gnss_sdr_flags.h"
#include "gnss_sdr_string_literals.h"
#include <chrono> // for std::chrono
#include <fcntl.h> // for open, O_WRONLY
#include <fstream> // for std::ifstream
#include <iomanip> // for std::setprecision
#include <iostream> // for std::cout
#include <vector> // fr std::vector
#include <algorithm> // for std::min
#include <chrono> // for std::chrono
#include <fcntl.h> // for open, O_WRONLY
#include <fstream> // for std::ifstream
#include <iomanip> // for std::setprecision
#include <iostream> // for std::cout
#include <vector> // fr std::vector
#if USE_GLOG_AND_GFLAGS
#include <glog/logging.h>

12
src/algorithms/signal_source/adapters/max2771_evkit_signal_source_fpga.cc
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@@ -28,7 +28,7 @@
#include <cmath> // for std::floor
#include <exception> // for std::exception
#include <iostream> // for std::cout
#include <vector> // for std::vector
#if USE_GLOG_AND_GFLAGS
#include <glog/logging.h>
#else
@@ -212,7 +212,7 @@ std::vector<uint32_t> MAX2771EVKITSignalSourceFPGA::setup_regs(void)
DIEID;
register_values[2] = // configuration 3 register
(0x0 << 28) + //reserved
(0x0 << 28) + // reserved
(gain_in_ << 22) +
(0x1 << 21) + // reserved
(HILOADEN << 20) +
@@ -266,7 +266,7 @@ std::vector<uint32_t> MAX2771EVKITSignalSourceFPGA::setup_regs(void)
(IXTAL << 19) +
(0x10 << 14) + // reserved
(0x0 << 13) + // reserved
(0x0 << 10) + //reserved
(0x0 << 10) + // reserved
(ICP << 9) +
(0x0 << 8) + // reserved
(0x0 << 7) + // reserved
@@ -291,9 +291,9 @@ std::vector<uint32_t> MAX2771EVKITSignalSourceFPGA::setup_regs(void)
default:
freq_sel = 0x604;
}
//uint32_t freq_sel = (freq_ == GPS_L1_FREQ_HZ) ? 0x604 :
register_values[4] = // PLL integer division register
(0x0 << 28) + //reserved
(0x0 << 28) + // reserved
(freq_sel << 13) +
(RDIV << 3) +
0x0; // reserved
@@ -318,7 +318,7 @@ std::vector<uint32_t> MAX2771EVKITSignalSourceFPGA::setup_regs(void)
(REFCLK_M_CNT << 4) +
(FCLKIN << 3) +
(ADCCLK << 2) +
(0x1 << 1) + //reserved
(0x1 << 1) + // reserved
MODE;
register_values[8] = TEST_MODE_1_REG_VAL; // test mode 1 register

2
src/algorithms/signal_source/adapters/max2771_evkit_signal_source_fpga.h
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@@ -143,7 +143,7 @@ private:
uint32_t in_stream_;
uint32_t out_stream_;
uint32_t bandwidth_; // 2500000, 4200000, 8700000, 16400000, 23400000, 36000000
uint32_t filter_order_; //3, 5
uint32_t filter_order_; // 3, 5
uint32_t gain_in_; // 0 to 0x3F
size_t item_size_; // 1

9
src/algorithms/signal_source/libs/fpga_buffer_monitor.cc
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@@ -41,15 +41,6 @@
#endif
//Fpga_buffer_monitor::Fpga_buffer_monitor(const std::string &device_name,
// uint32_t num_freq_bands,
// bool dump,
// std::string dump_filename)
// : d_dump_filename(std::move(dump_filename)),
// d_num_freq_bands(num_freq_bands),
// d_max_buff_occ_freq_band_0(0),
// d_max_buff_occ_freq_band_1(0),
// d_dump(dump)
Fpga_buffer_monitor::Fpga_buffer_monitor(
uint32_t num_freq_bands,
bool dump,

2
src/algorithms/signal_source/libs/fpga_switch.h
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@@ -42,7 +42,7 @@ public:
/*!
* \brief Constructor
*/
explicit Fpga_Switch(void);
Fpga_Switch(void);
/*!
* \brief Destructor
*/