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https://github.com/gnss-sdr/gnss-sdr
synced 2024-07-04 02:43:15 +00:00
neon hook
This commit is contained in:
Carles Fernandez
parent
e400885800
commit
e66ac2f476
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@ -177,10 +177,10 @@ static inline void volk_gnsssdr_16ic_x2_rotator_dot_prod_16ic_xn_a_sse3(lv_16sc_
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{
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a = _mm_load_si128((__m128i*)&(_in_a[n_vec][number*4])); //load (2 byte imag, 2 byte real) x 4 into 128 bits reg
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c = _mm_mullo_epi16 (a, b); // a3.i*b3.i, a3.r*b3.r, ....
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c = _mm_mullo_epi16(a, b); // a3.i*b3.i, a3.r*b3.r, ....
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c_sr = _mm_srli_si128 (c, 2); // Shift a right by imm8 bytes while shifting in zeros, and store the results in dst.
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real = _mm_subs_epi16 (c, c_sr);
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c_sr = _mm_srli_si128(c, 2); // Shift a right by imm8 bytes while shifting in zeros, and store the results in dst.
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real = _mm_subs_epi16(c, c_sr);
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b_sl = _mm_slli_si128(b, 2); // b3.r, b2.i ....
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a_sl = _mm_slli_si128(a, 2); // a3.r, a2.i ....
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@ -192,20 +192,19 @@ static inline void volk_gnsssdr_16ic_x2_rotator_dot_prod_16ic_xn_a_sse3(lv_16sc_
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realcacc[n_vec] = _mm_adds_epi16 (realcacc[n_vec], real);
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imagcacc[n_vec] = _mm_adds_epi16 (imagcacc[n_vec], imag);
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}
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}
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for (int n_vec=0;n_vec<num_a_vectors;n_vec++)
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for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
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{
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realcacc[n_vec] = _mm_and_si128 (realcacc[n_vec], mask_real);
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imagcacc[n_vec] = _mm_and_si128 (imagcacc[n_vec], mask_imag);
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realcacc[n_vec] = _mm_and_si128(realcacc[n_vec], mask_real);
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imagcacc[n_vec] = _mm_and_si128(imagcacc[n_vec], mask_imag);
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result = _mm_or_si128 (realcacc[n_vec], imagcacc[n_vec]);
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result = _mm_or_si128(realcacc[n_vec], imagcacc[n_vec]);
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_mm_store_si128((__m128i*)dotProductVector, result); // Store the results back into the dot product vector
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dotProduct = lv_cmake(0,0);
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for (int i = 0; i<4; ++i)
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for (int i = 0; i < 4; ++i)
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{
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dotProduct = lv_cmake(sat_adds16i(lv_creal(dotProduct), lv_creal(dotProductVector[i])),
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sat_adds16i(lv_cimag(dotProduct), lv_cimag(dotProductVector[i])));
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@ -351,18 +350,18 @@ static inline void volk_gnsssdr_16ic_x2_rotator_dot_prod_16ic_xn_u_sse3(lv_16sc_
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imag = _mm_adds_epi16(imag1, imag2);
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realcacc[n_vec] = _mm_adds_epi16 (realcacc[n_vec], real);
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imagcacc[n_vec] = _mm_adds_epi16 (imagcacc[n_vec], imag);
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realcacc[n_vec] = _mm_adds_epi16(realcacc[n_vec], real);
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imagcacc[n_vec] = _mm_adds_epi16(imagcacc[n_vec], imag);
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}
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}
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for (int n_vec=0;n_vec<num_a_vectors;n_vec++)
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for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
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{
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realcacc[n_vec] = _mm_and_si128 (realcacc[n_vec], mask_real);
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imagcacc[n_vec] = _mm_and_si128 (imagcacc[n_vec], mask_imag);
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result = _mm_or_si128 (realcacc[n_vec], imagcacc[n_vec]);
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result = _mm_or_si128(realcacc[n_vec], imagcacc[n_vec]);
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_mm_storeu_si128((__m128i*)dotProductVector, result); // Store the results back into the dot product vector
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dotProduct = lv_cmake(0,0);
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@ -392,7 +391,168 @@ static inline void volk_gnsssdr_16ic_x2_rotator_dot_prod_16ic_xn_u_sse3(lv_16sc_
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sat_adds16i(lv_cimag(_out[n_vec]), lv_cimag(tmp)));
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}
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}
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_out[2] =
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}
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#endif /* LV_HAVE_SSE3 */
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#ifdef LV_HAVE_NEON
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#include <arm_neon.h>
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static inline void volk_gnsssdr_16ic_x2_rotator_dot_prod_16ic_xn_neon(lv_16sc_t* out, const lv_16sc_t* in_common, const lv_32fc_t phase_inc, lv_32fc_t* phase, const lv_16sc_t** in_a, int num_a_vectors, unsigned int num_points)
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{
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// for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
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// {
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// result[n_vec] = lv_cmake(0,0);
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// }
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lv_16sc_t dotProduct = lv_cmake(0,0);
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const unsigned int neon_iters = num_points / 4;
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const lv_16sc_t** _in_a = in_a;
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const lv_16sc_t* _in_common = in_common;
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lv_16sc_t* _out = out;
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lv_16sc_t tmp16_;
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lv_32fc_t tmp32_;
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lv_32fc_t ___phase4 = phase_inc * phase_inc * phase_inc * phase_inc;
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__VOLK_ATTR_ALIGNED(16) float32_t __phase4_real[4] = { lv_creal(___phase4), lv_creal(___phase4), lv_creal(___phase4), lv_creal(___phase4) };
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__VOLK_ATTR_ALIGNED(16) float32_t __phase4_imag[4] = { lv_cimag(___phase4), lv_cimag(___phase4), lv_cimag(___phase4), lv_cimag(___phase4) };
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float32x4_t _phase4_real = vld1q_f32(__phase4_real);
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float32x4_t _phase4_imag = vld1q_f32(__phase4_imag);
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lv_32fc_t phase2 = (lv_32fc_t)(*phase) * phase_inc;
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lv_32fc_t phase3 = phase2 * phase_inc;
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lv_32fc_t phase4 = phase3 * phase_inc;
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__VOLK_ATTR_ALIGNED(16) float32_t __phase_real[4] = { lv_creal((*phase)), lv_creal(phase2), lv_creal(phase3), lv_creal(phase4) };
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__VOLK_ATTR_ALIGNED(16) float32_t __phase_imag[4] = { lv_cimag((*phase)), lv_cimag(phase2), lv_cimag(phase3), lv_cimag(phase4) };
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float32x4_t _phase_real = vld1q_f32(__phase_real);
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float32x4_t _phase_imag = vld1q_f32(__phase_imag);
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float32x4_t half = vdupq_n_f32(0.5f);
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int16x4x2_t tmp16;
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int32x4x2_t tmp32i;
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float32x4x2_t tmp32f, tmp_real, tmp_imag;
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float32x4_t sign, PlusHalf, Round;
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int16x4x2_t* accumulator;
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accumulator = (int16x4x2_t*)calloc(num_a_vectors, sizeof(int16x4x2_t));
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int16x4x2_t tmp_real, tmp_imag;
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for(int n_vec = 0; n_vec < num_a_vectors; n_vec++)
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{
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accumulator[n_vec].val[0] = vdup_n_s16(0);
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accumulator[n_vec].val[1] = vdup_n_s16(0);
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}
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if (neon_iters > 0)
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{
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int16x4x2_t a_val, b_val, c_val;
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for(unsigned int number = 0; number < neon_iters; number++)
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{
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/* load 4 complex numbers (int 16 bits each component) */
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tmp16 = vld2_s16((int16_t*)_in_common);
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__builtin_prefetch(_in_common + 8);
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_in_common += 4;
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/* promote them to int 32 bits */
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tmp32i.val[0] = vmovl_s16(tmp16.val[0]);
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tmp32i.val[1] = vmovl_s16(tmp16.val[1]);
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/* promote them to float 32 bits */
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tmp32f.val[0] = vcvtq_f32_s32(tmp32i.val[0]);
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tmp32f.val[1] = vcvtq_f32_s32(tmp32i.val[1]);
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/* complex multiplication of four complex samples (float 32 bits each component) */
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tmp_real.val[0] = vmulq_f32(tmp32f.val[0], _phase_real);
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tmp_real.val[1] = vmulq_f32(tmp32f.val[1], _phase_imag);
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tmp_imag.val[0] = vmulq_f32(tmp32f.val[0], _phase_imag);
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tmp_imag.val[1] = vmulq_f32(tmp32f.val[1], _phase_real);
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tmp32f.val[0] = vsubq_f32(tmp_real.val[0], tmp_real.val[1]);
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tmp32f.val[1] = vaddq_f32(tmp_imag.val[0], tmp_imag.val[1]);
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/* downcast results to int32 */
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/* in __aarch64__ we can do that with vcvtaq_s32_f32(ret1); vcvtaq_s32_f32(ret2); */
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sign = vcvtq_f32_u32((vshrq_n_u32(vreinterpretq_u32_f32(tmp32f.val[0]), 31)));
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PlusHalf = vaddq_f32(tmp32f.val[0], half);
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Round = vsubq_f32(PlusHalf, sign);
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tmp32i.val[0] = vcvtq_s32_f32(Round);
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sign = vcvtq_f32_u32((vshrq_n_u32(vreinterpretq_u32_f32(tmp32f.val[1]), 31)));
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PlusHalf = vaddq_f32(tmp32f.val[1], half);
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Round = vsubq_f32(PlusHalf, sign);
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tmp32i.val[1] = vcvtq_s32_f32(Round);
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/* downcast results to int16 */
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tmp16.val[0] = vqmovn_s32(tmp32i.val[0]);
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tmp16.val[1] = vqmovn_s32(tmp32i.val[1]);
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/* compute next four phases */
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tmp_real.val[0] = vmulq_f32(_phase_real, _phase4_real);
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tmp_real.val[1] = vmulq_f32(_phase_imag, _phase4_imag);
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tmp_imag.val[0] = vmulq_f32(_phase_real, _phase4_imag);
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tmp_imag.val[1] = vmulq_f32(_phase_imag, _phase4_real);
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_phase_real = vsubq_f32(tmp_real.val[0], tmp_real.val[1]);
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_phase_imag = vaddq_f32(tmp_imag.val[0], tmp_imag.val[1]);
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for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
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{
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a_val = vld2_s16((int16_t*)&(_in_a[n_vec][number*4])); //load (2 byte imag, 2 byte real) x 4 into 128 bits reg
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//__builtin_prefetch(_in_a[n_vec] + 8);
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// multiply the real*real and imag*imag to get real result
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// a0r*b0r|a1r*b1r|a2r*b2r|a3r*b3r
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tmp_real.val[0] = vmul_s16(a_val.val[0], b_val.val[0]);
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// a0i*b0i|a1i*b1i|a2i*b2i|a3i*b3i
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tmp_real.val[1] = vmul_s16(a_val.val[1], b_val.val[1]);
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// Multiply cross terms to get the imaginary result
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// a0r*b0i|a1r*b1i|a2r*b2i|a3r*b3i
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tmp_imag.val[0] = vmul_s16(a_val.val[0], b_val.val[1]);
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// a0i*b0r|a1i*b1r|a2i*b2r|a3i*b3r
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tmp_imag.val[1] = vmul_s16(a_val.val[1], b_val.val[0]);
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c_val.val[0] = vsub_s16(tmp_real.val[0], tmp_real.val[1]);
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c_val.val[1] = vadd_s16(tmp_imag.val[0], tmp_imag.val[1]);
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accumulator[n_vec].val[0] = vadd_s16(accumulator[n_vec].val[0], c_val.val[0]);
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accumulator[n_vec].val[1] = vadd_s16(accumulator[n_vec].val[1], c_val.val[1]);
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}
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}
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}
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for (int n_vec = 0; n_vec < num_a_vectors; n_vec++)
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{
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for(unsigned int n = sse_iters * 4; n < num_points; n++)
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{
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tmp16_ = *in_common++;
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tmp32_ = lv_cmake((float)lv_creal(tmp16_), (float)lv_cimag(tmp16_)) * (*phase);
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tmp16_ = lv_cmake((int16_t)rintf(lv_creal(tmp32_)), (int16_t)rintf(lv_cimag(tmp32_)));
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(*phase) *= phase_inc;
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lv_16sc_t tmp = tmp16_ * in_a[n_vec][n];
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_out[n_vec] = lv_cmake(sat_adds16i(lv_creal(_out[n_vec]), lv_creal(tmp)),
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sat_adds16i(lv_cimag(_out[n_vec]), lv_cimag(tmp)));
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}
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}
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}
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#endif /* LV_HAVE_NEON */
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#endif /*INCLUDED_volk_gnsssdr_16ic_xn_dot_prod_16ic_xn_H*/
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@ -132,6 +132,37 @@ static inline void volk_gnsssdr_16ic_x2_rotator_dotprodxnpuppet_16ic_u_sse3(lv_1
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#endif // SSE3
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#ifdef LV_HAVE_NEON
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static inline void volk_gnsssdr_16ic_x2_rotator_dotprodxnpuppet_16ic_neon(lv_16sc_t* result, const lv_16sc_t* local_code, const lv_16sc_t* in, unsigned int num_points)
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{
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// phases must be normalized. Phase rotator expects a complex exponential input!
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float rem_carrier_phase_in_rad = 0.345;
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float phase_step_rad = 0.123;
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lv_32fc_t phase[1];
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phase[0] = lv_cmake(cos(rem_carrier_phase_in_rad), -sin(rem_carrier_phase_in_rad));
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lv_32fc_t phase_inc[1];
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phase_inc[0] = lv_cmake(cos(phase_step_rad), -sin(phase_step_rad));
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int num_a_vectors = 3;
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lv_16sc_t** in_a = (lv_16sc_t**)volk_gnsssdr_malloc(sizeof(lv_16sc_t*) * num_a_vectors, volk_gnsssdr_get_alignment());
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for(unsigned int n = 0; n < num_a_vectors; n++)
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{
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in_a[n] = (lv_16sc_t*)volk_gnsssdr_malloc(sizeof(lv_16sc_t)*num_points, volk_gnsssdr_get_alignment());
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memcpy(in_a[n], in, sizeof(lv_16sc_t)*num_points);
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}
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result = (lv_16sc_t*)calloc(num_points, sizeof(lv_16sc_t));
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volk_gnsssdr_16ic_x2_rotator_dot_prod_16ic_xn_u_sse3(result, local_code, phase_inc[0], phase, (const lv_16sc_t**) in_a, num_a_vectors, num_points);
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for(unsigned int n = 0; n < num_a_vectors; n++)
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{
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volk_gnsssdr_free(in_a[n]);
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}
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volk_gnsssdr_free(in_a);
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}
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#endif // NEON
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#endif // INCLUDED_volk_gnsssdr_16ic_x2_rotator_dotprodxnpuppet_16ic_H
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