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1 - Check for any exception in tracking_dump_reader.cc and tracking_true_obs_reader.cc when manipulating files, not just a specific exception, for compatibility with the Linux OS running in the Zynq board. 2 - gps_l1_ca_dll_pll_tracking_test.cc uses the c_aid_tracking class instead of the tracking one. 3 - Implemented the code that runs the unit test of the GPS tracking algorithm using the HW accelerator in the FPGA

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This commit is contained in:
mmajoral 2017-03-13 09:59:16 +01:00
parent 8927543028
commit c6eda22bab
11 changed files with 559 additions and 174 deletions
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78
src/algorithms/tracking/adapters/gps_l1_ca_dll_pll_c_aid_tracking_fpga.cc
View File

@ -1,8 +1,9 @@
/*!
* \file gps_l1_ca_dll_pll_c_aid_tracking.cc
* \file gps_l1_ca_dll_pll_c_aid_tracking_fpga.cc
* \brief Implementation of an adapter of a DLL+PLL tracking loop block
* for GPS L1 C/A to a TrackingInterface
* \author Carlos Aviles, 2010. carlos.avilesr(at)googlemail.com
* \author Marc Majoral, 2017. mmajoral(at)cttc.cat
* Carlos Aviles, 2010. carlos.avilesr(at)googlemail.com
* Javier Arribas, 2011. jarribas(at)cttc.es
*
* Code DLL + carrier PLL according to the algorithms described in:
@ -12,7 +13,7 @@
*
* -------------------------------------------------------------------------
*
* Copyright (C) 2010-2015 (see AUTHORS file for a list of contributors)
* Copyright (C) 2010-2017 (see AUTHORS file for a list of contributors)
*
* GNSS-SDR is a software defined Global Navigation
* Satellite Systems receiver
@ -56,7 +57,6 @@ GpsL1CaDllPllCAidTrackingFpga::GpsL1CaDllPllCAidTrackingFpga(
int f_if;
bool dump;
std::string dump_filename;
//std::string default_item_type = "gr_complex";
std::string default_item_type = "cshort";
float pll_bw_hz;
float pll_bw_narrow_hz;
@ -64,7 +64,6 @@ GpsL1CaDllPllCAidTrackingFpga::GpsL1CaDllPllCAidTrackingFpga(
float dll_bw_narrow_hz;
float early_late_space_chips;
item_type_ = configuration->property(role + ".item_type", default_item_type);
//vector_length = configuration->property(role + ".vector_length", 2048);
fs_in = configuration->property("GNSS-SDR.internal_fs_hz", 2048000);
f_if = configuration->property(role + ".if", 0);
dump = configuration->property(role + ".dump", false);
@ -82,24 +81,7 @@ GpsL1CaDllPllCAidTrackingFpga::GpsL1CaDllPllCAidTrackingFpga(
vector_length = std::round(fs_in / (GPS_L1_CA_CODE_RATE_HZ / GPS_L1_CA_CODE_LENGTH_CHIPS));
//################# MAKE TRACKING GNURadio object ###################
// if (item_type_.compare("gr_complex") == 0)
// {
// item_size_ = sizeof(gr_complex);
// tracking_cc = gps_l1_ca_dll_pll_c_aid_make_tracking_cc(
// f_if,
// fs_in,
// vector_length,
// dump,
// dump_filename,
// pll_bw_hz,
// dll_bw_hz,
// pll_bw_narrow_hz,
// dll_bw_narrow_hz,
// extend_correlation_ms,
// early_late_space_chips);
// DLOG(INFO) << "tracking(" << tracking_cc->unique_id() << ")";
// }
// else if(item_type_.compare("cshort") == 0)
if(item_type_.compare("cshort") == 0)
{
item_size_ = sizeof(lv_16sc_t);
@ -119,8 +101,8 @@ GpsL1CaDllPllCAidTrackingFpga::GpsL1CaDllPllCAidTrackingFpga(
}
else
{
//item_size_ = sizeof(gr_complex);
item_size_ = sizeof(lv_16sc_t);
item_size_ = sizeof(lv_16sc_t);
// LOG(WARNING) << item_type_ << " unknown tracking item type";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
}
@ -129,17 +111,14 @@ GpsL1CaDllPllCAidTrackingFpga::GpsL1CaDllPllCAidTrackingFpga(
GpsL1CaDllPllCAidTrackingFpga::~GpsL1CaDllPllCAidTrackingFpga()
{}
{
printf("gspl1cadllpllcaidtrackingfpga destructor called\n");
}
void GpsL1CaDllPllCAidTrackingFpga::start_tracking()
{
// if (item_type_.compare("gr_complex") == 0)
// {
// tracking_cc->start_tracking();
// }
// else if (item_type_.compare("cshort") == 0)
if (item_type_.compare("cshort") == 0)
{
tracking_fpga_sc->start_tracking();
@ -158,11 +137,6 @@ void GpsL1CaDllPllCAidTrackingFpga::set_channel(unsigned int channel)
{
channel_ = channel;
// if (item_type_.compare("gr_complex") == 0)
// {
// tracking_cc->set_channel(channel);
// }
// else if (item_type_.compare("cshort") == 0)
if (item_type_.compare("cshort") == 0)
{
tracking_fpga_sc->set_channel(channel);
@ -170,17 +144,12 @@ void GpsL1CaDllPllCAidTrackingFpga::set_channel(unsigned int channel)
else
{
// LOG(WARNING) << item_type_ << " unknown tracking item type";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
}
}
void GpsL1CaDllPllCAidTrackingFpga::set_gnss_synchro(Gnss_Synchro* p_gnss_synchro)
{
// if (item_type_.compare("gr_complex") == 0)
// {
// tracking_cc->set_gnss_synchro(p_gnss_synchro);
// }
// else if (item_type_.compare("cshort") == 0)
if (item_type_.compare("cshort") == 0)
{
tracking_fpga_sc->set_gnss_synchro(p_gnss_synchro);
@ -188,7 +157,7 @@ void GpsL1CaDllPllCAidTrackingFpga::set_gnss_synchro(Gnss_Synchro* p_gnss_synchr
else
{
// LOG(WARNING) << item_type_ << " unknown tracking item type";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
}
}
@ -204,32 +173,29 @@ void GpsL1CaDllPllCAidTrackingFpga::disconnect(gr::top_block_sptr top_block)
//nothing to disconnect, now the tracking uses gr_sync_decimator
}
// CONVERT TO SOURCE
gr::basic_block_sptr GpsL1CaDllPllCAidTrackingFpga::get_left_block()
{
// if (item_type_.compare("gr_complex") == 0)
// {
// return tracking_cc;
// }
// else if (item_type_.compare("cshort") == 0)
if (item_type_.compare("cshort") == 0)
{
return tracking_fpga_sc;
}
else
{
// LOG(WARNING) << item_type_ << " unknown tracking item type";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
//LOG(WARNING) << item_type_ << " unknown tracking item type";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
return nullptr;
}
}
gr::basic_block_sptr GpsL1CaDllPllCAidTrackingFpga::get_right_block()
{
// if (item_type_.compare("gr_complex") == 0)
// {
// return tracking_cc;
// }
// else if (item_type_.compare("cshort") == 0)
if (item_type_.compare("cshort") == 0)
{
return tracking_fpga_sc;
@ -237,7 +203,7 @@ gr::basic_block_sptr GpsL1CaDllPllCAidTrackingFpga::get_right_block()
else
{
//LOG(WARNING) << item_type_ << " unknown tracking item type";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
LOG(WARNING) << item_type_ << " the tracking item type for the FPGA tracking test has to be cshort";
return nullptr;
}
}

12
src/algorithms/tracking/adapters/gps_l1_ca_dll_pll_c_aid_tracking_fpga.h
View File

@ -1,8 +1,9 @@
/*!
* \file gps_l1_ca_dll_pll_c_aid_tracking.h
* \file gps_l1_ca_dll_pll_c_aid_tracking_fpga.h
* \brief Interface of an adapter of a DLL+PLL tracking loop block
* for GPS L1 C/A to a TrackingInterface
* \author Carlos Aviles, 2010. carlos.avilesr(at)googlemail.com
* \author Marc Majoral, 2017. mmajoral(at)cttc.cat
* Carlos Aviles, 2010. carlos.avilesr(at)googlemail.com
* Javier Arribas, 2011. jarribas(at)cttc.es
*
* Code DLL + carrier PLL according to the algorithms described in:
@ -12,7 +13,7 @@
*
* -------------------------------------------------------------------------
*
* Copyright (C) 2010-2015 (see AUTHORS file for a list of contributors)
* Copyright (C) 2010-2017 (see AUTHORS file for a list of contributors)
*
* GNSS-SDR is a software defined Global Navigation
* Satellite Systems receiver
@ -40,8 +41,6 @@
#include <string>
#include "tracking_interface.h"
//#include "gps_l1_ca_dll_pll_c_aid_tracking_cc.h"
//#include "gps_l1_ca_dll_pll_c_aid_tracking_sc.h"
#include "gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc.h"
@ -78,6 +77,7 @@ public:
void connect(gr::top_block_sptr top_block);
void disconnect(gr::top_block_sptr top_block);
// CONVERT TO SOURCE
gr::basic_block_sptr get_left_block();
gr::basic_block_sptr get_right_block();
@ -97,8 +97,6 @@ public:
void start_tracking();
private:
//gps_l1_ca_dll_pll_c_aid_tracking_cc_sptr tracking_cc;
//gps_l1_ca_dll_pll_c_aid_tracking_sc_sptr tracking_sc;
gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc_sptr tracking_fpga_sc;
size_t item_size_;
std::string item_type_;

32
src/algorithms/tracking/gnuradio_blocks/gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc.cc
View File

@ -1,11 +1,12 @@
/*!
* \file gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc.cc
* \brief Implementation of a code DLL + carrier PLL tracking block
* \author Javier Arribas, 2015. jarribas(at)cttc.es
* \author Marc Majoral, 2017. mmajoral(at)cttc.cat
* Javier Arribas, 2015. jarribas(at)cttc.es
*
* -------------------------------------------------------------------------
*
* Copyright (C) 2010-2015 (see AUTHORS file for a list of contributors)
* Copyright (C) 2010-2017 (see AUTHORS file for a list of contributors)
*
* GNSS-SDR is a software defined Global Navigation
* Satellite Systems receiver
@ -77,17 +78,6 @@ gps_l1_ca_dll_pll_c_aid_make_tracking_fpga_sc(
}
void gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc::forecast (int noutput_items,
gr_vector_int &ninput_items_required)
{
if (noutput_items != 0)
{
ninput_items_required[0] = static_cast<int>(d_vector_length) * 2; //set the required available samples in each call
}
}
void gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc::msg_handler_preamble_index(pmt::pmt_t msg)
{
//pmt::print(msg);
@ -112,8 +102,9 @@ gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc::gps_l1_ca_dll_pll_c_aid_tracking_fpga_
float dll_bw_narrow_hz,
int extend_correlation_ms,
float early_late_space_chips) :
gr::block("gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc", gr::io_signature::make(1, 1, sizeof(lv_16sc_t)),
gr::block("gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc", gr::io_signature::make(0, 0, sizeof(lv_16sc_t)),
gr::io_signature::make(1, 1, sizeof(Gnss_Synchro)))
{
// Telemetry bit synchronization message port input
this->message_port_register_in(pmt::mp("preamble_timestamp_s"));
@ -318,17 +309,19 @@ gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc::~gps_l1_ca_dll_pll_c_aid_tracking_fpga
int gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc::general_work (int noutput_items __attribute__((unused)), gr_vector_int &ninput_items __attribute__((unused)),
gr_vector_const_void_star &input_items, gr_vector_void_star &output_items)
{
// Block input data and block output stream pointers
const lv_16sc_t* in = (lv_16sc_t*) input_items[0]; //PRN start block alignment
Gnss_Synchro **out = (Gnss_Synchro **) &output_items[0];
// GNSS_SYNCHRO OBJECT to interchange data between tracking->telemetry_decoder
Gnss_Synchro current_synchro_data = Gnss_Synchro();
// process vars
double code_error_filt_secs_Ti = 0.0;
double CURRENT_INTEGRATION_TIME_S = 0.0;
double CORRECTED_INTEGRATION_TIME_S = 0.0;
if (d_enable_tracking == true)
{
@ -351,12 +344,15 @@ int gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc::general_work (int noutput_items __
current_synchro_data.Carrier_Doppler_hz = d_carrier_doppler_hz;
*out[0] = current_synchro_data;
consume_each(samples_offset); // shift input to perform alignment with local replica
multicorrelator_fpga_8sc.set_initial_sample(samples_offset);
return 1;
}
// ################# CARRIER WIPEOFF AND CORRELATORS ##############################
// perform carrier wipe-off and compute Early, Prompt and Late correlation
multicorrelator_fpga_8sc.set_input_output_vectors(d_correlator_outs_16sc, in);
//multicorrelator_fpga_8sc.set_input_output_vectors(d_correlator_outs_16sc, in);
multicorrelator_fpga_8sc.set_output_vectors(d_correlator_outs_16sc);
multicorrelator_fpga_8sc.Carrier_wipeoff_multicorrelator_resampler(d_rem_carrier_phase_rad,
d_carrier_phase_step_rad,
d_rem_code_phase_chips,
@ -645,6 +641,8 @@ int gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc::general_work (int noutput_items __
void gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc::set_channel(unsigned int channel)
{
d_channel = channel;
multicorrelator_fpga_8sc.set_channel(d_channel);
LOG(INFO) << "Tracking Channel set to " << d_channel;
// ############# ENABLE DATA FILE LOG #################
if (d_dump == true)

10
src/algorithms/tracking/gnuradio_blocks/gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc.h
View File

@ -1,7 +1,8 @@
/*!
* \file gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc.h
* \brief Interface of a code DLL + carrier PLL tracking block
* \author Carlos Aviles, 2010. carlos.avilesr(at)googlemail.com
* \author Marc Majoral, 2017. mmajoral(at)cttc.cat
* Carlos Aviles, 2010. carlos.avilesr(at)googlemail.com
* Javier Arribas, 2011. jarribas(at)cttc.es
*
* Code DLL + carrier PLL according to the algorithms described in:
@ -11,7 +12,7 @@
*
* -------------------------------------------------------------------------
*
* Copyright (C) 2010-2015 (see AUTHORS file for a list of contributors)
* Copyright (C) 2010-2017 (see AUTHORS file for a list of contributors)
*
* GNSS-SDR is a software defined Global Navigation
* Satellite Systems receiver
@ -48,7 +49,6 @@
#include "gnss_synchro.h"
#include "tracking_2nd_DLL_filter.h"
#include "tracking_FLL_PLL_filter.h"
//#include "cpu_multicorrelator_16sc.h"
#include "fpga_multicorrelator_8sc.h"
class gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc;
@ -86,8 +86,6 @@ public:
int general_work (int noutput_items, gr_vector_int &ninput_items,
gr_vector_const_void_star &input_items, gr_vector_void_star &output_items);
void forecast (int noutput_items, gr_vector_int &ninput_items_required);
private:
friend gps_l1_ca_dll_pll_c_aid_tracking_fpga_sc_sptr
gps_l1_ca_dll_pll_c_aid_make_tracking_fpga_sc(long if_freq,
@ -132,8 +130,6 @@ private:
float* d_local_code_shift_chips;
//gr_complex* d_correlator_outs;
lv_16sc_t* d_correlator_outs_16sc;
//cpu_multicorrelator multicorrelator_cpu;
//cpu_multicorrelator_16sc multicorrelator_cpu_16sc;
fpga_multicorrelator_8sc multicorrelator_fpga_8sc;
// remaining code phase and carrier phase between tracking loops

370
src/algorithms/tracking/libs/fpga_multicorrelator_8sc.cc
View File

@ -1,15 +1,17 @@
/*!
* \file fpga_multicorrelator_8sc.cc
* \brief High optimized CPU vector multiTAP correlator class
* \brief High optimized FPGA vector correlator class
* \authors <ul>
* <li> Marc Majoral, 2017. mmajoral(at)cttc.cat
* <li> Javier Arribas, 2015. jarribas(at)cttc.es
* </ul>
*
* Class that implements a high optimized vector multiTAP correlator class for CPUs
* Class that controls and executes a high optimized vector correlator
* class in the FPGA
*
* -------------------------------------------------------------------------
*
* Copyright (C) 2010-2015 (see AUTHORS file for a list of contributors)
* Copyright (C) 2010-2017 (see AUTHORS file for a list of contributors)
*
* GNSS-SDR is a software defined Global Navigation
* Satellite Systems receiver
@ -35,31 +37,61 @@
#include "fpga_multicorrelator_8sc.h"
#include <cmath>
// FPGA stuff
#include <new>
// libraries used by DMA test code and GIPO test code
#include <stdio.h>
#include <fcntl.h>
#include <unistd.h>
#include <errno.h>
// libraries used by DMA test code
#include <sys/stat.h>
#include <stdint.h>
#include <unistd.h>
#include <assert.h>
// libraries used by GPIO test code
#include <stdlib.h>
#include <signal.h>
#include <sys/mman.h>
// logging
#include <glog/logging.h>
#define PAGE_SIZE 0x10000
#define MAX_LENGTH_DEVICEIO_NAME 50
#define CODE_RESAMPLER_NUM_BITS_PRECISION 20
#define CODE_PHASE_STEP_CHIPS_NUM_NBITS CODE_RESAMPLER_NUM_BITS_PRECISION
#define pwrtwo(x) (1 << (x))
#define MAX_CODE_RESAMPLER_COUNTER pwrtwo(CODE_PHASE_STEP_CHIPS_NUM_NBITS) // 2^CODE_PHASE_STEP_CHIPS_NUM_NBITS
#define PHASE_CARR_NBITS 32
#define PHASE_CARR_NBITS_INT 1
#define PHASE_CARR_NBITS_FRAC PHASE_CARR_NBITS - PHASE_CARR_NBITS_INT
bool fpga_multicorrelator_8sc::init(
int max_signal_length_samples,
int n_correlators)
{
// ALLOCATE MEMORY FOR INTERNAL vectors
size_t size = max_signal_length_samples * sizeof(lv_16sc_t);
d_n_correlators = n_correlators;
d_local_codes_resampled = static_cast<lv_16sc_t**>(volk_gnsssdr_malloc(n_correlators * sizeof(lv_16sc_t*), volk_gnsssdr_get_alignment()));
for (int n = 0; n < n_correlators; n++)
{
d_local_codes_resampled[n] = static_cast<lv_16sc_t*>(volk_gnsssdr_malloc(size, volk_gnsssdr_get_alignment()));
}
// FPGA stuff
// instantiate variable length vectors
d_initial_index = static_cast<unsigned*>(volk_gnsssdr_malloc(n_correlators * sizeof(unsigned), volk_gnsssdr_get_alignment()));
d_initial_interp_counter = static_cast<unsigned*>(volk_gnsssdr_malloc(n_correlators * sizeof(unsigned), volk_gnsssdr_get_alignment()));
return true;
}
void fpga_multicorrelator_8sc::set_initial_sample(int samples_offset)
{
d_initial_sample_counter = samples_offset;
}
bool fpga_multicorrelator_8sc::set_local_code_and_taps(
int code_length_chips,
@ -70,32 +102,35 @@ bool fpga_multicorrelator_8sc::set_local_code_and_taps(
d_shifts_chips = shifts_chips;
d_code_length_chips = code_length_chips;
// FPGA parameters
d_gps_code = static_cast<char*>(volk_gnsssdr_malloc(code_length_chips * sizeof(char), volk_gnsssdr_get_alignment()));
fpga_multicorrelator_8sc::fpga_configure_tracking_gps_local_code();
return true;
}
bool fpga_multicorrelator_8sc::set_input_output_vectors(lv_16sc_t* corr_out, const lv_16sc_t* sig_in)
bool fpga_multicorrelator_8sc::set_output_vectors(lv_16sc_t* corr_out)
{
// Save CPU pointers
d_sig_in = sig_in;
d_corr_out = corr_out;
return true;
}
void fpga_multicorrelator_8sc::update_local_code(int correlator_length_samples, float rem_code_phase_chips, float code_phase_step_chips)
{
volk_gnsssdr_16ic_xn_resampler_16ic_xn(d_local_codes_resampled,
d_local_code_in,
rem_code_phase_chips,
code_phase_step_chips,
d_shifts_chips,
d_code_length_chips,
d_n_correlators,
correlator_length_samples);
d_rem_code_phase_chips = rem_code_phase_chips;
fpga_multicorrelator_8sc::fpga_compute_code_shift_parameters();
fpga_multicorrelator_8sc::fpga_configure_code_parameters_in_fpga();
}
@ -106,23 +141,40 @@ bool fpga_multicorrelator_8sc::Carrier_wipeoff_multicorrelator_resampler(
float code_phase_step_chips,
int signal_length_samples)
{
update_local_code(signal_length_samples, rem_code_phase_chips, code_phase_step_chips);
// Regenerate phase at each call in order to avoid numerical issues
lv_32fc_t phase_offset_as_complex[1];
phase_offset_as_complex[0] = lv_cmake(std::cos(rem_carrier_phase_in_rad), -std::sin(rem_carrier_phase_in_rad));
// call VOLK_GNSSSDR kernel
volk_gnsssdr_16ic_x2_rotator_dot_prod_16ic_xn(d_corr_out, d_sig_in, std::exp(lv_32fc_t(0, -phase_step_rad)), phase_offset_as_complex, (const lv_16sc_t**)d_local_codes_resampled, d_n_correlators, signal_length_samples);
d_rem_carrier_phase_in_rad = rem_carrier_phase_in_rad;
d_code_phase_step_chips = code_phase_step_chips;
d_phase_step_rad = phase_step_rad;
d_correlator_length_samples = signal_length_samples;
fpga_multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga();
fpga_multicorrelator_8sc::fpga_configure_signal_parameters_in_fpga();
fpga_multicorrelator_8sc::fpga_launch_multicorrelator_fpga();
int irq_count;
ssize_t nb;
// wait for interrupt
nb=read(d_fd, &irq_count, sizeof(irq_count));
if (nb != sizeof(irq_count))
{
printf("Tracking_module Read failed to retrive 4 bytes!\n");
printf("Tracking_module Interrupt number %d\n", irq_count);
}
fpga_multicorrelator_8sc::read_tracking_gps_results();
return true;
}
fpga_multicorrelator_8sc::fpga_multicorrelator_8sc()
{
d_sig_in = nullptr;
d_local_code_in = nullptr;
d_shifts_chips = nullptr;
d_corr_out = nullptr;
d_local_codes_resampled = nullptr;
d_code_length_chips = 0;
d_n_correlators = 0;
}
@ -130,28 +182,19 @@ fpga_multicorrelator_8sc::fpga_multicorrelator_8sc()
fpga_multicorrelator_8sc::~fpga_multicorrelator_8sc()
{
if(d_local_codes_resampled != nullptr)
{
fpga_multicorrelator_8sc::free();
}
close(d_fd);
}
bool fpga_multicorrelator_8sc::free()
{
// Free memory
if (d_local_codes_resampled != nullptr)
{
for (int n = 0; n < d_n_correlators; n++)
{
volk_gnsssdr_free(d_local_codes_resampled[n]);
}
volk_gnsssdr_free(d_local_codes_resampled);
d_local_codes_resampled = nullptr;
}
// unlock the hardware
fpga_multicorrelator_8sc::unlock_channel(); // unlock the channel
// FPGA stuff
// free the FPGA dynamically created variables
if (d_initial_index != nullptr)
{
@ -166,11 +209,238 @@ bool fpga_multicorrelator_8sc::free()
d_initial_interp_counter = nullptr;
}
if (d_gps_code != nullptr)
{
volk_gnsssdr_free(d_gps_code);
d_gps_code = nullptr;
}
return true;
}
void fpga_multicorrelator_8sc::set_channel(unsigned int channel)
{
d_channel = channel;
snprintf(d_device_io_name, MAX_LENGTH_DEVICEIO_NAME, "/dev/uio%d",d_channel);
printf("Opening Device Name : %s\n", d_device_io_name);
if ((d_fd = open(d_device_io_name, O_RDWR | O_SYNC )) == -1)
{
LOG(WARNING) << "Cannot open deviceio" << d_device_io_name;
}
d_map_base = (volatile unsigned *)mmap(NULL, PAGE_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, d_fd,0);
if (d_map_base == (void *) -1)
{
LOG(WARNING) << "Cannot map the FPGA tracking module " << d_channel << "into user memory";
}
// sanity check : check test register
unsigned writeval = 0x55AA;
unsigned readval;
readval = fpga_multicorrelator_8sc::fpga_acquisition_test_register(writeval);
if (writeval != readval)
{
LOG(WARNING) << "Test register sanity check failed";
}
else
{
printf("Test register sanity check success !\n");
}
}
unsigned fpga_multicorrelator_8sc::fpga_acquisition_test_register(unsigned writeval)
{
unsigned readval;
// write value to test register
d_map_base[15] = writeval;
// read value from test register
readval = d_map_base[15];
// return read value
return readval;
}
void fpga_multicorrelator_8sc::fpga_configure_tracking_gps_local_code(void)
{
int k,s;
unsigned temp;
unsigned *ena_write_signals;
ena_write_signals = new unsigned[d_n_correlators];
ena_write_signals[0]= 0x00000000;
ena_write_signals[1]= 0x20000000;
for (s=2;s<d_n_correlators;s++)
{
ena_write_signals[s]= ena_write_signals[s-1]*2; //0x40000000;
}
for (s=0;s<d_n_correlators;s++)
{
// clear memory address counter
d_map_base[11] = 0x10000000;
// write correlator 0
for (k=0;k< d_code_length_chips;k++)
{
if (lv_creal(d_local_code_in[k]) == 1)
{
temp = 1;
}
else
{
temp = 0;
}
d_map_base[11] = 0x0C000000 | (temp & 0xFFFF) | ena_write_signals[s];
}
}
delete [] ena_write_signals;
}
void fpga_multicorrelator_8sc::fpga_compute_code_shift_parameters(void)
{
float tempvalues[3];
float tempvalues2[3];
float tempvalues3[3];
int i;
for (i=0;i<d_n_correlators;i++)
{
// initial index calculation
tempvalues[i] = floor(d_shifts_chips[i] + d_rem_code_phase_chips);
if (tempvalues[i] < 0)
{
tempvalues2[i] = tempvalues[i] + d_code_length_chips; // % operator does not work as in Matlab with negative numbers
}
else
{
tempvalues2[i] = tempvalues[i];
}
d_initial_index[i] = (unsigned) ((int) tempvalues2[i]) % d_code_length_chips;
// initial interpolator counter calculation
tempvalues3[i] = fmod(d_shifts_chips[i]+ d_rem_code_phase_chips,1.0);
if (tempvalues3[i] < 0)
{
tempvalues3[i] = tempvalues3[i] + 1.0; // fmod operator does not work as in Matlab with negative numbers
}
d_initial_interp_counter[i] = (unsigned) floor(MAX_CODE_RESAMPLER_COUNTER * tempvalues3[i]);
}
}
void fpga_multicorrelator_8sc::fpga_configure_code_parameters_in_fpga(void)
{
int i;
for (i=0;i<d_n_correlators;i++)
{
d_map_base[1+i] = d_initial_index[i];
d_map_base[1 + d_n_correlators + i] = d_initial_interp_counter[i];
}
d_map_base[8] = d_code_length_chips - 1; // number of samples - 1
}
void fpga_multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga(void)
{
float d_rem_carrier_phase_in_rad_temp;
float d_phase_step_rad_int_temp;
d_code_phase_step_chips_num = (unsigned) roundf(MAX_CODE_RESAMPLER_COUNTER*d_code_phase_step_chips);
if (d_rem_carrier_phase_in_rad > M_PI)
{
d_rem_carrier_phase_in_rad_temp = -2*M_PI + d_rem_carrier_phase_in_rad;
}
else if (d_rem_carrier_phase_in_rad < - M_PI)
{
d_rem_carrier_phase_in_rad_temp = 2*M_PI + d_rem_carrier_phase_in_rad;
}
else
{
d_rem_carrier_phase_in_rad_temp = d_rem_carrier_phase_in_rad;
}
d_rem_carr_phase_rad_int = (int) roundf((fabs(d_rem_carrier_phase_in_rad_temp)/M_PI)*pow(2, PHASE_CARR_NBITS_FRAC));
if (d_rem_carrier_phase_in_rad_temp < 0)
{
d_rem_carr_phase_rad_int = -d_rem_carr_phase_rad_int;
}
d_phase_step_rad_int = (int) roundf((fabs(d_phase_step_rad)/M_PI)*pow(2, PHASE_CARR_NBITS_FRAC)); // the FPGA accepts a range for the phase step between -pi and +pi
if (d_phase_step_rad < 0)
{
d_phase_step_rad_int = -d_phase_step_rad_int;
}
}
void fpga_multicorrelator_8sc::fpga_configure_signal_parameters_in_fpga(void)
{
d_map_base[0] = d_code_phase_step_chips_num;
d_map_base[7] = d_correlator_length_samples - 1;
d_map_base[9] = d_rem_carr_phase_rad_int;
d_map_base[10] = d_phase_step_rad_int;
d_map_base[12] = 0; // lock the channel
d_map_base[13] = d_initial_sample_counter;
}
void fpga_multicorrelator_8sc::fpga_launch_multicorrelator_fpga(void)
{
// enable interrupts
int reenable = 1;
write(d_fd, (void *)&reenable, sizeof(int));
d_map_base[14] = 0; // writing anything to reg 14 launches the tracking
}
void fpga_multicorrelator_8sc::read_tracking_gps_results(void)
{
int *readval_real;
int *readval_imag;
int k;
readval_real= new int[d_n_correlators];
readval_imag= new int[d_n_correlators];
for (k=0;k<d_n_correlators;k++)
{
readval_real[k] = d_map_base[1 + k];
if (readval_real[k] >= 1048576) // 0x100000 (21 bits two's complement)
{
readval_real[k] = -2097152 + readval_real[k];
}
readval_real[k] = readval_real[k]*2; // the results are shifted two bits to the left due to the complex multiplier in the FPGA
}
for (k=0;k<d_n_correlators;k++)
{
readval_imag[k] = d_map_base[1 + d_n_correlators + k];
if (readval_imag[k] >= 1048576) // 0x100000 (21 bits two's complement)
{
readval_imag[k] = -2097152 + readval_imag[k];
}
readval_imag[k] = readval_imag[k]*2; // the results are shifted two bits to the left due to the complex multiplier in the FPGA
}
for (k=0;k<d_n_correlators;k++)
{
d_corr_out[k] = lv_cmake(readval_real[k], readval_imag[k]);
}
delete[] readval_real;
delete[] readval_imag;
}
void fpga_multicorrelator_8sc::unlock_channel(void)
{
// unlock the channel to let the next samples go through
d_map_base[12] = 1; // unlock the channel
}

61
src/algorithms/tracking/libs/fpga_multicorrelator_8sc.h
View File

@ -1,15 +1,17 @@
/*!
* \file fpga_multicorrelator_8sc.h
* \brief High optimized CPU vector multiTAP correlator class for lv_16sc_t (short int complex)
* \brief High optimized FPGA vector correlator class for lv_16sc_t (short int complex)
* \authors <ul>
* <li> Marc Majoral, 2017. mmajoral(at)cttc.cat
* <li> Javier Arribas, 2016. jarribas(at)cttc.es
* </ul>
*
* Class that implements a high optimized vector multiTAP correlator class for CPUs
* Class that controls and executes a high optimized vector correlator
* class in the FPGA
*
* -------------------------------------------------------------------------
*
* Copyright (C) 2010-2015 (see AUTHORS file for a list of contributors)
* Copyright (C) 2010-2017 (see AUTHORS file for a list of contributors)
*
* GNSS-SDR is a software defined Global Navigation
* Satellite Systems receiver
@ -37,8 +39,8 @@
#include <volk_gnsssdr/volk_gnsssdr.h>
// FPGA specific stuff
//#define MAX_NUM_CORRELATORS 3
#define MAX_LENGTH_DEVICEIO_NAME 50
/*!
* \brief Class that implements carrier wipe-off and correlators.
@ -50,37 +52,56 @@ public:
~fpga_multicorrelator_8sc();
bool init(int max_signal_length_samples, int n_correlators);
bool set_local_code_and_taps(int code_length_chips, const lv_16sc_t* local_code_in, float *shifts_chips);
bool set_input_output_vectors(lv_16sc_t* corr_out, const lv_16sc_t* sig_in);
bool set_output_vectors(lv_16sc_t* corr_out);
void update_local_code(int correlator_length_samples, float rem_code_phase_chips, float code_phase_step_chips);
bool Carrier_wipeoff_multicorrelator_resampler(float rem_carrier_phase_in_rad, float phase_step_rad, float rem_code_phase_chips, float code_phase_step_chips, int signal_length_samples);
bool free();
void set_channel(unsigned int channel);
void set_initial_sample(int samples_offset);
private:
// Allocate the device input vectors
const lv_16sc_t *d_sig_in;
lv_16sc_t **d_local_codes_resampled;
const lv_16sc_t *d_local_code_in;
lv_16sc_t *d_corr_out;
float *d_shifts_chips;
int d_code_length_chips;
int d_n_correlators;
// FPGA parameters
unsigned d_nsamples;
unsigned d_code_length;
// data related to the hardware module and the driver
char d_device_io_name[MAX_LENGTH_DEVICEIO_NAME]; // driver io name
int d_fd; // driver descriptor
volatile unsigned *d_map_base; // driver memory map
// configuration data received from the interface
unsigned int d_channel; // channel number
unsigned d_ncorrelators; // number of correlators
unsigned d_correlator_length_samples;
float d_rem_code_phase_chips;
float d_code_phase_step_chips;
float d_rem_carrier_phase_in_rad;
float d_phase_step_rad;
// configuration data computed in the format that the FPGA expects
unsigned *d_initial_index;
unsigned *d_initial_interp_counter;
unsigned d_code_phase_step_chips_num;
unsigned d_ncorrelators;
unsigned *d_initial_index; //initial_index[MAX_NUM_CORRELATORS];
unsigned *d_initial_interp_counter; //initial_interp_counter[MAX_NUM_CORRELATORS];
int d_rem_carr_phase_rad_int;
int d_phase_step_rad_int;
unsigned d_initial_sample_counter;
char *d_gps_code;
// FPGA registers
unsigned map_base[16];
// FPGA private functions
unsigned fpga_acquisition_test_register(unsigned writeval);
void fpga_configure_tracking_gps_local_code(void);
void fpga_compute_code_shift_parameters(void);
void fpga_configure_code_parameters_in_fpga(void);
void fpga_compute_signal_parameters_in_fpga(void);
void fpga_configure_signal_parameters_in_fpga(void);
void fpga_launch_multicorrelator_fpga(void);
void read_tracking_gps_results(void);
void unlock_channel(void);
};
#endif /* GNSS_SDR_CPU_MULTICORRELATOR_H_ */
#endif /* GNSS_SDR_FPGA_MULTICORRELATOR_H_ */

3
src/tests/test_main.cc
View File

@ -132,6 +132,9 @@ DECLARE_string(log_dir);
#endif
#endif
#if FPGA_BLOCKS_TEST
#include "unit-tests/signal-processing-blocks/tracking/gps_l1_ca_dll_pll_tracking_test_fpga.cc"
#endif
// For GPS NAVIGATION (L1)
concurrent_queue<Gps_Acq_Assist> global_gps_acq_assist_queue;

2
src/tests/unit-tests/signal-processing-blocks/libs/tracking_dump_reader.cc
View File

@ -54,7 +54,7 @@ bool tracking_dump_reader::read_binary_obs()
d_dump_file.read((char *) &aux2, sizeof(double));
}
catch (const std::ifstream::failure &e)
catch (const std::exception &e)
{
return false;
}

2
src/tests/unit-tests/signal-processing-blocks/libs/tracking_true_obs_reader.cc
View File

@ -40,7 +40,7 @@ bool tracking_true_obs_reader::read_binary_obs()
d_dump_file.read((char *) &prn_delay_chips, sizeof(double));
d_dump_file.read((char *) &tow, sizeof(double));
}
catch (const std::ifstream::failure &e)
catch (const std::exception &e)
{
return false;
}

20
src/tests/unit-tests/signal-processing-blocks/tracking/gps_l1_ca_dll_pll_tracking_test.cc
View File

@ -50,7 +50,8 @@
#include "tracking_interface.h"
#include "in_memory_configuration.h"
#include "gnss_synchro.h"
#include "gps_l1_ca_dll_pll_tracking.h"
//#include "gps_l1_ca_dll_pll_tracking.h"
#include "gps_l1_ca_dll_pll_c_aid_tracking.h"
#include "tracking_true_obs_reader.h"
#include "tracking_dump_reader.h"
#include "signal_generator_flags.h"
@ -353,8 +354,8 @@ TEST_F(GpsL1CADllPllTrackingTest, ValidationOfResults)
}) << "Failure opening true observables file" << std::endl;
top_block = gr::make_top_block("Tracking test");
std::shared_ptr<TrackingInterface> tracking = std::make_shared<GpsL1CaDllPllTracking>(config.get(), "Tracking_1C", 1, 1);
//std::shared_ptr<TrackingInterface> tracking = std::make_shared<GpsL1CaDllPllCAidTracking>(config.get(), "Tracking_1C", 1, 1);
//std::shared_ptr<TrackingInterface> tracking = std::make_shared<GpsL1CaDllPllTracking>(config.get(), "Tracking_1C", 1, 1);
std::shared_ptr<TrackingInterface> tracking = std::make_shared<GpsL1CaDllPllCAidTracking>(config.get(), "Tracking_1C", 1, 1);
boost::shared_ptr<GpsL1CADllPllTrackingTest_msg_rx> msg_rx = GpsL1CADllPllTrackingTest_msg_rx_make();
@ -400,6 +401,7 @@ TEST_F(GpsL1CADllPllTrackingTest, ValidationOfResults)
tracking->start_tracking();
EXPECT_NO_THROW( {
gettimeofday(&tv, NULL);
begin = tv.tv_sec * 1000000 + tv.tv_usec;
@ -413,28 +415,37 @@ TEST_F(GpsL1CADllPllTrackingTest, ValidationOfResults)
long int nepoch = true_obs_data.num_epochs();
std::cout << "True observation epochs=" << nepoch << std::endl;
arma::vec true_timestamp_s = arma::zeros(nepoch, 1);
arma::vec true_acc_carrier_phase_cycles = arma::zeros(nepoch, 1);
arma::vec true_Doppler_Hz = arma::zeros(nepoch, 1);
arma::vec true_prn_delay_chips = arma::zeros(nepoch, 1);
arma::vec true_tow_s = arma::zeros(nepoch, 1);
long int epoch_counter = 0;
while(true_obs_data.read_binary_obs())
{
true_timestamp_s(epoch_counter) = true_obs_data.signal_timestamp_s;
true_acc_carrier_phase_cycles(epoch_counter) = true_obs_data.acc_carrier_phase_cycles;
true_Doppler_Hz(epoch_counter) = true_obs_data.doppler_l1_hz;
true_prn_delay_chips(epoch_counter) = true_obs_data.prn_delay_chips;
true_tow_s(epoch_counter) = true_obs_data.tow;
epoch_counter++;
}
//load the measured values
tracking_dump_reader trk_dump;
ASSERT_NO_THROW({
if (trk_dump.open_obs_file(std::string("./tracking_ch_0.dat")) == false)
{
throw std::exception();
};
}) << "Failure opening tracking dump file" << std::endl;
@ -442,11 +453,12 @@ TEST_F(GpsL1CADllPllTrackingTest, ValidationOfResults)
nepoch = trk_dump.num_epochs();
std::cout << "Measured observation epochs=" << nepoch << std::endl;
arma::vec trk_timestamp_s = arma::zeros(nepoch, 1);
arma::vec trk_acc_carrier_phase_cycles = arma::zeros(nepoch, 1);
arma::vec trk_Doppler_Hz = arma::zeros(nepoch, 1);
arma::vec trk_prn_delay_chips = arma::zeros(nepoch, 1);
epoch_counter = 0;
while(trk_dump.read_binary_obs())
{

143
src/tests/unit-tests/signal-processing-blocks/tracking/gps_l1_ca_dll_pll_tracking_test_fpga.cc
View File

@ -2,6 +2,7 @@
* \file gps_l1_ca_dll_pll_tracking_test.cc
* \brief This class implements a tracking test for Galileo_E5a_DLL_PLL_Tracking
* implementation based on some input parameters.
* \author Marc Majoral, 2017. mmajoral(at)cttc.cat
* \author Javier Arribas, 2017. jarribas(at)cttc.es
*
*
@ -35,6 +36,9 @@
#include <iostream>
#include <unistd.h>
#include <armadillo>
#include <boost/thread.hpp> // to test the FPGA we have to create a simultaneous task to send the samples using the DMA and stop the test
#include <boost/chrono.hpp> // temporary for debugging
#include <stdio.h> // FPGA read input file
#include <gnuradio/top_block.h>
#include <gnuradio/blocks/file_source.h>
#include <gnuradio/analog/sig_source_waveform.h>
@ -52,7 +56,6 @@
#include "tracking_interface.h"
#include "in_memory_configuration.h"
#include "gnss_synchro.h"
//#include "gps_l1_ca_dll_pll_tracking_fpga.h"
#include "gps_l1_ca_dll_pll_c_aid_tracking_fpga.h"
#include "tracking_true_obs_reader.h"
#include "tracking_dump_reader.h"
@ -60,6 +63,109 @@
#include "interleaved_byte_to_complex_short.h"
#define MAX_NUM_TEST_CASES 20
#define MAX_INPUT_SAMPLES_PER_TEST_CASE (8184)
#define MAX_INPUT_SAMPLES_TOTAL MAX_INPUT_SAMPLES_PER_TEST_CASE*MAX_NUM_TEST_CASES
#define DMA_TRANSFER_SIZE 2046
#define MIN_SAMPLES_REMAINING 20000 // number of remaining samples in the DMA that causes the CPU to stop the flowgraph (it has to be a bit alrger than 2x max packet size)
void wait(int seconds)
{
boost::this_thread::sleep_for(boost::chrono::seconds{seconds});
}
void send_tracking_gps_input_samples(FILE *ptr_myfile, int num_remaining_samples, gr::top_block_sptr top_block)
{
int sample_pointer;
int num_samples_transferred = 0;
static int flowgraph_stopped = 0;
char *buffer;
// DMA descriptor
int tx_fd;
tx_fd = open("/dev/loop_tx", O_WRONLY);
if ( tx_fd < 0 )
{
printf("can't open loop device\n");
exit(1);
}
buffer=(char *)malloc(DMA_TRANSFER_SIZE);
if (!buffer)
{
fprintf(stderr, "Memory error!");
}
while(num_remaining_samples >0)
{
if (num_remaining_samples < MIN_SAMPLES_REMAINING)
{
if (flowgraph_stopped == 0)
{
// stop top module
top_block->stop();
flowgraph_stopped = 1;
}
}
if (num_remaining_samples > DMA_TRANSFER_SIZE)
{
fread(buffer, DMA_TRANSFER_SIZE, 1, ptr_myfile);
assert( DMA_TRANSFER_SIZE == write(tx_fd, &buffer[0], DMA_TRANSFER_SIZE) );
num_remaining_samples = num_remaining_samples - DMA_TRANSFER_SIZE;
num_samples_transferred = num_samples_transferred + DMA_TRANSFER_SIZE;
}
else
{
fread(buffer, num_remaining_samples, 1, ptr_myfile);
assert( num_remaining_samples == write(tx_fd, &buffer[0], num_remaining_samples) );
num_samples_transferred = num_samples_transferred + num_remaining_samples;
num_remaining_samples = 0;
}
}
free(buffer);
close(tx_fd);
}
// thread that sends the samples to the FPGA
void thread(gr::top_block_sptr top_block, const char * file_name)
{
// file descriptor
FILE *ptr_myfile;
int fileLen;
ptr_myfile=fopen(file_name,"rb");
if (!ptr_myfile)
{
printf("Unable to open file!");
}
fseek(ptr_myfile, 0, SEEK_END);
fileLen=ftell(ptr_myfile);
fseek(ptr_myfile, 0, SEEK_SET);
wait(20); // wait for some time to give time to the other thread to program the device
//send_tracking_gps_input_samples(tx_fd, ptr_myfile, fileLen);
send_tracking_gps_input_samples(ptr_myfile, fileLen, top_block);
fclose(ptr_myfile);
}
// ######## GNURADIO BLOCK MESSAGE RECEVER #########
class GpsL1CADllPllTrackingTestFpga_msg_rx;
@ -330,11 +436,11 @@ void GpsL1CADllPllTrackingTestFpga::check_results_codephase(arma::vec true_time_
TEST_F(GpsL1CADllPllTrackingTestFpga, ValidationOfResultsFpga)
{
// Configure the signal generator
configure_generator();
// Generate signal raw signal samples and observations RINEX file
generate_signal();
// DO not generate signal raw signal samples and observations RINEX file by default
//generate_signal();
struct timeval tv;
long long int begin = 0;
@ -357,7 +463,6 @@ TEST_F(GpsL1CADllPllTrackingTestFpga, ValidationOfResultsFpga)
}) << "Failure opening true observables file" << std::endl;
top_block = gr::make_top_block("Tracking test");
//std::shared_ptr<TrackingInterface> tracking = std::make_shared<GpsL1CaDllPllTracking>(config.get(), "Tracking_1C", 1, 1);
std::shared_ptr<TrackingInterface> tracking = std::make_shared<GpsL1CaDllPllCAidTrackingFpga>(config.get(), "Tracking_1C", 1, 1);
boost::shared_ptr<GpsL1CADllPllTrackingTestFpga_msg_rx> msg_rx = GpsL1CADllPllTrackingTestFpga_msg_rx_make();
@ -373,45 +478,61 @@ TEST_F(GpsL1CADllPllTrackingTestFpga, ValidationOfResultsFpga)
//restart the epoch counter
true_obs_data.restart();
std::cout << "Initial Doppler [Hz]=" << true_obs_data.doppler_l1_hz << " Initial code delay [Chips]=" << true_obs_data.prn_delay_chips << std::endl;
gnss_synchro.Acq_delay_samples = (GPS_L1_CA_CODE_LENGTH_CHIPS - true_obs_data.prn_delay_chips / GPS_L1_CA_CODE_LENGTH_CHIPS) * baseband_sampling_freq * GPS_L1_CA_CODE_PERIOD;
gnss_synchro.Acq_doppler_hz = true_obs_data.doppler_l1_hz;
gnss_synchro.Acq_samplestamp_samples = 0;
ASSERT_NO_THROW( {
tracking->set_channel(gnss_synchro.Channel_ID);
}) << "Failure setting channel." << std::endl;
ASSERT_NO_THROW( {
tracking->set_gnss_synchro(&gnss_synchro);
}) << "Failure setting gnss_synchro." << std::endl;
ASSERT_NO_THROW( {
tracking->connect(top_block);
}) << "Failure connecting tracking to the top_block." << std::endl;
ASSERT_NO_THROW( {
std::string file = "./" + filename_raw_data;
const char * file_name = file.c_str();
gr::blocks::file_source::sptr file_source = gr::blocks::file_source::make(sizeof(int8_t), file_name, false);
interleaved_byte_to_complex_short_sptr char_to_cshort = make_interleaved_byte_to_complex_short();
gr::blocks::null_sink::sptr sink = gr::blocks::null_sink::make(sizeof(Gnss_Synchro));
top_block->connect(file_source, 0, char_to_cshort, 0);
top_block->connect(char_to_cshort, 0, tracking->get_left_block(), 0);
top_block->connect(tracking->get_right_block(), 0, sink, 0);
top_block->msg_connect(tracking->get_right_block(), pmt::mp("events"), msg_rx, pmt::mp("events"));
}) << "Failure connecting the blocks of tracking test." << std::endl;
tracking->start_tracking();
// assemble again the file name in a null terminated string (not available by default in the main program flow)
std::string file = "./" + filename_raw_data;
const char * file_name = file.c_str();
// start thread that sends the DMA samples to the FPGA
boost::thread t{thread, top_block, file_name};
EXPECT_NO_THROW( {
gettimeofday(&tv, NULL);
begin = tv.tv_sec * 1000000 + tv.tv_usec;
top_block->run(); // Start threads and wait
tracking.reset();
gettimeofday(&tv, NULL);
end = tv.tv_sec * 1000000 + tv.tv_usec;
}) << "Failure running the top_block." << std::endl;
// wait until child thread terminates
t.join();
//check results
//load the true values
long int nepoch = true_obs_data.num_epochs();