From c241b7b1d6d9be17dd969ca8190a6f66b80eb8b6 Mon Sep 17 00:00:00 2001 From: David Pubill Date: Fri, 19 Oct 2012 13:38:25 +0000 Subject: [PATCH] - Added TCP connector for Galileo E1 simulink tracking - Added simulink-based Galileo_E1_DLL_PLL_VEML_Tracking git-svn-id: https://svn.code.sf.net/p/gnss-sdr/code/trunk@250 64b25241-fba3-4117-9849-534c7e92360d --- ...sdr_galileo_e1_tcp_connector_tracking.conf | 273 + conf/gnss-sdr_tcp_connector_tracking.conf | 4 +- .../galileo_e1_tcp_connector_tracking.cc | 174 + .../galileo_e1_tcp_connector_tracking.h | 116 + .../gps_l1_ca_tcp_connector_tracking.cc | 1 + src/algorithms/tracking/adapters/jamfile.jam | 1 + .../galileo_e1_tcp_connector_tracking_cc.cc | 637 + .../galileo_e1_tcp_connector_tracking_cc.h | 215 + .../gps_l1_ca_tcp_connector_tracking_cc.cc | 20 +- .../tracking/gnuradio_blocks/jamfile.jam | 1 + src/algorithms/tracking/libs/jamfile.jam | 1 + .../tracking/libs/tcp_communication.cc | 37 +- .../tracking/libs/tcp_communication.h | 6 +- .../tracking/libs/tcp_packet_data.cc | 42 + src/core/receiver/gnss_block_factory.cc | 14 +- src/main/jamfile.jam | 3 + src/tests/jamfile.jam | 3 + ..._sdr_galileo_e1_tcp_connector_tracking.txt | 136 + ..._galileo_e1_tcp_connector_tracking_lib.mdl | 62086 ++++++++++++++++ ..._galileo_e1_tcp_connector_tracking_start.m | 174 + 20 files changed, 63917 insertions(+), 27 deletions(-) create mode 100644 conf/gnss-sdr_galileo_e1_tcp_connector_tracking.conf create mode 100644 src/algorithms/tracking/adapters/galileo_e1_tcp_connector_tracking.cc create mode 100644 src/algorithms/tracking/adapters/galileo_e1_tcp_connector_tracking.h create mode 100644 src/algorithms/tracking/gnuradio_blocks/galileo_e1_tcp_connector_tracking_cc.cc create mode 100644 src/algorithms/tracking/gnuradio_blocks/galileo_e1_tcp_connector_tracking_cc.h create mode 100644 src/algorithms/tracking/libs/tcp_packet_data.cc create mode 100644 src/utils/simulink/Single Thread/README_gnss_sdr_galileo_e1_tcp_connector_tracking.txt create mode 100644 src/utils/simulink/Single Thread/gnss_sdr_galileo_e1_tcp_connector_tracking_lib.mdl create mode 100644 src/utils/simulink/Single Thread/gnss_sdr_galileo_e1_tcp_connector_tracking_start.m diff --git a/conf/gnss-sdr_galileo_e1_tcp_connector_tracking.conf b/conf/gnss-sdr_galileo_e1_tcp_connector_tracking.conf new file mode 100644 index 000000000..fb561e8d2 --- /dev/null +++ b/conf/gnss-sdr_galileo_e1_tcp_connector_tracking.conf @@ -0,0 +1,273 @@ + +[GNSS-SDR] + +;######### GLOBAL OPTIONS ################## +;internal_fs_hz: Internal signal sampling frequency after the signal conditioning stage [Hz]. +GNSS-SDR.internal_fs_hz=4000000 + +;######### CONTROL_THREAD CONFIG ############ +ControlThread.wait_for_flowgraph=false + +;######### SIGNAL_SOURCE CONFIG ############ +;#implementation: Use File_Signal_Source or UHD_Signal_Source or GN3S_Signal_Source (experimental) +SignalSource.implementation=File_Signal_Source + +;#filename: path to file with the captured GNSS signal samples to be processed +SignalSource.filename=/home/engunit/workspace/cap2/cp_cttc_1_galileo_4Msps.dat + +;#item_type: Type and resolution for each of the signal samples. Use only gr_complex in this version. +SignalSource.item_type=gr_complex + +;#sampling_frequency: Original Signal sampling frequency in [Hz] +SignalSource.sampling_frequency=4000000 + +;#freq: RF front-end center frequency in [Hz] +SignalSource.freq=1575420000 + +;#gain: Front-end Gain in [dB] +SignalSource.gain=50 + +;#subdevice: UHD subdevice specification (for USRP1 use A:0 or B:0) +SignalSource.subdevice=B:0 + +;#samples: Number of samples to be processed. Notice that 0 indicates the entire file. +SignalSource.samples=0 + +;#repeat: Repeat the processing file. Disable this option in this version +SignalSource.repeat=false + +;#dump: Dump the Signal source data to a file. Disable this option in this version +SignalSource.dump=false + +SignalSource.dump_filename=../data/signal_source.dat + +;#enable_throttle_control: Enabling this option tells the signal source to keep the delay between samples in post processing. +; it helps to not overload the CPU, but the processing time will be longer. +SignalSource.enable_throttle_control=false + + +;######### SIGNAL_CONDITIONER CONFIG ############ +;## It holds blocks to change data type, filter and resample input data. +;#implementation: Pass_Through disables this block +SignalConditioner.implementation=Pass_Through + +;######### DATA_TYPE_ADAPTER CONFIG ############ +;## Changes the type of input data. Please disable it in this version. +;#implementation: Pass_Through disables this block +DataTypeAdapter.implementation=Pass_Through + +;######### INPUT_FILTER CONFIG ############ +;## Filter the input data. Can be combined with frequency translation for IF signals + +;#implementation: Pass_Through disables this block +;InputFilter.implementation=Fir_Filter +InputFilter.implementation=Pass_Through + +;#dump: Dump the filtered data to a file. +InputFilter.dump=false + +;#dump_filename: Log path and filename. +InputFilter.dump_filename=../data/input_filter.dat + +;#The following options are used in the filter design of Fir_Filter implementation. +;#These options are based on parameters of gnuradio's function: gr_remez. +;#These function calculates the optimal (in the Chebyshev/minimax sense) FIR filter inpulse reponse given a set of band edges, the desired reponse on those bands, and the weight given to the error in those bands. + +;#input_item_type: Type and resolution for input signal samples. Use only gr_complex in this version. +InputFilter.input_item_type=gr_complex + +;#outut_item_type: Type and resolution for output filtered signal samples. Use only gr_complex in this version. +InputFilter.output_item_type=gr_complex + +;#taps_item_type: Type and resolution for the taps of the filter. Use only float in this version. +InputFilter.taps_item_type=float + +;#number_of_taps: Number of taps in the filter. Increasing this parameter increases the processing time +InputFilter.number_of_taps=5 + +;#number_of _bands: Number of frequency bands in the filter. +InputFilter.number_of_bands=2 + +;#bands: frequency at the band edges [ b1 e1 b2 e2 b3 e3 ...]. +;#Frequency is in the range [0, 1], with 1 being the Nyquist frequency (Fs/2) +;#The number of band_begin and band_end elements must match the number of bands + +InputFilter.band1_begin=0.0 +InputFilter.band1_end=0.45 +InputFilter.band2_begin=0.55 +InputFilter.band2_end=1.0 + +;#ampl: desired amplitude at the band edges [ a(b1) a(e1) a(b2) a(e2) ...]. +;#The number of ampl_begin and ampl_end elements must match the number of bands + +InputFilter.ampl1_begin=1.0 +InputFilter.ampl1_end=1.0 +InputFilter.ampl2_begin=0.0 +InputFilter.ampl2_end=0.0 + +;#band_error: weighting applied to each band (usually 1). +;#The number of band_error elements must match the number of bands +InputFilter.band1_error=1.0 +InputFilter.band2_error=1.0 + +;#filter_type: one of "bandpass", "hilbert" or "differentiator" +InputFilter.filter_type=bandpass + +;#grid_density: determines how accurately the filter will be constructed. +;The minimum value is 16; higher values are slower to compute the filter. +InputFilter.grid_density=16 + +;######### RESAMPLER CONFIG ############ +;## Resamples the input data. + +;#implementation: Pass_Through disables this block +Resampler.implementation=Pass_Through + +;#dump: Dump the filtered data to a file. +InputFilter.dump=false +;#dump_filename: Log path and filename. +InputFilter.dump=../data/resampler.dat + +;#item_type: Type and resolution for each of the signal samples. Use only gr_complex in this version. +Resampler.item_type=gr_complex + +;#sample_freq_in: the sample frequency of the input signal +Resampler.sample_freq_in=4000000 + +;#sample_freq_out: the desired sample frequency of the output signal +Resampler.sample_freq_out=4000000 + + +;######### CHANNELS GLOBAL CONFIG ############ +;#count: Number of available satellite channels. +Channels.count=1 +Channels.in_acquisition=1 + +;######### CHANNEL 0 CONFIG ############ +Channel0.system=Galileo +Channel0.signal=1B +Channel0.satellite=12 +Channel0.repeat_satellite=true + +;######### CHANNEL 1 CONFIG ############ + +Channel1.system=Galileo +Channel1.signal=1B +Channel1.satellite=11 +Channel1.repeat_satellite=true + +;######### ACQUISITION GLOBAL CONFIG ############ + +;#dump: Enable or disable the acquisition internal data file logging [true] or [false] +Acquisition.dump=false +;#filename: Log path and filename +Acquisition.dump_filename=./acq_dump.dat +;#item_type: Type and resolution for each of the signal samples. Use only gr_complex in this version. +Acquisition.item_type=gr_complex +;#if: Signal intermediate frequency in [Hz] +Acquisition.if=0 +;#sampled_ms: Signal block duration for the acquisition signal detection [ms] +Acquisition.sampled_ms=4 + +;######### ACQUISITION CHANNELS CONFIG ###### + +;######### ACQUISITION CH 0 CONFIG ############ +;#implementation: Acquisition algorithm selection for this channel: [GPS_L1_CA_PCPS_Acquisition] or [Galileo_E1_PCPS_Ambiguous_Acquisition] +Acquisition0.implementation=Galileo_E1_PCPS_Ambiguous_Acquisition +;#threshold: Acquisition threshold +Acquisition0.threshold=50 +;#doppler_max: Maximum expected Doppler shift [Hz] +Acquisition0.doppler_max=10000 +;#doppler_max: Doppler step in the grid search [Hz] +Acquisition0.doppler_step=125 +;#cboc: Only for [Galileo_E1_PCPS_Ambiguous_Acquisition]. This option allows you to choose between acquiring with CBOC signal [true] or sinboc(1,1) signal [false] +Acquisition0.cboc=true + +;######### ACQUISITION CH 1 CONFIG ############ +Acquisition1.implementation=Galileo_E1_PCPS_Ambiguous_Acquisition +Acquisition1.threshold=50 +Acquisition1.doppler_max=10000 +Acquisition1.doppler_step=125 +Acquisition1.cboc=true + + +;######### TRACKING GLOBAL CONFIG ############ + +;#implementation: Selected tracking algorithm: [GPS_L1_CA_DLL_PLL_Tracking] or [GPS_L1_CA_DLL_FLL_PLL_Tracking] or [GPS_L1_CA_TCP_CONNECTOR_Tracking] or [Galileo_E1_DLL_PLL_VEML_Tracking] or [Galileo_E1_TCP_CONNECTOR_Tracking] +Tracking.implementation=Galileo_E1_TCP_CONNECTOR_Tracking +;#item_type: Type and resolution for each of the signal samples. Use only [gr_complex] in this version. +Tracking.item_type=gr_complex + +;#sampling_frequency: Signal Intermediate Frequency in [Hz] +Tracking.if=0 + +;#dump: Enable or disable the Tracking internal binary data file logging [true] or [false] +Tracking.dump=false + +;#dump_filename: Log path and filename. Notice that the tracking channel will add "x.dat" where x is the channel number. +Tracking.dump_filename=../data/veml_tracking_ch_ + +;#pll_bw_hz: PLL loop filter bandwidth [Hz] +Tracking.pll_bw_hz=30.0; + +;#dll_bw_hz: DLL loop filter bandwidth [Hz] +Tracking.dll_bw_hz=2.0; + +;#fll_bw_hz: FLL loop filter bandwidth [Hz] +Tracking.fll_bw_hz=10.0; + +;#order: PLL/DLL loop filter order [2] or [3] +Tracking.order=3; + +;#early_late_space_chips: correlator early-late space [chips]. Use [0.5] for GPS and [0.15] for Galileo +Tracking.early_late_space_chips=0.15; + +;#very_early_late_space_chips: only for [Galileo_E1_DLL_PLL_VEML_Tracking], correlator very early-late space [chips]. Use [0.6] +Tracking.very_early_late_space_chips=0.6; + +;#port_ch0: local TCP port for channel 0 +Tracking.port_ch0=2070; + +;######### TELEMETRY DECODER CONFIG ############ +;#implementation: Use [GPS_L1_CA_Telemetry_Decoder] for GPS L1 C/A. +TelemetryDecoder.implementation=GPS_L1_CA_Telemetry_Decoder +TelemetryDecoder.dump=false + +;######### OBSERVABLES CONFIG ############ +;#implementation: Use [GPS_L1_CA_Observables] for GPS L1 C/A. +Observables.implementation=GPS_L1_CA_Observables + +;#dump: Enable or disable the Observables internal binary data file logging [true] or [false] +Observables.dump=false + +;#dump_filename: Log path and filename. +Observables.dump_filename=./observables.dat + + +;######### PVT CONFIG ############ +;#implementation: Position Velocity and Time (PVT) implementation algorithm: Use [GPS_L1_CA_PVT] in this version. +PVT.implementation=GPS_L1_CA_PVT + +;#averaging_depth: Number of PVT observations in the moving average algorithm +PVT.averaging_depth=100 + +;#flag_average: Enables the PVT averaging between output intervals (arithmetic mean) [true] or [false] +PVT.flag_averaging=true + +;#output_rate_ms: Period between two PVT outputs. Notice that the minimum period is equal to the tracking integration time (for GPS CA L1 is 1ms) [ms] +PVT.output_rate_ms=100; + +;#display_rate_ms: Position console print (std::out) interval [ms]. Notice that output_rate_ms<=display_rate_ms. +PVT.display_rate_ms=500; + +;#dump: Enable or disable the PVT internal binary data file logging [true] or [false] +PVT.dump=false + +;#dump_filename: Log path and filename without extension. Notice that PVT will add ".dat" to the binary dump and ".kml" to GoogleEarth dump. +PVT.dump_filename=./PVT + +;######### OUTPUT_FILTER CONFIG ############ +;# Receiver output filter: Leave this block disabled in this version +OutputFilter.implementation=Null_Sink_Output_Filter +OutputFilter.filename=data/gnss-sdr.dat +OutputFilter.item_type=gr_complex \ No newline at end of file diff --git a/conf/gnss-sdr_tcp_connector_tracking.conf b/conf/gnss-sdr_tcp_connector_tracking.conf index e6eb9f787..318d7a457 100644 --- a/conf/gnss-sdr_tcp_connector_tracking.conf +++ b/conf/gnss-sdr_tcp_connector_tracking.conf @@ -144,8 +144,8 @@ Resampler.sample_freq_out=4000000 ;######### CHANNELS GLOBAL CONFIG ############ ;#count: Number of available satellite channels. -Channels.count=7 -Channels.in_acquisition=7 +Channels.count=4 +Channels.in_acquisition=4 ;######### CHANNEL 0 CONFIG ############ ;#system: GPS, GLONASS, GALILEO, SBAS or COMPASS diff --git a/src/algorithms/tracking/adapters/galileo_e1_tcp_connector_tracking.cc b/src/algorithms/tracking/adapters/galileo_e1_tcp_connector_tracking.cc new file mode 100644 index 000000000..18d63c5f7 --- /dev/null +++ b/src/algorithms/tracking/adapters/galileo_e1_tcp_connector_tracking.cc @@ -0,0 +1,174 @@ +/*! + * \file gps_l1_ca_tcp_connector_tracking.cc + * \brief Implementation of an adapter of a TCP connector block based on code DLL + carrier PLL + * \author David Pubill, 2012. dpubill(at)cttc.es + * Luis Esteve, 2012. luis(at)epsilon-formacion.com + * Javier Arribas, 2011. jarribas(at)cttc.es + * + * Code DLL + carrier PLL according to the algorithms described in: + * K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen, + * A Software-Defined GPS and Galileo Receiver. A Single-Frequency + * Approach, Birkhauser, 2007 + * + * ------------------------------------------------------------------------- + * + * Copyright (C) 2010-2012 (see AUTHORS file for a list of contributors) + * + * GNSS-SDR is a software defined Global Navigation + * Satellite Systems receiver + * + * This file is part of GNSS-SDR. + * + * GNSS-SDR is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * at your option) any later version. + * + * GNSS-SDR is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNSS-SDR. If not, see . + * + * ------------------------------------------------------------------------- + */ + +#include "galileo_e1_tcp_connector_tracking.h" +#include "GPS_L1_CA.h" +#include "Galileo_E1.h" +#include "configuration_interface.h" +#ifdef GNSS_SDR_USE_BOOST_ROUND + #include +#endif +#include +#include +#include + +using google::LogMessage; + +GalileoE1TcpConnectorTracking::GalileoE1TcpConnectorTracking( + ConfigurationInterface* configuration, std::string role, + unsigned int in_streams, unsigned int out_streams, + gr_msg_queue_sptr queue) : + role_(role), in_streams_(in_streams), out_streams_(out_streams), + queue_(queue) +{ + + DLOG(INFO) << "role " << role; + //DLOG(INFO) << "vector length " << vector_length; + + //################# CONFIGURATION PARAMETERS ######################## + + int fs_in; + int vector_length; + int f_if; + bool dump; + std::string dump_filename; + std::string item_type; + std::string default_item_type = "gr_complex"; + float pll_bw_hz; + float dll_bw_hz; + float early_late_space_chips; + float very_early_late_space_chips; + size_t port_ch0; + + item_type = configuration->property(role + ".item_type",default_item_type); + fs_in = configuration->property("GNSS-SDR.internal_fs_hz", 2048000); + f_if = configuration->property(role + ".if", 0); + dump = configuration->property(role + ".dump", false); + pll_bw_hz = configuration->property(role + ".pll_bw_hz", 50.0); + dll_bw_hz = configuration->property(role + ".dll_bw_hz", 2.0); + early_late_space_chips = configuration->property(role + ".early_late_space_chips", 0.15); + very_early_late_space_chips = configuration->property(role + ".very_early_late_space_chips", 0.6); + port_ch0 = configuration->property(role + ".port_ch0", 2060); + + std::string default_dump_filename = "./track_ch"; + dump_filename = configuration->property(role + ".dump_filename", + default_dump_filename); //unused! +#ifdef GNSS_SDR_USE_BOOST_ROUND + vector_length = round(fs_in / (Galileo_E1_CODE_CHIP_RATE_HZ / Galileo_E1_B_CODE_LENGTH_CHIPS)); +#else + vector_length = std::round(fs_in / (Galileo_E1_CODE_CHIP_RATE_HZ / Galileo_E1_B_CODE_LENGTH_CHIPS)); +#endif + //################# MAKE TRACKING GNURadio object ################### + if (item_type.compare("gr_complex") == 0) + { + item_size_ = sizeof(gr_complex); + tracking_ = galileo_e1_tcp_connector_make_tracking_cc( + f_if, + fs_in, + vector_length, + queue_, + dump, + dump_filename, + pll_bw_hz, + dll_bw_hz, + early_late_space_chips, + very_early_late_space_chips, + port_ch0); + } + else + { + LOG_AT_LEVEL(WARNING) << item_type << " unknown tracking item type."; + } + + DLOG(INFO) << "tracking(" << tracking_->unique_id() << ")"; +} + +GalileoE1TcpConnectorTracking::~GalileoE1TcpConnectorTracking() +{ +} + +void GalileoE1TcpConnectorTracking::start_tracking() +{ + tracking_->start_tracking(); +} + +/* + * Set tracking channel unique ID + */ +void GalileoE1TcpConnectorTracking::set_channel(unsigned int channel) +{ + channel_ = channel; + tracking_->set_channel(channel); +} + +/* + * Set tracking channel internal queue + */ +void GalileoE1TcpConnectorTracking::set_channel_queue( + concurrent_queue *channel_internal_queue) +{ + channel_internal_queue_ = channel_internal_queue; + + tracking_->set_channel_queue(channel_internal_queue_); + +} + +void GalileoE1TcpConnectorTracking::set_gnss_synchro(Gnss_Synchro* p_gnss_synchro) +{ + tracking_->set_gnss_synchro(p_gnss_synchro); +} + +void GalileoE1TcpConnectorTracking::connect(gr_top_block_sptr top_block) +{ + //nothing to connect, now the tracking uses gr_sync_decimator +} + +void GalileoE1TcpConnectorTracking::disconnect(gr_top_block_sptr top_block) +{ + //nothing to disconnect, now the tracking uses gr_sync_decimator +} + +gr_basic_block_sptr GalileoE1TcpConnectorTracking::get_left_block() +{ + return tracking_; +} + +gr_basic_block_sptr GalileoE1TcpConnectorTracking::get_right_block() +{ + return tracking_; +} + diff --git a/src/algorithms/tracking/adapters/galileo_e1_tcp_connector_tracking.h b/src/algorithms/tracking/adapters/galileo_e1_tcp_connector_tracking.h new file mode 100644 index 000000000..121815329 --- /dev/null +++ b/src/algorithms/tracking/adapters/galileo_e1_tcp_connector_tracking.h @@ -0,0 +1,116 @@ +/*! + * \file gps_l1_ca_tcp_connector_tracking.h + * \brief Interface of an adapter of a TCP connector block based on code DLL + carrier PLL + * for GPS L1 C/A to a TrackingInterface + * \author David Pubill, 2012. dpubill(at)cttc.es + * Luis Esteve, 2012. luis(at)epsilon-formacion.com + * Javier Arribas, 2011. jarribas(at)cttc.es + * + * Code DLL + carrier PLL according to the algorithms described in: + * K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen, + * A Software-Defined GPS and Galileo Receiver. A Single-Frequency + * Approach, Birkha user, 2007 + * + * ------------------------------------------------------------------------- + * + * Copyright (C) 2012 (see AUTHORS file for a list of contributors) + * + * GNSS-SDR is a software defined Global Navigation + * Satellite Systems receiver + * + * This file is part of GNSS-SDR. + * + * GNSS-SDR is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * at your option) any later version. + * + * GNSS-SDR is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNSS-SDR. If not, see . + * + * ------------------------------------------------------------------------- + */ + +#ifndef GNSS_SDR_GALILEO_E1_TCP_CONNECTOR_TRACKING_H_ +#define GNSS_SDR_GALILEO_E1_TCP_CONNECTOR_TRACKING_H_ + +#include "tracking_interface.h" +#include "galileo_e1_tcp_connector_tracking_cc.h" +#include + +class ConfigurationInterface; + +/*! + * \brief This class implements a code DLL + carrier PLL tracking loop + */ +class GalileoE1TcpConnectorTracking : public TrackingInterface +{ + +public: + + GalileoE1TcpConnectorTracking(ConfigurationInterface* configuration, + std::string role, + unsigned int in_streams, + unsigned int out_streams, + gr_msg_queue_sptr queue); + + virtual ~GalileoE1TcpConnectorTracking(); + + std::string role() + { + return role_; + } + std::string implementation() + { + return "Galileo_E1_TCP_CONNECTOR_Tracking"; + } + size_t item_size() + { + return item_size_; + } + + void connect(gr_top_block_sptr top_block); + void disconnect(gr_top_block_sptr top_block); + gr_basic_block_sptr get_left_block(); + gr_basic_block_sptr get_right_block(); + + + /*! + * \brief Set tracking channel unique ID + */ + void set_channel(unsigned int channel); + + /*! + * \brief Set acquisition/tracking common Gnss_Synchro object pointer + * to efficiently exchange synchronization data between acquisition and + * tracking blocks + */ + void set_gnss_synchro(Gnss_Synchro* p_gnss_synchro); + + /*! + * \brief Set tracking channel internal queue + */ + void set_channel_queue(concurrent_queue *channel_internal_queue); + + void start_tracking(); + +private: + + galileo_e1_tcp_connector_tracking_cc_sptr tracking_; + size_t item_size_; + + unsigned int channel_; + + std::string role_; + unsigned int in_streams_; + unsigned int out_streams_; + gr_msg_queue_sptr queue_; + concurrent_queue *channel_internal_queue_; +}; + +#endif // GNSS_SDR_GALILEO_E1_TCP_CONNECTOR_TRACKING_H_ diff --git a/src/algorithms/tracking/adapters/gps_l1_ca_tcp_connector_tracking.cc b/src/algorithms/tracking/adapters/gps_l1_ca_tcp_connector_tracking.cc index 572bf4c36..f082ddeae 100644 --- a/src/algorithms/tracking/adapters/gps_l1_ca_tcp_connector_tracking.cc +++ b/src/algorithms/tracking/adapters/gps_l1_ca_tcp_connector_tracking.cc @@ -2,6 +2,7 @@ * \file gps_l1_ca_tcp_connector_tracking.cc * \brief Implementation of an adapter of a TCP connector block based on code DLL + carrier PLL * \author David Pubill, 2012. dpubill(at)cttc.es + * Luis Esteve, 2012. luis(at)epsilon-formacion.com * Javier Arribas, 2011. jarribas(at)cttc.es * * Code DLL + carrier PLL according to the algorithms described in: diff --git a/src/algorithms/tracking/adapters/jamfile.jam b/src/algorithms/tracking/adapters/jamfile.jam index 5393be324..3577193da 100644 --- a/src/algorithms/tracking/adapters/jamfile.jam +++ b/src/algorithms/tracking/adapters/jamfile.jam @@ -4,4 +4,5 @@ obj gps_l1_ca_dll_pll_tracking : gps_l1_ca_dll_pll_tracking.cc : darwin obj gps_l1_ca_dll_fll_pll_tracking : gps_l1_ca_dll_fll_pll_tracking.cc : darwin:GNSS_SDR_USE_BOOST_ROUND ; obj gps_l1_ca_tcp_connector_tracking : gps_l1_ca_tcp_connector_tracking.cc : darwin:GNSS_SDR_USE_BOOST_ROUND ; obj galileo_e1_dll_pll_veml_tracking : galileo_e1_dll_pll_veml_tracking.cc : darwin:GNSS_SDR_USE_BOOST_ROUND ; +obj galileo_e1_tcp_connector_tracking : galileo_e1_tcp_connector_tracking.cc : darwin:GNSS_SDR_USE_BOOST_ROUND ; obj gps_l1_ca_dll_pll_optim_tracking : gps_l1_ca_dll_pll_optim_tracking.cc : darwin:GNSS_SDR_USE_BOOST_ROUND ; \ No newline at end of file diff --git a/src/algorithms/tracking/gnuradio_blocks/galileo_e1_tcp_connector_tracking_cc.cc b/src/algorithms/tracking/gnuradio_blocks/galileo_e1_tcp_connector_tracking_cc.cc new file mode 100644 index 000000000..4f4a93542 --- /dev/null +++ b/src/algorithms/tracking/gnuradio_blocks/galileo_e1_tcp_connector_tracking_cc.cc @@ -0,0 +1,637 @@ +/*! + * \file galileo_e1_tcp_connector_tracking_cc.cc + * \brief Implementation of a TCP connector block based on Code DLL + carrier PLL + * \author David Pubill, 2012. dpubill(at)cttc.es + * Luis Esteve, 2012. luis(at)epsilon-formacion.com + * Javier Arribas, 2011. jarribas(at)cttc.es + * + * + * Code DLL + carrier PLL according to the algorithms described in: + * [1] K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen, + * A Software-Defined GPS and Galileo Receiver. A Single-Frequency + * Approach, Birkha user, 2007 + * + * ------------------------------------------------------------------------- + * + * Copyright (C) 2010-2012 (see AUTHORS file for a list of contributors) + * + * GNSS-SDR is a software defined Global Navigation + * Satellite Systems receiver + * + * This file is part of GNSS-SDR. + * + * GNSS-SDR is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * at your option) any later version. + * + * GNSS-SDR is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNSS-SDR. If not, see . + * + * ------------------------------------------------------------------------- + */ + +#include "gnss_synchro.h" +#include "galileo_e1_tcp_connector_tracking_cc.h" +#include "galileo_e1_signal_processing.h" +#include "tracking_discriminators.h" +#include "CN_estimators.h" +#include "GPS_L1_CA.h" +#include "Galileo_E1.h" +#include "control_message_factory.h" +#include "tcp_communication.h" +#include +#include +#include +#include +#include "math.h" +#include +#include +#include + +#include +#include "tcp_packet_data.h" + +/*! + * \todo Include in definition header file + */ +#define CN0_ESTIMATION_SAMPLES 10 +#define MINIMUM_VALID_CN0 25 +#define MAXIMUM_LOCK_FAIL_COUNTER 200 + +using google::LogMessage; + +galileo_e1_tcp_connector_tracking_cc_sptr +galileo_e1_tcp_connector_make_tracking_cc( + long if_freq, + long fs_in, + unsigned int vector_length, + gr_msg_queue_sptr queue, + bool dump, + std::string dump_filename, + float pll_bw_hz, + float dll_bw_hz, + float early_late_space_chips, + float very_early_late_space_chips, + size_t port_ch0) +{ + return galileo_e1_tcp_connector_tracking_cc_sptr(new Galileo_E1_Tcp_Connector_Tracking_cc(if_freq, + fs_in, vector_length, queue, dump, dump_filename, pll_bw_hz, dll_bw_hz, early_late_space_chips, very_early_late_space_chips, port_ch0)); +} + + + +void Galileo_E1_Tcp_Connector_Tracking_cc::forecast (int noutput_items, + gr_vector_int &ninput_items_required) +{ + ninput_items_required[0] = (int)d_vector_length*2; //set the required available samples in each call +} + + + +Galileo_E1_Tcp_Connector_Tracking_cc::Galileo_E1_Tcp_Connector_Tracking_cc( + long if_freq, + long fs_in, + unsigned int vector_length, + gr_msg_queue_sptr queue, + bool dump, + std::string dump_filename, + float pll_bw_hz, + float dll_bw_hz, + float early_late_space_chips, + float very_early_late_space_chips, + size_t port_ch0): + gr_block ("Galileo_E1_Tcp_Connector_Tracking_cc", gr_make_io_signature (1, 1, sizeof(gr_complex)), + gr_make_io_signature(1, 1, sizeof(Gnss_Synchro))) +{ + this->set_relative_rate(1.0/vector_length); + // initialize internal vars + d_queue = queue; + d_dump = dump; + d_if_freq = if_freq; + d_fs_in = fs_in; + d_vector_length = vector_length; + d_dump_filename = dump_filename; + d_code_loop_filter=Tracking_2nd_DLL_filter(0.004); + d_carrier_loop_filter=Tracking_2nd_PLL_filter(0.004); + + // Initialize tracking ========================================== + + d_code_loop_filter.set_DLL_BW(dll_bw_hz); + d_carrier_loop_filter.set_PLL_BW(pll_bw_hz); + + //--- DLL variables -------------------------------------------------------- + d_early_late_spc_chips = early_late_space_chips; // Define early-late offset (in chips) + d_very_early_late_spc_chips = very_early_late_space_chips; // Define very-early-late offset (in chips) + + //--- TCP CONNECTOR variables -------------------------------------------------------- + d_port_ch0 = port_ch0; + d_port = 0; + d_listen_connection = true; + d_control_id = 0; + + // Initialization of local code replica + // Get space for a vector with the sinboc(1,1) replica sampled 2x/chip +// int d_ca_code_size = (int)(2*Galileo_E1_B_CODE_LENGTH_CHIPS + 4); + d_ca_code = new gr_complex[(int)(2*Galileo_E1_B_CODE_LENGTH_CHIPS + 4)]; + +// std::cout << "d_ca_code_size = " << d_ca_code_size << std::endl; + + /* If an array is partitioned for more than one thread to operate on, + * having the sub-array boundaries unaligned to cache lines could lead + * to performance degradation. Here we allocate memory + * (gr_comlex array of size 2*d_vector_length) aligned to cache of 16 bytes + */ + // todo: do something if posix_memalign fails + // Get space for the resampled early / prompt / late local replicas + if (posix_memalign((void**)&d_very_early_code, 16, d_vector_length * sizeof(gr_complex) * 2) == 0){}; + if (posix_memalign((void**)&d_early_code, 16, d_vector_length * sizeof(gr_complex) * 2) == 0){}; + if (posix_memalign((void**)&d_prompt_code, 16, d_vector_length * sizeof(gr_complex) * 2) == 0){}; + if (posix_memalign((void**)&d_late_code, 16, d_vector_length * sizeof(gr_complex) * 2) == 0){}; + if (posix_memalign((void**)&d_very_late_code, 16, d_vector_length * sizeof(gr_complex) * 2) == 0){}; + // space for carrier wipeoff and signal baseband vectors + if (posix_memalign((void**)&d_carr_sign, 16, d_vector_length * sizeof(gr_complex) * 2) == 0){}; + // correlator outputs (scalar) + if (posix_memalign((void**)&d_Very_Early, 16, sizeof(gr_complex)) == 0){}; + if (posix_memalign((void**)&d_Early, 16, sizeof(gr_complex)) == 0){}; + if (posix_memalign((void**)&d_Prompt, 16, sizeof(gr_complex)) == 0){}; + if (posix_memalign((void**)&d_Late, 16, sizeof(gr_complex)) == 0){}; + if (posix_memalign((void**)&d_Very_Late, 16, sizeof(gr_complex)) == 0){}; + + + //--- Perform initializations ------------------------------ + // define initial code frequency basis of NCO + d_code_freq_hz = Galileo_E1_CODE_CHIP_RATE_HZ; + // define residual code phase (in chips) + d_rem_code_phase_samples = 0.0; + // define residual carrier phase + d_rem_carr_phase_rad = 0.0; + // define phase step + d_code_phase_step_chips = d_code_freq_hz / (float)d_fs_in; //[chips] + + // sample synchronization + d_sample_counter = 0; + //d_sample_counter_seconds = 0; + d_acq_sample_stamp = 0; + + d_enable_tracking = false; + d_pull_in = false; + d_last_seg = 0; + + d_current_prn_length_samples = (int)d_vector_length; + + // CN0 estimation and lock detector buffers + d_cn0_estimation_counter = 0; + d_Prompt_buffer = new gr_complex[CN0_ESTIMATION_SAMPLES]; + d_carrier_lock_test = 1; + d_CN0_SNV_dB_Hz = 0; + d_carrier_lock_fail_counter = 0; + d_carrier_lock_threshold = 20; + + systemName["G"] = std::string("GPS"); + systemName["R"] = std::string("GLONASS"); + systemName["S"] = std::string("SBAS"); + systemName["E"] = std::string("Galileo"); + systemName["C"] = std::string("Compass"); +} + +void Galileo_E1_Tcp_Connector_Tracking_cc::start_tracking() +{ + + d_acq_code_phase_samples = d_acquisition_gnss_synchro->Acq_delay_samples; + d_acq_carrier_doppler_hz = d_acquisition_gnss_synchro->Acq_doppler_hz; + d_acq_sample_stamp = d_acquisition_gnss_synchro->Acq_samplestamp_samples; + + // DLL/PLL filter initialization + d_carrier_loop_filter.initialize(d_acq_carrier_doppler_hz); //initialize the carrier filter + d_code_loop_filter.initialize(d_acq_code_phase_samples); //initialize the code filter + + + // generate local reference ALWAYS starting at chip 2 (2 samples per chip) + galileo_e1_code_gen_complex_sampled(&d_ca_code[2],d_acquisition_gnss_synchro->Signal, false, d_acquisition_gnss_synchro->PRN, 2*Galileo_E1_CODE_CHIP_RATE_HZ, 0); + + d_ca_code[0] = d_ca_code[(int)(2*Galileo_E1_B_CODE_LENGTH_CHIPS)]; + d_ca_code[1] = d_ca_code[(int)(2*Galileo_E1_B_CODE_LENGTH_CHIPS+1)]; + d_ca_code[(int)(2*Galileo_E1_B_CODE_LENGTH_CHIPS+2)] = d_ca_code[2]; + d_ca_code[(int)(2*Galileo_E1_B_CODE_LENGTH_CHIPS+3)] = d_ca_code[3]; + d_carrier_lock_fail_counter = 0; + d_rem_code_phase_samples = 0.0; + d_rem_carr_phase_rad = 0; + d_next_rem_code_phase_samples = 0; + d_acc_carrier_phase_rad = 0; + + d_code_phase_samples = d_acq_code_phase_samples; + d_carrier_doppler_hz = d_acq_carrier_doppler_hz; + + d_next_prn_length_samples = d_vector_length; + + std::string sys_ = &d_acquisition_gnss_synchro->System; + sys = sys_.substr(0,1); + + // DEBUG OUTPUT + std::cout << "Tracking start on channel " << d_channel << " for satellite " << Gnss_Satellite(systemName[sys], d_acquisition_gnss_synchro->PRN) << std::endl; + DLOG(INFO) << "Start tracking for satellite " << Gnss_Satellite(systemName[sys], d_acquisition_gnss_synchro->PRN) << " received" << std::endl; + + // enable tracking + d_pull_in = true; + d_enable_tracking = true; + + std::cout << "PULL-IN Doppler [Hz]=" << d_carrier_doppler_hz + << " PULL-IN Code Phase [samples]=" << d_acq_code_phase_samples << std::endl; +} + + +void Galileo_E1_Tcp_Connector_Tracking_cc::update_local_code() +{ + + double tcode_half_chips; + float rem_code_phase_half_chips; + int associated_chip_index; + int code_length_half_chips = (int)(2*Galileo_E1_B_CODE_LENGTH_CHIPS); + double code_phase_step_chips; + double code_phase_step_half_chips; + int early_late_spc_samples; + int very_early_late_spc_samples; + int epl_loop_length_samples; + + // unified loop for E, P, L code vectors + code_phase_step_chips = ((double)d_code_freq_hz) / ((double)d_fs_in); + code_phase_step_half_chips = (2.0*(double)d_code_freq_hz) / ((double)d_fs_in); + + rem_code_phase_half_chips = d_rem_code_phase_samples * (2*d_code_freq_hz / d_fs_in); + tcode_half_chips = -(double)rem_code_phase_half_chips; + + early_late_spc_samples=round(d_early_late_spc_chips/code_phase_step_chips); + very_early_late_spc_samples=round(d_very_early_late_spc_chips/code_phase_step_chips); + + epl_loop_length_samples=d_current_prn_length_samples+very_early_late_spc_samples*2; + + + for (int i=0; itelemetry_decoder + Gnss_Synchro current_synchro_data; + // Fill the acquisition data + current_synchro_data = *d_acquisition_gnss_synchro; + + const gr_complex* in = (gr_complex*) input_items[0]; //PRN start block alignement + Gnss_Synchro **out = (Gnss_Synchro **) &output_items[0]; + + // Update the prn length based on code freq (variable) and + // sampling frequency (fixed) + // variable code PRN sample block size + d_current_prn_length_samples = d_next_prn_length_samples; + + update_local_code(); + update_local_carrier(); + + // perform Early, Prompt and Late correlation + d_correlator.Carrier_wipeoff_and_VEPL_volk(d_current_prn_length_samples, + in, + d_carr_sign, + d_very_early_code, + d_early_code, + d_prompt_code, + d_late_code, + d_very_late_code, + d_Very_Early, + d_Early, + d_Prompt, + d_Late, + d_Very_Late, + is_unaligned()); + + + //! Variable used for control + d_control_id++; + + //! Send and receive a TCP packet + boost::array tx_variables_array = {{d_control_id,(*d_Very_Early).real(),(*d_Very_Early).imag(),(*d_Early).real(),(*d_Early).imag(),(*d_Late).real(),(*d_Late).imag(),(*d_Very_Late).real(),(*d_Very_Late).imag(),(*d_Prompt).real(),(*d_Prompt).imag(),d_acq_carrier_doppler_hz,1}}; + d_tcp_com.send_receive_tcp_packet_galileo_e1(tx_variables_array, &tcp_data); + + // PLL discriminator, carrier loop filter implementation and NCO command generation (TCP_connector) + carr_nco_hz = tcp_data.proc_pack_carr_error; + // Modify carrier freq based on NCO command (TCP_connector) + d_carrier_doppler_hz = tcp_data.proc_pack_carrier_doppler_hz; + + // DLL discriminator, carrier loop filter implementation and NCO command generation (TCP_connector) + code_nco_chips = tcp_data.proc_pack_code_error; + // Modify code freq based on NCO command + d_code_freq_hz = Galileo_E1_CODE_CHIP_RATE_HZ + (d_carrier_doppler_hz * Galileo_E1_CODE_CHIP_RATE_HZ) / Galileo_E1_FREQ_HZ - code_nco_chips; + // Update the phase step based on code freq (variable) and sampling frequency (fixed) + d_code_phase_step_chips = d_code_freq_hz / (float)d_fs_in; //[chips] + + // keep alignment parameters for the next input buffer + float T_chip_seconds; + float T_prn_seconds; + float T_prn_samples; + float K_blk_samples; + T_chip_seconds = 1 / d_code_freq_hz; + T_prn_seconds = T_chip_seconds * Galileo_E1_B_CODE_LENGTH_CHIPS; + T_prn_samples = T_prn_seconds * d_fs_in; + d_rem_code_phase_samples = d_next_rem_code_phase_samples; + K_blk_samples = T_prn_samples + d_rem_code_phase_samples; + d_next_prn_length_samples = round(K_blk_samples); //round to a discrete samples + d_next_rem_code_phase_samples = K_blk_samples - d_next_prn_length_samples; //rounding error + + /*! + * \todo Improve the lock detection algorithm! + */ + // ####### CN0 ESTIMATION AND LOCK DETECTORS ###### + if (d_cn0_estimation_counter < CN0_ESTIMATION_SAMPLES) + { + // fill buffer with prompt correlator output values + d_Prompt_buffer[d_cn0_estimation_counter] = *d_Prompt; + d_cn0_estimation_counter++; + } + else + { + d_cn0_estimation_counter = 0; + d_CN0_SNV_dB_Hz = galileo_e1_CN0_SNV(d_Prompt_buffer, CN0_ESTIMATION_SAMPLES, d_fs_in); + d_carrier_lock_test = carrier_lock_detector(d_Prompt_buffer, CN0_ESTIMATION_SAMPLES); + // ###### TRACKING UNLOCK NOTIFICATION ##### + if (std::abs(d_carrier_lock_test) > d_carrier_lock_threshold or d_CN0_SNV_dB_Hz < MINIMUM_VALID_CN0) + { + d_carrier_lock_fail_counter++; + } + else + { + if (d_carrier_lock_fail_counter > 0) d_carrier_lock_fail_counter--; + } + if (d_carrier_lock_fail_counter > MAXIMUM_LOCK_FAIL_COUNTER) + { + std::cout << "Channel " << d_channel << " loss of lock!" << std::endl ; + //tracking_message = 3; //loss of lock + //d_channel_internal_queue->push(tracking_message); + ControlMessageFactory* cmf = new ControlMessageFactory(); + if (d_queue != gr_msg_queue_sptr()) { + d_queue->handle(cmf->GetQueueMessage(d_channel, 2)); + } + delete cmf; + d_carrier_lock_fail_counter = 0; + d_enable_tracking = false; // TODO: check if disabling tracking is consistent with the channel state machine + + } + } + + // ########### Output the tracking data to navigation and PVT ########## + + current_synchro_data.Prompt_I = (double)(*d_Prompt).real(); + current_synchro_data.Prompt_Q = (double)(*d_Prompt).imag(); + // Tracking_timestamp_secs is aligned with the PRN start sample + current_synchro_data.Tracking_timestamp_secs=((double)d_sample_counter+(double)d_next_prn_length_samples+(double)d_next_rem_code_phase_samples)/(double)d_fs_in; + // This tracking block aligns the Tracking_timestamp_secs with the start sample of the PRN, thus, Code_phase_secs=0 + current_synchro_data.Code_phase_secs=0; + current_synchro_data.Carrier_phase_rads = (double)d_acc_carrier_phase_rad; + current_synchro_data.CN0_dB_hz = (double)d_CN0_SNV_dB_Hz; + *out[0] = current_synchro_data; + + // ########## DEBUG OUTPUT + /*! + * \todo The stop timer has to be moved to the signal source! + */ + // debug: Second counter in channel 0 + if (d_channel == 0) + { + if (floor(d_sample_counter / d_fs_in) != d_last_seg) + { + d_last_seg = floor(d_sample_counter / d_fs_in); + std::cout << "Current input signal time = " << d_last_seg << " [s]" << std::endl; + std::cout << "Tracking CH " << d_channel << ": Satellite " << Gnss_Satellite(systemName[sys], d_acquisition_gnss_synchro->PRN) + << ", CN0 = " << d_CN0_SNV_dB_Hz << " [dB-Hz]" << std::endl; + } + } + else + { + if (floor(d_sample_counter / d_fs_in) != d_last_seg) + { + d_last_seg = floor(d_sample_counter / d_fs_in); + std::cout << "Tracking CH " << d_channel << ": Satellite " << Gnss_Satellite(systemName[sys], d_acquisition_gnss_synchro->PRN) + << ", CN0 = " << d_CN0_SNV_dB_Hz << " [dB-Hz]" << std::endl; + } + } + } + else + { + *d_Early = gr_complex(0,0); + *d_Prompt = gr_complex(0,0); + *d_Late = gr_complex(0,0); + Gnss_Synchro **out = (Gnss_Synchro **) &output_items[0]; //block output streams pointer + // GNSS_SYNCHRO OBJECT to interchange data between tracking->telemetry_decoder + Gnss_Synchro current_synchro_data; + *out[0] = current_synchro_data; + + //! When tracking is disabled an array of 1's is sent to maintain the TCP connection + boost::array tx_variables_array = {{1,1,1,1,1,1,1,1,1,1,1,1,0}}; + d_tcp_com.send_receive_tcp_packet_galileo_e1(tx_variables_array, &tcp_data); + } + + if(d_dump) + { + // MULTIPLEXED FILE RECORDING - Record results to file + float prompt_I; + float prompt_Q; + float tmp_VE, tmp_E, tmp_P, tmp_L, tmp_VL; + float tmp_float; + tmp_float=0; + double tmp_double; + prompt_I = (*d_Prompt).real(); + prompt_Q = (*d_Prompt).imag(); + tmp_VE = std::abs(*d_Very_Early); + tmp_E = std::abs(*d_Early); + tmp_P = std::abs(*d_Prompt); + tmp_L = std::abs(*d_Late); + tmp_VL = std::abs(*d_Very_Late); + + try + { + // EPR + d_dump_file.write((char*)&tmp_VE, sizeof(float)); + d_dump_file.write((char*)&tmp_E, sizeof(float)); + d_dump_file.write((char*)&tmp_P, sizeof(float)); + d_dump_file.write((char*)&tmp_L, sizeof(float)); + d_dump_file.write((char*)&tmp_VL, sizeof(float)); + // PROMPT I and Q (to analyze navigation symbols) + d_dump_file.write((char*)&prompt_I, sizeof(float)); + d_dump_file.write((char*)&prompt_Q, sizeof(float)); + // PRN start sample stamp + d_dump_file.write((char*)&d_sample_counter, sizeof(unsigned long int)); + // accumulated carrier phase + d_dump_file.write((char*)&d_acc_carrier_phase_rad, sizeof(float)); + + // carrier and code frequency + d_dump_file.write((char*)&d_carrier_doppler_hz, sizeof(float)); + d_dump_file.write((char*)&d_code_freq_hz, sizeof(float)); + + //PLL commands + d_dump_file.write((char*)&tmp_float, sizeof(float)); + d_dump_file.write((char*)&carr_nco_hz, sizeof(float)); + + //DLL commands + d_dump_file.write((char*)&tmp_float, sizeof(float)); + d_dump_file.write((char*)&code_nco_chips, sizeof(float)); + + // CN0 and carrier lock test + d_dump_file.write((char*)&d_CN0_SNV_dB_Hz, sizeof(float)); + d_dump_file.write((char*)&d_carrier_lock_test, sizeof(float)); + + // AUX vars (for debug purposes) + tmp_float = d_rem_code_phase_samples; + d_dump_file.write((char*)&tmp_float, sizeof(float)); + tmp_double=(double)(d_sample_counter+d_current_prn_length_samples); + d_dump_file.write((char*)&tmp_double, sizeof(double)); + } + catch (std::ifstream::failure e) + { + std::cout << "Exception writing trk dump file " << e.what() << std::endl; + } + } +// if(d_current_prn_length_samples!=d_vector_length) +// std::cout << "d_current_prn_length_samples = " << d_current_prn_length_samples << std::endl; + consume_each(d_current_prn_length_samples); // this is necesary in gr_block derivates + d_sample_counter += d_current_prn_length_samples; //count for the processed samples + return 1; //output tracking result ALWAYS even in the case of d_enable_tracking==false +} + + + +void Galileo_E1_Tcp_Connector_Tracking_cc::set_channel(unsigned int channel) +{ + d_channel = channel; + LOG_AT_LEVEL(INFO) << "Tracking Channel set to " << d_channel; + // ############# ENABLE DATA FILE LOG ################# + if (d_dump==true) + { + if (d_dump_file.is_open() == false) + { + try + { + d_dump_filename.append(boost::lexical_cast(d_channel)); + d_dump_filename.append(".dat"); + d_dump_file.exceptions (std::ifstream::failbit | std::ifstream::badbit); + d_dump_file.open(d_dump_filename.c_str(), std::ios::out | std::ios::binary); + std::cout << "Tracking dump enabled on channel " << d_channel << " Log file: " << d_dump_filename.c_str() << std::endl; + } + catch (std::ifstream::failure e) + { + std::cout << "channel " << d_channel << " Exception opening trk dump file " << e.what() << std::endl; + } + } + } + + //! Listen for connections on a TCP port + if (d_listen_connection == true) + { + d_port = d_port_ch0 + d_channel; + d_listen_connection = d_tcp_com.listen_tcp_connection(d_port,d_port_ch0); + } +} + + + +void Galileo_E1_Tcp_Connector_Tracking_cc::set_channel_queue(concurrent_queue *channel_internal_queue) +{ + d_channel_internal_queue = channel_internal_queue; +} + +void Galileo_E1_Tcp_Connector_Tracking_cc::set_gnss_synchro(Gnss_Synchro* p_gnss_synchro) +{ + d_acquisition_gnss_synchro = p_gnss_synchro; + + // Gnss_Satellite(satellite.get_system(), satellite.get_PRN()); + //DLOG(INFO) << "Tracking code phase set to " << d_acq_code_phase_samples; + //DLOG(INFO) << "Tracking carrier doppler set to " << d_acq_carrier_doppler_hz; + //DLOG(INFO) << "Tracking Satellite set to " << d_satellite; + +} diff --git a/src/algorithms/tracking/gnuradio_blocks/galileo_e1_tcp_connector_tracking_cc.h b/src/algorithms/tracking/gnuradio_blocks/galileo_e1_tcp_connector_tracking_cc.h new file mode 100644 index 000000000..901c7fc0f --- /dev/null +++ b/src/algorithms/tracking/gnuradio_blocks/galileo_e1_tcp_connector_tracking_cc.h @@ -0,0 +1,215 @@ +/*! + * \file gps_l1_ca_tcp_connector_tracking_cc.h + * \brief Interface of a TCP connector block based on code DLL + carrier PLL VEML (Very Early + * Minus Late) tracking block for Galileo E1 signals + * \author David Pubill, 2012. dpubill(at)cttc.es + * Luis Esteve, 2012. luis(at)epsilon-formacion.com + * Javier Arribas, 2011. jarribas(at)cttc.es + * + * Code DLL + carrier PLL according to the algorithms described in: + * K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen, + * A Software-Defined GPS and Galileo Receiver. A Single-Frequency Approach, + * Birkhauser, 2007 + * + * ------------------------------------------------------------------------- + * + * Copyright (C) 2010-2012 (see AUTHORS file for a list of contributors) + * + * GNSS-SDR is a software defined Global Navigation + * Satellite Systems receiver + * + * This file is part of GNSS-SDR. + * + * GNSS-SDR is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * at your option) any later version. + * + * GNSS-SDR is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNSS-SDR. If not, see . + * + * ------------------------------------------------------------------------- + */ +#ifndef GNSS_SDR_GALILEO_E1_TCP_CONNECTOR_TRACKING_CC_H +#define GNSS_SDR_GALILEO_E1_TCP_CONNECTOR_TRACKING_CC_H + +#include +#include +#include +#include +#include +#include + +#include "concurrent_queue.h" +#include "gnss_synchro.h" +#include "tracking_2nd_DLL_filter.h" +#include "tracking_2nd_PLL_filter.h" +#include "correlator.h" +#include "tcp_communication.h" + + + +class Galileo_E1_Tcp_Connector_Tracking_cc; +typedef boost::shared_ptr + galileo_e1_tcp_connector_tracking_cc_sptr; + +galileo_e1_tcp_connector_tracking_cc_sptr +galileo_e1_tcp_connector_make_tracking_cc(long if_freq, + long fs_in, unsigned + int vector_length, + gr_msg_queue_sptr queue, + bool dump, + std::string dump_filename, + float pll_bw_hz, + float dll_bw_hz, + float early_late_space_chips, + float very_early_late_space_chips, + size_t port_ch0); + +/*! + * \brief This class implements a code DLL + carrier PLL VEML (Very Early + * Minus Late) tracking block for Galileo E1 signals + */ +class Galileo_E1_Tcp_Connector_Tracking_cc: public gr_block +{ +public: + + ~Galileo_E1_Tcp_Connector_Tracking_cc(); + + void set_channel(unsigned int channel); + void set_gnss_synchro(Gnss_Synchro* p_gnss_synchro); + void start_tracking(); + void set_channel_queue(concurrent_queue *channel_internal_queue); + + + int general_work (int noutput_items, gr_vector_int &ninput_items, + gr_vector_const_void_star &input_items, gr_vector_void_star &output_items); + + void forecast (int noutput_items, gr_vector_int &ninput_items_required); + + +private: + + friend galileo_e1_tcp_connector_tracking_cc_sptr + galileo_e1_tcp_connector_make_tracking_cc(long if_freq, + long fs_in, unsigned + int vector_length, + gr_msg_queue_sptr queue, + bool dump, + std::string dump_filename, + float pll_bw_hz, + float dll_bw_hz, + float early_late_space_chips, + float very_early_late_space_chips, + size_t port_ch0); + + Galileo_E1_Tcp_Connector_Tracking_cc(long if_freq, + long fs_in, unsigned + int vector_length, + gr_msg_queue_sptr queue, + bool dump, + std::string dump_filename, + float pll_bw_hz, + float dll_bw_hz, + float early_late_space_chips, + float very_early_late_space_chips, + size_t port_ch0); + + void update_local_code(); + + void update_local_carrier(); + + // tracking configuration vars + gr_msg_queue_sptr d_queue; + concurrent_queue *d_channel_internal_queue; + unsigned int d_vector_length; + bool d_dump; + + Gnss_Synchro* d_acquisition_gnss_synchro; + unsigned int d_channel; + int d_last_seg; + long d_if_freq; + long d_fs_in; + + float d_early_late_spc_chips; + float d_very_early_late_spc_chips; + + float d_code_phase_step_chips; + + gr_complex* d_ca_code; + + gr_complex* d_very_early_code; + gr_complex* d_early_code; + gr_complex* d_prompt_code; + gr_complex* d_late_code; + gr_complex* d_very_late_code; + gr_complex* d_carr_sign; + + gr_complex *d_Very_Early; + gr_complex *d_Early; + gr_complex *d_Prompt; + gr_complex *d_Late; + gr_complex *d_Very_Late; + + // remaining code phase and carrier phase between tracking loops + float d_rem_code_phase_samples; + float d_next_rem_code_phase_samples; + float d_rem_carr_phase_rad; + + // PLL and DLL filter library + Tracking_2nd_DLL_filter d_code_loop_filter; + Tracking_2nd_PLL_filter d_carrier_loop_filter; + + // acquisition + float d_acq_code_phase_samples; + float d_acq_carrier_doppler_hz; + + // correlator + Correlator d_correlator; + + // tracking vars + float d_code_freq_hz; + float d_carrier_doppler_hz; + float d_acc_carrier_phase_rad; + float d_code_phase_samples; + size_t d_port_ch0; + size_t d_port; + int d_listen_connection; + float d_control_id; + tcp_communication d_tcp_com; + + //PRN period in samples + int d_current_prn_length_samples; + int d_next_prn_length_samples; + //double d_sample_counter_seconds; + + //processing samples counters + unsigned long int d_sample_counter; + unsigned long int d_acq_sample_stamp; + + // CN0 estimation and lock detector + int d_cn0_estimation_counter; + gr_complex* d_Prompt_buffer; + float d_carrier_lock_test; + float d_CN0_SNV_dB_Hz; + float d_carrier_lock_threshold; + int d_carrier_lock_fail_counter; + + // control vars + bool d_enable_tracking; + bool d_pull_in; + + // file dump + std::string d_dump_filename; + std::ofstream d_dump_file; + + std::map systemName; + std::string sys; +}; + +#endif //GNSS_SDR_GALILEO_E1_TCP_CONNECTOR_TRACKING_CC_H diff --git a/src/algorithms/tracking/gnuradio_blocks/gps_l1_ca_tcp_connector_tracking_cc.cc b/src/algorithms/tracking/gnuradio_blocks/gps_l1_ca_tcp_connector_tracking_cc.cc index 16a808dc2..1e5742ad2 100644 --- a/src/algorithms/tracking/gnuradio_blocks/gps_l1_ca_tcp_connector_tracking_cc.cc +++ b/src/algorithms/tracking/gnuradio_blocks/gps_l1_ca_tcp_connector_tracking_cc.cc @@ -61,8 +61,6 @@ #define CN0_ESTIMATION_SAMPLES 10 #define MINIMUM_VALID_CN0 25 #define MAXIMUM_LOCK_FAIL_COUNTER 200 -#define NUM_TX_VARIABLES 9 -#define NUM_RX_VARIABLES 4 using google::LogMessage; @@ -356,16 +354,6 @@ Gps_L1_Ca_Tcp_Connector_Tracking_cc::~Gps_L1_Ca_Tcp_Connector_Tracking_cc() d_tcp_com.close_tcp_connection(d_port); } -tcp_packet_data::tcp_packet_data() { - - proc_pack_code_error = 0; - proc_pack_carr_error = 0; - proc_pack_carrier_doppler_hz = 0; -} - -tcp_packet_data::~tcp_packet_data() { -} - /* Tracking signal processing * Notice that this is a class derived from gr_sync_decimator, so each of the ninput_items has vector_length samples @@ -462,8 +450,8 @@ int Gps_L1_Ca_Tcp_Connector_Tracking_cc::general_work (int noutput_items, gr_vec d_control_id++; //! Send and receive a TCP packet - boost::array tx_variables_array = {{d_control_id,(*d_Early).real(),(*d_Early).imag(),(*d_Late).real(),(*d_Late).imag(),(*d_Prompt).real(),(*d_Prompt).imag(),d_acq_carrier_doppler_hz,1}}; - d_tcp_com.send_receive_tcp_packet(tx_variables_array, &tcp_data); + boost::array tx_variables_array = {{d_control_id,(*d_Early).real(),(*d_Early).imag(),(*d_Late).real(),(*d_Late).imag(),(*d_Prompt).real(),(*d_Prompt).imag(),d_acq_carrier_doppler_hz,1}}; + d_tcp_com.send_receive_tcp_packet_gps_l1_ca(tx_variables_array, &tcp_data); //! Recover the tracking data code_error = tcp_data.proc_pack_code_error; @@ -585,8 +573,8 @@ int Gps_L1_Ca_Tcp_Connector_Tracking_cc::general_work (int noutput_items, gr_vec *out[0] = current_synchro_data; //! When tracking is disabled an array of 1's is sent to maintain the TCP connection - boost::array tx_variables_array = {{1,1,1,1,1,1,1,1,0}}; - d_tcp_com.send_receive_tcp_packet(tx_variables_array, &tcp_data); + boost::array tx_variables_array = {{1,1,1,1,1,1,1,1,0}}; + d_tcp_com.send_receive_tcp_packet_gps_l1_ca(tx_variables_array, &tcp_data); } if(d_dump) diff --git a/src/algorithms/tracking/gnuradio_blocks/jamfile.jam b/src/algorithms/tracking/gnuradio_blocks/jamfile.jam index d2d2d50e0..18e7940e5 100644 --- a/src/algorithms/tracking/gnuradio_blocks/jamfile.jam +++ b/src/algorithms/tracking/gnuradio_blocks/jamfile.jam @@ -4,4 +4,5 @@ obj gps_l1_ca_dll_pll_tracking_cc : gps_l1_ca_dll_pll_tracking_cc.cc : obj gps_l1_ca_dll_fll_pll_tracking_cc : gps_l1_ca_dll_fll_pll_tracking_cc.cc : darwin:GNSS_SDR_USE_BOOST_ROUND ; obj gps_l1_ca_tcp_connector_tracking_cc : gps_l1_ca_tcp_connector_tracking_cc.cc : darwin:GNSS_SDR_USE_BOOST_ROUND ; obj galileo_e1_dll_pll_veml_tracking_cc : galileo_e1_dll_pll_veml_tracking_cc.cc : darwin:GNSS_SDR_USE_BOOST_ROUND ; +obj galileo_e1_tcp_connector_tracking_cc : galileo_e1_tcp_connector_tracking_cc.cc : darwin:GNSS_SDR_USE_BOOST_ROUND ; obj gps_l1_ca_dll_pll_optim_tracking_cc : gps_l1_ca_dll_pll_optim_tracking_cc.cc : darwin:GNSS_SDR_USE_BOOST_ROUND ; diff --git a/src/algorithms/tracking/libs/jamfile.jam b/src/algorithms/tracking/libs/jamfile.jam index 98c8a58f8..84f333bad 100644 --- a/src/algorithms/tracking/libs/jamfile.jam +++ b/src/algorithms/tracking/libs/jamfile.jam @@ -8,3 +8,4 @@ obj tracking_2nd_DLL_filter : tracking_2nd_DLL_filter.cc ; obj correlator : correlator.cc ; obj cordic : cordic.cc ; obj tcp_communication : tcp_communication.cc ; +obj tcp_packet_data : tcp_packet_data.cc ; diff --git a/src/algorithms/tracking/libs/tcp_communication.cc b/src/algorithms/tracking/libs/tcp_communication.cc index 63534d69b..4a2115490 100644 --- a/src/algorithms/tracking/libs/tcp_communication.cc +++ b/src/algorithms/tracking/libs/tcp_communication.cc @@ -35,9 +35,6 @@ #include -#define NUM_TX_VARIABLES 9 -#define NUM_RX_VARIABLES 4 - tcp_communication::tcp_communication() : tcp_socket_(io_service_) {} @@ -82,7 +79,7 @@ int tcp_communication::listen_tcp_connection(size_t d_port_, size_t d_port_ch0_) -void tcp_communication::send_receive_tcp_packet(boost::array buf, tcp_packet_data *tcp_data_) +void tcp_communication::send_receive_tcp_packet_galileo_e1(boost::array buf, tcp_packet_data *tcp_data_) { int controlc = 0; boost::array readbuf; @@ -116,7 +113,39 @@ void tcp_communication::send_receive_tcp_packet(boost::array buf, tcp_packet_data *tcp_data_) +{ + int controlc = 0; + boost::array readbuf; + float d_control_id_ = buf.data()[0]; + try + { + // Send a TCP packet + tcp_socket_.write_some(boost::asio::buffer(buf)); + + // Read the received TCP packet + tcp_socket_.read_some(boost::asio::buffer(readbuf)); + + //! Control. The GNSS-SDR program ends if an error in a TCP packet is detected. + if (d_control_id_ != readbuf.data()[0]) + { + throw "Packet error!"; + } + + // Recover the variables received + tcp_data_->proc_pack_code_error = readbuf.data()[1]; + tcp_data_->proc_pack_carr_error = readbuf.data()[2]; + tcp_data_->proc_pack_carrier_doppler_hz = readbuf.data()[3]; + } + + catch(std::exception& e) + { + std::cerr << "Exception: " << e.what() << ". Please press Ctrl+C to end the program." << std::endl; + std::cin >> controlc; + } + return; +} void tcp_communication::close_tcp_connection(size_t d_port_) { diff --git a/src/algorithms/tracking/libs/tcp_communication.h b/src/algorithms/tracking/libs/tcp_communication.h index 4be86ff1f..702d5537b 100644 --- a/src/algorithms/tracking/libs/tcp_communication.h +++ b/src/algorithms/tracking/libs/tcp_communication.h @@ -36,6 +36,9 @@ #include #include "tcp_packet_data.h" +#define NUM_TX_VARIABLES_GALILEO_E1 13 +#define NUM_TX_VARIABLES_GPS_L1_CA 9 +#define NUM_RX_VARIABLES 4 class tcp_communication { @@ -45,7 +48,8 @@ public: ~tcp_communication(); int listen_tcp_connection(size_t d_port_, size_t d_port_ch0_); - void send_receive_tcp_packet(boost::array buf, tcp_packet_data *tcp_data_); + void send_receive_tcp_packet_galileo_e1(boost::array buf, tcp_packet_data *tcp_data_); + void send_receive_tcp_packet_gps_l1_ca(boost::array buf, tcp_packet_data *tcp_data_); void close_tcp_connection(size_t d_port_); private: diff --git a/src/algorithms/tracking/libs/tcp_packet_data.cc b/src/algorithms/tracking/libs/tcp_packet_data.cc new file mode 100644 index 000000000..820574bce --- /dev/null +++ b/src/algorithms/tracking/libs/tcp_packet_data.cc @@ -0,0 +1,42 @@ +/*! + * \file tcp_packet_data.cc + * \brief Interface of the TCP packet data class + * \author David Pubill, 2011. dpubill(at)cttc.es + * + * + * ------------------------------------------------------------------------- + * + * Copyright (C) 2010-2012 (see AUTHORS file for a list of contributors) + * + * GNSS-SDR is a software defined Global Navigation + * Satellite Systems receiver + * + * This file is part of GNSS-SDR. + * + * GNSS-SDR is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * at your option) any later version. + * + * GNSS-SDR is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNSS-SDR. If not, see . + * + * ------------------------------------------------------------------------- + */ +#include "tcp_packet_data.h" + +tcp_packet_data::tcp_packet_data() +{ + + proc_pack_code_error = 0; + proc_pack_carr_error = 0; + proc_pack_carrier_doppler_hz = 0; +} + +tcp_packet_data::~tcp_packet_data() { +} diff --git a/src/core/receiver/gnss_block_factory.cc b/src/core/receiver/gnss_block_factory.cc index 6ea2d25d8..6db878173 100644 --- a/src/core/receiver/gnss_block_factory.cc +++ b/src/core/receiver/gnss_block_factory.cc @@ -60,6 +60,7 @@ #include "gps_l1_ca_dll_fll_pll_tracking.h" #include "gps_l1_ca_tcp_connector_tracking.h" #include "galileo_e1_dll_pll_veml_tracking.h" +#include "galileo_e1_tcp_connector_tracking.h" #include "gps_l1_ca_telemetry_decoder.h" #include "gps_l1_ca_observables.h" #include "gps_l1_ca_pvt.h" @@ -364,15 +365,20 @@ GNSSBlockInterface* GNSSBlockFactory::GetBlock( out_streams, queue); } else if (implementation.compare("GPS_L1_CA_TCP_CONNECTOR_Tracking") == 0) - { + { block = new GpsL1CaTcpConnectorTracking(configuration, role, in_streams, out_streams, queue); - } + } else if (implementation.compare("Galileo_E1_DLL_PLL_VEML_Tracking") == 0) - { + { block = new GalileoE1DllPllVemlTracking(configuration, role, in_streams, out_streams, queue); - } + } + else if (implementation.compare("Galileo_E1_TCP_CONNECTOR_Tracking") == 0) + { + block = new GalileoE1TcpConnectorTracking(configuration, role, in_streams, + out_streams, queue); + } // TELEMETRY DECODERS ---------------------------------------------------------- diff --git a/src/main/jamfile.jam b/src/main/jamfile.jam index c744f7850..2e11ecf61 100644 --- a/src/main/jamfile.jam +++ b/src/main/jamfile.jam @@ -55,11 +55,13 @@ exe gnss-sdr : main.cc ../algorithms/tracking/adapters//gps_l1_ca_dll_fll_pll_tracking ../algorithms/tracking/adapters//gps_l1_ca_tcp_connector_tracking ../algorithms/tracking/adapters//galileo_e1_dll_pll_veml_tracking +../algorithms/tracking/adapters//galileo_e1_tcp_connector_tracking ../algorithms/tracking/gnuradio_blocks//gps_l1_ca_dll_pll_tracking_cc ../algorithms/tracking/gnuradio_blocks//gps_l1_ca_dll_pll_optim_tracking_cc ../algorithms/tracking/gnuradio_blocks//gps_l1_ca_dll_fll_pll_tracking_cc ../algorithms/tracking/gnuradio_blocks//gps_l1_ca_tcp_connector_tracking_cc ../algorithms/tracking/gnuradio_blocks//galileo_e1_dll_pll_veml_tracking_cc +../algorithms/tracking/gnuradio_blocks//galileo_e1_tcp_connector_tracking_cc ../algorithms/tracking/libs//tracking_discriminators ../algorithms/tracking/libs//CN_estimators ../algorithms/tracking/libs//tracking_FLL_PLL_filter @@ -68,6 +70,7 @@ exe gnss-sdr : main.cc ../algorithms/tracking/libs//correlator ../algorithms/tracking/libs//cordic ../algorithms/tracking/libs//tcp_communication +../algorithms/tracking/libs//tcp_packet_data ../core/libs//INIReader ../core/libs//ini ../core/libs//string_converter diff --git a/src/tests/jamfile.jam b/src/tests/jamfile.jam index 249e0e3ae..86aa58978 100644 --- a/src/tests/jamfile.jam +++ b/src/tests/jamfile.jam @@ -52,11 +52,13 @@ exe run_tests : test_main.cc ../algorithms/tracking/adapters//gps_l1_ca_dll_fll_pll_tracking ../algorithms/tracking/adapters//gps_l1_ca_tcp_connector_tracking ../algorithms/tracking/adapters//galileo_e1_dll_pll_veml_tracking +../algorithms/tracking/adapters//galileo_e1_tcp_connector_tracking ../algorithms/tracking/gnuradio_blocks//gps_l1_ca_dll_pll_tracking_cc ../algorithms/tracking/gnuradio_blocks//gps_l1_ca_dll_pll_optim_tracking_cc ../algorithms/tracking/gnuradio_blocks//gps_l1_ca_dll_fll_pll_tracking_cc ../algorithms/tracking/gnuradio_blocks//gps_l1_ca_tcp_connector_tracking_cc ../algorithms/tracking/gnuradio_blocks//galileo_e1_dll_pll_veml_tracking_cc +../algorithms/tracking/gnuradio_blocks//galileo_e1_tcp_connector_tracking_cc ../algorithms/tracking/libs//tracking_discriminators ../algorithms/tracking/libs//CN_estimators ../algorithms/tracking/libs//tracking_FLL_PLL_filter @@ -65,6 +67,7 @@ exe run_tests : test_main.cc ../algorithms/tracking/libs//correlator ../algorithms/tracking/libs//cordic ../algorithms/tracking/libs//tcp_communication +../algorithms/tracking/libs//tcp_packet_data ../core/libs//INIReader ../core/libs//ini ../core/libs//string_converter diff --git a/src/utils/simulink/Single Thread/README_gnss_sdr_galileo_e1_tcp_connector_tracking.txt b/src/utils/simulink/Single Thread/README_gnss_sdr_galileo_e1_tcp_connector_tracking.txt new file mode 100644 index 000000000..3da3a7972 --- /dev/null +++ b/src/utils/simulink/Single Thread/README_gnss_sdr_galileo_e1_tcp_connector_tracking.txt @@ -0,0 +1,136 @@ + /*! + * \file README.txt + * \brief How to add a block to the Simulink Library repository of Matlab, + * how to use the "gnss_sdr_galileo_e1_tcp_connector_tracking_start.m" script and how + * to replace the tracking block of the library. + * + * \author David Pubill, 2012. dpubill(at)cttc.es + * + * ------------------------------------------------------------------------- + * + * Copyright (C) 2010-2012 (see AUTHORS file for a list of contributors) + * + * GNSS-SDR is a software defined Global Navigation + * Satellite Systems receiver + * + * This file is part of GNSS-SDR. + * + * GNSS-SDR is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * at your option) any later version. + * + * GNSS-SDR is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNSS-SDR. If not, see . + * + * ------------------------------------------------------------------------- + */ + + +IMPORTANT: Please, to use this tracking check the configuration file called +'gnss-sdr_galileo_e1_tcp_connector_tracking.conf'. There are two major changes: + 1.- Choose the [Galileo_E1_TCP_CONNECTOR_Tracking] tracking algorithm. + 2.- Choose a tcp port for channel 0 (e.g. Tracking.port_ch0=2070;) + + +A) HOW TO add a block to the Simulink Library repository of your Matlab installation + --------------------------------------------------------------------------------- + (These steps should be followed only the first time) + +1.- Copy the content of this folder to a folder accessible from Simulink. + +2.- In the Matlab Command Window type: + >> simulink; + to open the Simulink Library Browser. + +3.- Right-click on the Simulink/User-Defined Functions of the Simulink + Library menu, and click on "Open User-Defined Functions library" + (Window_1) + +4.- Open the library model 'gnss_sdr_galileo_e1_tcp_connector_tracking_lib.mdl' + (Window_2) + +5.- If this is not the first time there should be an existing 'gnss-sdr' + block in the 'User-Defined Functions' window that should be deleted + before drag and drop the new 'gnss_sdr' block (which includes 3 blocks: + - 'gnss_sdr_galileo_e1_tcp_connector_tracking_rx' block + - 'gnss_sdr_galileo_e1_tcp_connector_tracking' block + - 'gnss_sdr_galileo_e1_tcp_connector_tracking_tx' block) + from Window_2 to Window_1. A new message should appear: "This library + is locked. The action performed requires it to be unlocked". Then, + click on the "Unlock" button (the block will be copied) and close + Window_2. + +6.- Right-click on the 'gnss-sdr' block and click on "Link Options --> + Disable link", repeat the action but now clicking on "Link Options --> + Break link". This action disables and breaks the link with the + original library model. + +7.- On Window_1 save the "simulink/User-Defined Functions" library. + To do that go to "File > Save". Then, close Window_1. + +8.- From "Simulink Library Browser" window, press F5 to refresh and generate + the new Simulink Library repository (it may take a few seconds). This + completes the installation of the custom Simulink block. + + +B) HOW TO use the "gnss_sdr_galileo_e1_tcp_connector_tracking_start.m" script: + ---------------------------------------------------------------- + + ---------------------- ---------------- ---------------------- +| | | gnss_sdr_ | | | +| gnss_sdr_galileo_e1_ | | galileo_e1_ | | gnss_sdr_galileo_e1_ | +| tcp_connector_ | --> | tcp_connector_ | --> | tcp_connector_ | +| tracking_rx | | tracking | | tracking_tx | +| | | | | | + ---------------------- ---------------- ---------------------- + +The 'gnss_sdr_galileo_e1_tcp_connector_tracking_start.m' is the script that builds +and configures a simulink model for interacting with the GNSS-SDR platform +through a TCP communication. 'User parameters' can be modified but, by +default, these are the values assigned: + +%User parameters + host = '84.88.61.86'; %Remote IP address (GNSS-SDR computer IP) + port = 2070; %Remote port (GNSS-SDR computer port for Ch0) + num_vars_rx = 13; %Number of variables expected from GNSS-SDR + num_vars_tx = 4; %Number of variable to be transmitted to GNSS-SDR + timeout = '10'; %Timeout in seconds + +'host', 'port' and 'timeout' parameters configure both +'gnss_sdr_galileo_e1_tcp_connector_tracking_rx' and +'gnss_sdr_galileo_e1_tcp_connector_tracking_tx' blocks. The 'port' parameter +sets the base port number for the first channel (ch0). Each of the subsequent +channels increases their port by one unit (e.g. ch0_port=2070, ch1_port=2071,...). + +Also the name of the tracking block can be modified. It must match with +the Simulink model name: + + %Name of the tracking block, it must match the Simulink model name + tracking_block_name = 'gnss_sdr_galileo_e1_tcp_connector_tracking'; + +To run the script just type in the Matlab Command window the following: + +>>gnss_sdr_galileo_e1_tcp_connector_tracking_start(N); + +where N must match the number of channels configured in the GNSS-SDR +platform. + + +C) HOW TO replace the tracking block of the library + ------------------------------------------------ + +1.- Open the library model 'gnss_sdr_galileo_e1_tcp_connector_tracking_lib.mdl' +2.- Unlock the library. Click on "Edit > Unlock Library". +3.- Open the "gnss-sdr" block and change the "gnss_sdr_galileo_e1_tcp_connector_tracking" + block by another one. If the name is different it must be updated in + the "gnss_sdr_galileo_e1_tcp_connector_parallel_tracking_start.m" code (see + section B) +4.- Save the new library. +5.- Go to section A and follow the instructions. + diff --git a/src/utils/simulink/Single Thread/gnss_sdr_galileo_e1_tcp_connector_tracking_lib.mdl b/src/utils/simulink/Single Thread/gnss_sdr_galileo_e1_tcp_connector_tracking_lib.mdl new file mode 100644 index 000000000..99f227ef7 --- /dev/null +++ b/src/utils/simulink/Single Thread/gnss_sdr_galileo_e1_tcp_connector_tracking_lib.mdl @@ -0,0 +1,62086 @@ +Library { + Name "gnss_sdr_galileo_e1_tcp_connector_tracking_lib" + Version 7.6 + MdlSubVersion 0 + SavedCharacterEncoding "windows-1252" + LibraryType "BlockLibrary" + SaveDefaultBlockParams on + ScopeRefreshTime 0.035000 + OverrideScopeRefreshTime on + DisableAllScopes off + MaxMDLFileLineLength 120 + Created "Thu Mar 08 11:41:48 2012" + Creator "David Pubill" + UpdateHistory "UpdateHistoryNever" + ModifiedByFormat "%" + LastModifiedBy "David Pubill" + ModifiedDateFormat "%" + LastModifiedDate "Fri Oct 19 12:46:31 2012" + RTWModifiedTimeStamp 272551143 + ModelVersionFormat "1.%" + ConfigurationManager "None" + SampleTimeColors off + SampleTimeAnnotations off + LibraryLinkDisplay "none" + WideLines off + ShowLineDimensions off + ShowPortDataTypes off + ShowLoopsOnError on + IgnoreBidirectionalLines off + ShowStorageClass off + ShowTestPointIcons on + ShowSignalResolutionIcons on + ShowViewerIcons on + SortedOrder off + ExecutionContextIcon off + ShowLinearizationAnnotations on + BlockNameDataTip off + BlockParametersDataTip off + BlockDescriptionStringDataTip off + ToolBar on + StatusBar on + BrowserShowLibraryLinks off + BrowserLookUnderMasks off + SimulationMode "normal" + LinearizationMsg "none" + Profile off + ParamWorkspaceSource "MATLABWorkspace" + RecordCoverage off + CovSaveName "covdata" + CovMetricSettings "dw" + CovNameIncrementing off + CovHtmlReporting on + CovForceBlockReductionOff on + covSaveCumulativeToWorkspaceVar on + CovSaveSingleToWorkspaceVar on + CovCumulativeReport off + CovReportOnPause on + CovModelRefEnable "Off" + CovExternalEMLEnable off + ExtModeBatchMode off + ExtModeEnableFloating on + ExtModeTrigType "manual" + ExtModeTrigMode "normal" + ExtModeTrigPort "1" + ExtModeTrigElement "any" + ExtModeTrigDuration 1000 + ExtModeTrigDurationFloating "auto" + ExtModeTrigHoldOff 0 + ExtModeTrigDelay 0 + ExtModeTrigDirection "rising" + ExtModeTrigLevel 0 + ExtModeArchiveMode "off" + ExtModeAutoIncOneShot off + ExtModeIncDirWhenArm off + ExtModeAddSuffixToVar off + ExtModeWriteAllDataToWs off + ExtModeArmWhenConnect on + ExtModeSkipDownloadWhenConnect off + ExtModeLogAll on + ExtModeAutoUpdateStatusClock on + ShowModelReferenceBlockVersion off + ShowModelReferenceBlockIO off + Array { + Type "Handle" + Dimension 1 + Simulink.ConfigSet { + $ObjectID 1 + Version "1.10.0" + Array { + Type "Handle" + Dimension 9 + Simulink.SolverCC { + $ObjectID 2 + Version "1.10.0" + StartTime "0.0" + StopTime "10.0" + AbsTol "auto" + FixedStep "auto" + InitialStep "auto" + MaxNumMinSteps "-1" + MaxOrder 5 + ZcThreshold "auto" + ConsecutiveZCsStepRelTol "10*128*eps" + MaxConsecutiveZCs "1000" + ExtrapolationOrder 4 + NumberNewtonIterations 1 + MaxStep "auto" + MinStep "auto" + MaxConsecutiveMinStep "1" + RelTol "1e-3" + SolverMode "Auto" + ConcurrentTasks off + Solver "VariableStepDiscrete" + SolverName "VariableStepDiscrete" + SolverJacobianMethodControl "auto" + ShapePreserveControl "DisableAll" + ZeroCrossControl "UseLocalSettings" + ZeroCrossAlgorithm "Nonadaptive" + AlgebraicLoopSolver "TrustRegion" + SolverResetMethod "Fast" + PositivePriorityOrder off + AutoInsertRateTranBlk off + SampleTimeConstraint "Unconstrained" + InsertRTBMode "Whenever possible" + } + Simulink.DataIOCC { + $ObjectID 3 + Version "1.10.0" + Decimation "1" + ExternalInput "[t, u]" + FinalStateName "xFinal" + InitialState "xInitial" + LimitDataPoints on + MaxDataPoints "1000" + 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+ UseSpecifiedMinMax off + InlineInvariantSignals off + OptimizeBlockIOStorage on + BufferReuse on + EnhancedBackFolding off + StrengthReduction off + ExpressionFolding on + BooleansAsBitfields off + BitfieldContainerType "uint_T" + EnableMemcpy on + MemcpyThreshold 64 + PassReuseOutputArgsAs "Structure reference" + ExpressionDepthLimit 2147483647 + FoldNonRolledExpr on + LocalBlockOutputs on + RollThreshold 5 + SystemCodeInlineAuto off + StateBitsets off + DataBitsets off + UseTempVars off + ZeroExternalMemoryAtStartup on + ZeroInternalMemoryAtStartup on + InitFltsAndDblsToZero off + NoFixptDivByZeroProtection off + EfficientFloat2IntCast off + EfficientMapNaN2IntZero on + OptimizeModelRefInitCode off + LifeSpan "inf" + MaxStackSize "Inherit from target" + BufferReusableBoundary on + SimCompilerOptimization "Off" + AccelVerboseBuild off + } + Simulink.DebuggingCC { + $ObjectID 5 + Version "1.10.0" + RTPrefix "error" + ConsistencyChecking "none" + ArrayBoundsChecking "none" + SignalInfNanChecking "none" + SignalRangeChecking "none" + ReadBeforeWriteMsg "UseLocalSettings" + WriteAfterWriteMsg "UseLocalSettings" + WriteAfterReadMsg "UseLocalSettings" + AlgebraicLoopMsg "warning" + ArtificialAlgebraicLoopMsg "warning" + SaveWithDisabledLinksMsg "warning" + SaveWithParameterizedLinksMsg "none" + CheckSSInitialOutputMsg on + UnderspecifiedInitializationDetection "Classic" + MergeDetectMultiDrivingBlocksExec "none" + CheckExecutionContextPreStartOutputMsg off + CheckExecutionContextRuntimeOutputMsg off + SignalResolutionControl "UseLocalSettings" + BlockPriorityViolationMsg "warning" + MinStepSizeMsg "warning" + TimeAdjustmentMsg "none" + MaxConsecutiveZCsMsg "error" + MaskedZcDiagnostic "warning" + IgnoredZcDiagnostic "warning" + SolverPrmCheckMsg "warning" + InheritedTsInSrcMsg "warning" + DiscreteInheritContinuousMsg "warning" + MultiTaskDSMMsg "error" + MultiTaskCondExecSysMsg "error" + MultiTaskRateTransMsg "error" + SingleTaskRateTransMsg "none" + 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For \n * further information, please check the R" + "EADME_gnss_sdr_galileo_e1_tcp_connector_tracking.txt file.\n *\n * \\author David Pubill, 2012. dpubill(at)ctt" + "c.es\n * -------------------------------------------------------------------------\n *\n * Copyright (C) 2010" + "-2012 (see AUTHORS file for a list of contributors)\n *\n * GNSS-SDR is a software defined Global Navigation\n" + " * Satellite Systems receiver\n *\n * This file is part of GNSS-SDR.\n *\n * GNSS-SDR is free soft" + "ware: you can redistribute it and/or modify\n * it under the terms of the GNU General Public License as publish" + "ed by\n * the Free Software Foundation, either version 3 of the License, or\n * at your option) any later vers" + "ion.\n *\n * GNSS-SDR is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; withou" + "t even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU Gener" + "al Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n" + " * along with GNSS-SDR. If not, see .\n *\n * ---------------------------------" + "----------------------------------------\n */" + MaskDisplayString "/*! \\n * \\file gnss_sdr_galileo_e1_tcp_connector_tracking_lib.mdl\\n * \\brief gns" + "s_sdr_galileo_e1_tcp_connector_tracking Simulink library model. For \\n * further information, please check th" + "e README_gnss_sdr_galileo_e1_tcp_connector_tracking.txt file.\\n *\\n * \\author David Pubill, 2012. dpubill(a" + "t)cttc.es\\n * -------------------------------------------------------------------------\\n *\\n * Copyright " + "(C) 2010-2012 (see AUTHORS file for a list of contributors)\\n *\\n * GNSS-SDR is a software defined Global N" + "avigation\\n * Satellite Systems receiver\\n *\\n * This file is part of GNSS-SDR.\\n *\\n * GNSS-" + "SDR is free software: you can redistribute it and/or modify\\n * it under the terms of the GNU General Public L" + "icense as published by\\n * the Free Software Foundation, either version 3 of the License, or\\n * at your opt" + "ion) any later version.\\n *\\n * GNSS-SDR is distributed in the hope that it will be useful,\\n * but WITHOU" + "T ANY WARRANTY; without even the implied warranty of\\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. " + " See the\\n * GNU General Public License for more details.\\n *\\n * You should have received a copy of the G" + "NU General Public License\\n * along with GNSS-SDR. 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+ Inputs "*/" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + Port { + PortNumber 1 + Name "Tau1" + RTWStorageClass "Auto" + DataLoggingNameMode "SignalName" + } + } + Block { + BlockType Product + Name "Divide5" + SID "4288" + Ports [2, 1] + Position [370, 275, 405, 375] + ShowName off + Inputs "*/" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + Port { + PortNumber 1 + Name "Tau2" + RTWStorageClass "Auto" + DataLoggingNameMode "SignalName" + } + } + Block { + BlockType Product + Name "Divide6" + SID "4289" + Ports [2, 1] + Position [545, 145, 580, 245] + ShowName off + Inputs "*/" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Divide7" + SID "4290" + Ports [2, 1] + Position [545, 255, 580, 355] + ShowName off + Inputs "*/" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product4" + SID "4291" + Ports [2, 1] + Position [265, 225, 295, 265] + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product5" + SID "4292" + Ports [2, 1] + Position [845, 106, 875, 224] + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product6" + SID "4293" + Ports [2, 1] + Position [685, 274, 715, 316] + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Subtract1" + SID "4294" + Ports [2, 1] + Position [685, 35, 710, 95] + ShowName off + Inputs "+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Switch + Name "Switch4" + SID "4295" + Position [485, 27, 535, 133] + ShowName off + Threshold "1" + InputSameDT off + SaturateOnIntegerOverflow off + } + Block { + BlockType Switch + Name "Switch5" + SID "4296" + Position [825, 277, 875, 383] + ShowName off + Threshold "1" + InputSameDT off + SaturateOnIntegerOverflow off + } + Block { + BlockType Switch + Name "Switch6" + SID "4297" + Position [765, 82, 815, 188] + ShowName off + Threshold "1" + InputSameDT off + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "Wn" + SID "4298" + Position [170, 227, 215, 263] + Gain "(8*zeta_PLL)/(1+(4*(zeta_PLL)^2))" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Constant + Name "d_pdi_carr" + SID "4299" + Position [475, 264, 525, 296] + Value "d_pdi_carr" + SampleTime "-1" + } + Block { + BlockType Constant + Name "k" + SID "4300" + Position [300, 179, 350, 211] + Value "k_PLL" + SampleTime "-1" + } + Block { + BlockType Constant + Name "lbw" + SID "4301" + Position [100, 229, 150, 261] + Value "B_PLL" + SampleTime "-1" + } + Block { + BlockType Outport + Name "carr_nco" + SID "4302" + Position [1040, 203, 1070, 217] + IconDisplay "Port number" + } + Line { + SrcBlock "d_pdi_carr" + SrcPort 1 + DstBlock "Divide7" + DstPort 1 + } + Line { + SrcBlock "Divide7" + SrcPort 1 + DstBlock "Product6" + DstPort 2 + } + Line { + SrcBlock "Add1" + SrcPort 1 + Points [45, 0] + Branch { + DstBlock "carr_nco" + DstPort 1 + } + Branch { + Points [0, 100] + DstBlock "Delay1" + DstPort 1 + } + } + Line { + SrcBlock "Product5" + SrcPort 1 + DstBlock "Add1" + DstPort 1 + } + Line { + SrcBlock "Divide6" + SrcPort 1 + DstBlock "Product5" + DstPort 2 + } + Line { + SrcBlock "carr_error" + SrcPort 1 + Points [395, 0] + Branch { + Points [175, 0; 0, 30] + Branch { + Points [0, 235] + DstBlock "Product6" + DstPort 1 + } + Branch { + DstBlock "Subtract1" + DstPort 1 + } + } + Branch { + Points [0, 25] + DstBlock "Switch4" + DstPort 1 + } + } + Line { + Name "Tau2" + Labels [0, 0] + SrcBlock "Divide5" + SrcPort 1 + Points [35, 0; 0, -155] + DstBlock "Divide6" + DstPort 1 + } + Line { + SrcBlock "2*zeta" + SrcPort 1 + DstBlock "Divide5" + DstPort 1 + } + Line { + SrcBlock "Product4" + SrcPort 1 + DstBlock "Divide4" + DstPort 2 + } + Line { + SrcBlock "k" + SrcPort 1 + DstBlock "Divide4" + DstPort 1 + } + Line { + Name "Tau1" + Labels [0, 0] + SrcBlock "Divide4" + SrcPort 1 + Points [55, 0] + Branch { + Points [0, 110] + DstBlock "Divide7" + DstPort 2 + } + Branch { + DstBlock "Divide6" + DstPort 2 + } + } + Line { + Labels [0, 0] + SrcBlock "lbw" + SrcPort 1 + DstBlock "Wn" + DstPort 1 + } + Line { + SrcBlock "Wn" + SrcPort 1 + Points [15, 0] + Branch { + Points [10, 0] + Branch { + Points [0, 10] + DstBlock "Product4" + DstPort 2 + } + Branch { + Points [0, -10] + DstBlock "Product4" + DstPort 1 + } + } + Branch { + Points [0, 105] + DstBlock "Divide5" + DstPort 2 + } + } + Line { + SrcBlock "Delay1" + SrcPort 1 + Points [-30, 0] + DstBlock "Add1" + DstPort 3 + } + Line { + SrcBlock "Subtract1" + SrcPort 1 + Points [20, 0; 0, 35] + DstBlock "Switch6" + DstPort 1 + } + Line { + SrcBlock "Switch6" + SrcPort 1 + DstBlock "Product5" + DstPort 1 + } + Line { + SrcBlock "Product6" + SrcPort 1 + DstBlock "Switch5" + DstPort 1 + } + Line { + SrcBlock "Switch5" + SrcPort 1 + Points [20, 0; 0, -120] + DstBlock "Add1" + DstPort 2 + } + Line { + SrcBlock "Constant5" + SrcPort 1 + DstBlock "Switch5" + DstPort 3 + } + Line { + SrcBlock "Delay3" + SrcPort 1 + DstBlock "Subtract1" + DstPort 2 + } + Line { + SrcBlock "Constant6" + SrcPort 1 + DstBlock "Switch4" + DstPort 3 + } + Line { + SrcBlock "enable_tracking" + SrcPort 1 + Points [25, 0] + Branch { + Points [335, 0] + Branch { + Points [0, 55] + DstBlock "Switch6" + DstPort 2 + } + Branch { + DstBlock "Switch4" + DstPort 2 + } + } + Branch { + Points [0, 300; 660, 0; 0, -50] + DstBlock "Switch5" + DstPort 2 + } + } + Line { + SrcBlock "Constant4" + SrcPort 1 + DstBlock "Switch6" + DstPort 3 + } + Line { + SrcBlock "Switch4" + SrcPort 1 + DstBlock "Delay3" + DstPort 1 + } + Annotation { + Position [998, 349] + } + Annotation { + Position [983, 334] + } + } + } + Block { + BlockType SubSystem + Name "PLL discriminator" + SID "2149" + Ports [1, 1] + Position [75, 18, 185, 82] + AncestorBlock "gnss_sdr_tcp_connector_tracking_lib/gnss_sdr/gnss_sdr_tcp_connector_tracking/Carrier Tracking \n" + "(PLL)/atan2(Q,I)1/PLL Costas loop two quadrant arctan discriminator" + LibraryVersion "*1.36" + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "PLL discriminator" + Location [259, 411, 754, 585] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + SIDHighWatermark "11685" + Block { + BlockType Inport + Name "P" + SID "2149:11670" + Position [15, 68, 45, 82] + IconDisplay "Port number" + } + Block { + BlockType Abs + Name "Abs" + SID "2149:11685" + Position [250, 115, 280, 145] + ShowName off + SaturateOnIntegerOverflow off + } + Block { + BlockType ComplexToRealImag + Name "Complex to\nReal-Imag" + SID "2149:11671" + Ports [1, 2] + Position [70, 35, 140, 110] + ShowName off + Output "Real and imag" + } + Block { + BlockType Constant + Name "Constant" + SID "2149:11683" + Position [315, 120, 345, 150] + ShowName off + Value "0" + SampleTime "-1" + } + Block { + BlockType Product + Name "Divide" + SID "2149:11672" + Ports [2, 1] + Position [210, 13, 230, 117] + ShowName off + Inputs "*/" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Switch + Name "Switch" + SID "2149:11684" + Position [365, 47, 415, 153] + ShowName off + Criteria "u2 > Threshold" + InputSameDT off + SaturateOnIntegerOverflow off + } + Block { + BlockType Trigonometry + Name "Trigonometric\nFunction" + SID "2149:11673" + Ports [1, 1] + Position [260, 43, 305, 87] + ShowName off + Operator "atan" + } + Block { + BlockType Outport + Name "carr_error" + SID "2149:11674" + Position [440, 93, 470, 107] + IconDisplay "Port number" + } + Line { + SrcBlock "Abs" + SrcPort 1 + Points [20, 0; 0, -30] + DstBlock "Switch" + DstPort 2 + } + Line { + SrcBlock "Trigonometric\nFunction" + SrcPort 1 + DstBlock "Switch" + DstPort 1 + } + Line { + SrcBlock "Switch" + SrcPort 1 + DstBlock "carr_error" + DstPort 1 + } + Line { + SrcBlock "Constant" + SrcPort 1 + DstBlock "Switch" + DstPort 3 + } + Line { + SrcBlock "Complex to\nReal-Imag" + SrcPort 2 + Points [20, 0; 0, -50] + DstBlock "Divide" + DstPort 1 + } + Line { + SrcBlock "Complex to\nReal-Imag" + SrcPort 1 + Points [35, 0; 0, 35] + Branch { + DstBlock "Divide" + DstPort 2 + } + Branch { + Points [0, 40] + DstBlock "Abs" + DstPort 1 + } + } + Line { + SrcBlock "Divide" + SrcPort 1 + DstBlock "Trigonometric\nFunction" + DstPort 1 + } + Line { + SrcBlock "P" + SrcPort 1 + DstBlock "Complex to\nReal-Imag" + DstPort 1 + } + } + } + Block { + BlockType Sum + Name "Subtract" + SID "2150" + Ports [2, 1] + Position [575, 187, 605, 218] + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Switch + Name "Switch" + SID "2151" + Position [560, 62, 610, 168] + ShowName off + Threshold "1" + InputSameDT off + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "[rad/s] to [Hz]" + SID "2152" + Position [215, 34, 270, 66] + ShowName off + Gain "1/(2*pi)" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "carr_nco" + SID "2153" + Position [655, 108, 685, 122] + IconDisplay "Port number" + } + Block { + BlockType Outport + Name "carrier_doppler_Hz" + SID "2154" + Position [665, 198, 695, 212] + Port "2" + IconDisplay "Port number" + } + Line { + SrcBlock "PLL discriminator" + SrcPort 1 + DstBlock "[rad/s] to [Hz]" + DstPort 1 + } + Line { + SrcBlock "P" + SrcPort 1 + DstBlock "PLL discriminator" + DstPort 1 + } + Line { + SrcBlock "enable_tracking" + SrcPort 1 + Points [35, 0] + Branch { + Points [260, 0; 0, -50] + DstBlock "Switch" + DstPort 2 + } + Branch { + Points [0, -60] + DstBlock "PLL Filter" + DstPort 2 + } + } + Line { + SrcBlock "PLL Filter" + SrcPort 1 + Points [20, 0] + Branch { + Points [0, 115] + DstBlock "Subtract" + DstPort 1 + } + Branch { + DstBlock "Switch" + DstPort 1 + } + } + Line { + SrcBlock "d_acq_carrier_doppler_Hz" + SrcPort 1 + DstBlock "Subtract" + DstPort 2 + } + Line { + SrcBlock "Subtract" + SrcPort 1 + DstBlock "carrier_doppler_Hz" + DstPort 1 + } + Line { + SrcBlock "Switch" + SrcPort 1 + DstBlock "carr_nco" + DstPort 1 + } + Line { + SrcBlock "Constant" + SrcPort 1 + DstBlock "Switch" + DstPort 3 + } + Line { + SrcBlock "[rad/s] to [Hz]" + SrcPort 1 + DstBlock "PLL Filter" + DstPort 1 + } + } + } + Block { + BlockType SubSystem + Name "Code Tracking\n(DLL)" + SID "2155" + Ports [5, 1] + Position [450, 44, 605, 426] + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "Code Tracking\n(DLL)" + Location [514, 607, 1002, 858] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "vE" + SID "2156" + Position [25, 23, 55, 37] + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "E" + SID "2157" + Position [25, 58, 55, 72] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "L" + SID "2158" + Position [25, 93, 55, 107] + Port "3" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "vL" + SID "2159" + Position [25, 128, 55, 142] + Port "4" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "enable_tracking" + SID "2160" + Position [25, 173, 55, 187] + Port "5" + IconDisplay "Port number" + } + Block { + BlockType SubSystem + Name "DLL Filter" + SID "2161" + Ports [2, 1] + Position [260, 36, 405, 229] + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "DLL Filter" + Location [158, 107, 1310, 563] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "code_error" + SID "2162" + Position [30, 13, 60, 27] + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "enable_tracking" + SID "2163" + Position [30, 73, 60, 87] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Constant + Name "2*zeta" + SID "2164" + Position [300, 284, 350, 316] + Value "2*zeta_DLL" + SampleTime "-1" + } + Block { + BlockType Sum + Name "Add" + SID "2165" + Ports [3, 1] + Position [935, 141, 965, 279] + ShowName off + Inputs "+++" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Constant + Name "Constant" + SID "2166" + Position [720, 155, 750, 185] + ShowName off + Value "0" + SampleTime "-1" + } + Block { + BlockType Constant + Name "Constant2" + SID "2167" + Position [775, 350, 805, 380] + ShowName off + Value "0" + SampleTime "-1" + } + Block { + BlockType Constant + Name "Constant3" + SID "2168" + Position [440, 100, 470, 130] + ShowName off + Value "0" + SampleTime "-1" + } + Block { + BlockType Reference + Name "Delay" + SID "2169" + Ports [1, 1] + Position [955, 293, 985, 327] + BlockMirror on + NamePlacement "alternate" + ShowName off + LibraryVersion "1.310" + UserDataPersistent on + UserData "DataTag2" + SourceBlock "simulink/Discrete/Integer Delay" + SourceType "Integer Delay" + NumDelays "1" + InputProcessing "Inherited" + vinit "0.0" + samptime "-1" + } + Block { + BlockType Reference + Name "Delay2" + SID "2170" + Ports [1, 1] + Position [575, 63, 605, 97] + NamePlacement "alternate" + ShowName off + LibraryVersion "1.310" + UserDataPersistent on + UserData "DataTag3" + SourceBlock "simulink/Discrete/Integer Delay" + SourceType "Integer Delay" + NumDelays "1" + InputProcessing "Inherited" + vinit "0.0" + samptime "-1" + } + Block { + BlockType Product + Name "Divide" + SID "2171" + Ports [2, 1] + Position [370, 170, 405, 270] + ShowName off + Inputs "*/" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + Port { + PortNumber 1 + Name "Tau1" + RTWStorageClass "Auto" + DataLoggingNameMode "SignalName" + } + } + Block { + BlockType Product + Name "Divide2" + SID "2172" + Ports [2, 1] + Position [370, 275, 405, 375] + ShowName off + Inputs "*/" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + Port { + PortNumber 1 + Name "Tau2" + RTWStorageClass "Auto" + DataLoggingNameMode "SignalName" + } + } + Block { + BlockType Product + Name "Divide4" + SID "2173" + Ports [2, 1] + Position [545, 145, 580, 245] + ShowName off + Inputs "*/" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Divide5" + SID "2174" + Ports [2, 1] + Position [545, 255, 580, 355] + ShowName off + Inputs "*/" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product1" + SID "2175" + Ports [2, 1] + Position [265, 225, 295, 265] + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product2" + SID "2176" + Ports [2, 1] + Position [845, 106, 875, 224] + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product3" + SID "2177" + Ports [2, 1] + Position [685, 274, 715, 316] + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Subtract" + SID "2178" + Ports [2, 1] + Position [685, 35, 710, 95] + ShowName off + Inputs "+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Switch + Name "Switch1" + SID "2179" + Position [485, 27, 535, 133] + ShowName off + Threshold "1" + InputSameDT off + SaturateOnIntegerOverflow off + } + Block { + BlockType Switch + Name "Switch2" + SID "2180" + Position [825, 277, 875, 383] + ShowName off + Threshold "1" + InputSameDT off + SaturateOnIntegerOverflow off + } + Block { + BlockType Switch + Name "Switch4" + SID "2181" + Position [765, 82, 815, 188] + ShowName off + Threshold "1" + InputSameDT off + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "Wn" + SID "2182" + Position [170, 227, 215, 263] + Gain "(8*zeta_DLL)/(1+(4*(zeta_DLL)^2))" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Constant + Name "d_pdi_code" + SID "2183" + Position [475, 264, 525, 296] + Value "d_pdi_code" + SampleTime "-1" + } + Block { + BlockType Constant + Name "k" + SID "2184" + Position [300, 179, 350, 211] + Value "k_DLL" + SampleTime "-1" + } + Block { + BlockType Constant + Name "lbw" + SID "2185" + Position [100, 229, 150, 261] + Value "B_DLL" + SampleTime "-1" + } + Block { + BlockType Outport + Name "code_nco" + SID "2186" + Position [1040, 203, 1070, 217] + IconDisplay "Port number" + } + Line { + SrcBlock "d_pdi_code" + SrcPort 1 + DstBlock "Divide5" + DstPort 1 + } + Line { + SrcBlock "Divide5" + SrcPort 1 + DstBlock "Product3" + DstPort 2 + } + Line { + SrcBlock "Add" + SrcPort 1 + Points [45, 0] + Branch { + DstBlock "code_nco" + DstPort 1 + } + Branch { + Points [0, 100] + DstBlock "Delay" + DstPort 1 + } + } + Line { + SrcBlock "Product2" + SrcPort 1 + DstBlock "Add" + DstPort 1 + } + Line { + SrcBlock "Divide4" + SrcPort 1 + DstBlock "Product2" + DstPort 2 + } + Line { + SrcBlock "code_error" + SrcPort 1 + Points [395, 0] + Branch { + Points [175, 0; 0, 30] + Branch { + Points [0, 235] + DstBlock "Product3" + DstPort 1 + } + Branch { + DstBlock "Subtract" + DstPort 1 + } + } + Branch { + Points [0, 25] + DstBlock "Switch1" + DstPort 1 + } + } + Line { + Name "Tau2" + Labels [0, 0] + SrcBlock "Divide2" + SrcPort 1 + Points [35, 0; 0, -155] + DstBlock "Divide4" + DstPort 1 + } + Line { + SrcBlock "2*zeta" + SrcPort 1 + DstBlock "Divide2" + DstPort 1 + } + Line { + SrcBlock "Product1" + SrcPort 1 + DstBlock "Divide" + DstPort 2 + } + Line { + SrcBlock "k" + SrcPort 1 + DstBlock "Divide" + DstPort 1 + } + Line { + Name "Tau1" + Labels [0, 0] + SrcBlock "Divide" + SrcPort 1 + Points [55, 0] + Branch { + Points [0, 110] + DstBlock "Divide5" + DstPort 2 + } + Branch { + DstBlock "Divide4" + DstPort 2 + } + } + Line { + Labels [0, 0] + SrcBlock "lbw" + SrcPort 1 + DstBlock "Wn" + DstPort 1 + } + Line { + SrcBlock "Wn" + SrcPort 1 + Points [15, 0] + Branch { + Points [10, 0] + Branch { + Points [0, 10] + DstBlock "Product1" + DstPort 2 + } + Branch { + Points [0, -10] + DstBlock "Product1" + DstPort 1 + } + } + Branch { + Points [0, 105] + DstBlock "Divide2" + DstPort 2 + } + } + Line { + SrcBlock "Delay" + SrcPort 1 + Points [-30, 0] + DstBlock "Add" + DstPort 3 + } + Line { + SrcBlock "Subtract" + SrcPort 1 + Points [20, 0; 0, 35] + DstBlock "Switch4" + DstPort 1 + } + Line { + SrcBlock "Switch4" + SrcPort 1 + DstBlock "Product2" + DstPort 1 + } + Line { + SrcBlock "Product3" + SrcPort 1 + DstBlock "Switch2" + DstPort 1 + } + Line { + SrcBlock "Switch2" + SrcPort 1 + Points [20, 0; 0, -120] + DstBlock "Add" + DstPort 2 + } + Line { + SrcBlock "Constant2" + SrcPort 1 + DstBlock "Switch2" + DstPort 3 + } + Line { + SrcBlock "Delay2" + SrcPort 1 + DstBlock "Subtract" + DstPort 2 + } + Line { + SrcBlock "Constant3" + SrcPort 1 + DstBlock "Switch1" + DstPort 3 + } + Line { + SrcBlock "enable_tracking" + SrcPort 1 + Points [25, 0] + Branch { + Points [0, 0; 335, 0] + Branch { + Points [0, 55] + DstBlock "Switch4" + DstPort 2 + } + Branch { + DstBlock "Switch1" + DstPort 2 + } + } + Branch { + Points [0, 300; 660, 0; 0, -50] + DstBlock "Switch2" + DstPort 2 + } + } + Line { + SrcBlock "Constant" + SrcPort 1 + DstBlock "Switch4" + DstPort 3 + } + Line { + SrcBlock "Switch1" + SrcPort 1 + DstBlock "Delay2" + DstPort 1 + } + Annotation { + Position [998, 349] + } + Annotation { + Position [983, 334] + } + } + } + Block { + BlockType SubSystem + Name "DLL discriminator" + SID "2187" + Ports [4, 1] + Position [80, 13, 225, 152] + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "DLL discriminator" + Location [272, 238, 794, 581] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "vE" + SID "2188" + Position [20, 23, 50, 37] + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "E" + SID "2189" + Position [15, 108, 45, 122] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "L" + SID "2190" + Position [15, 223, 45, 237] + Port "3" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "vL" + SID "2191" + Position [15, 293, 45, 307] + Port "4" + IconDisplay "Port number" + } + Block { + BlockType Math + Name "E power" + SID "2192" + Ports [1, 1] + Position [95, 100, 125, 130] + Operator "magnitude^2" + } + Block { + BlockType Math + Name "L power" + SID "2193" + Ports [1, 1] + Position [90, 215, 120, 245] + Operator "magnitude^2" + } + Block { + BlockType Sqrt + Name "Sqrt" + SID "2194" + Position [215, 65, 245, 95] + ShowName off + } + Block { + BlockType Sqrt + Name "Sqrt1" + SID "2195" + Position [220, 250, 250, 280] + ShowName off + } + Block { + BlockType Sum + Name "Sum" + SID "2196" + Ports [2, 1] + Position [260, 145, 280, 165] + ShowName off + IconShape "round" + Inputs "+|-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + } + Block { + BlockType Sum + Name "Sum1" + SID "2197" + Ports [2, 1] + Position [320, 180, 340, 200] + ShowName off + IconShape "round" + Inputs "+|+" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + } + Block { + BlockType Sum + Name "Sum2" + SID "2198" + Ports [2, 1] + Position [160, 70, 180, 90] + ShowName off + IconShape "round" + Inputs "+|+" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + } + Block { + BlockType Sum + Name "Sum3" + SID "2199" + Ports [2, 1] + Position [155, 255, 175, 275] + ShowName off + IconShape "round" + Inputs "+|+" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + } + Block { + BlockType Product + Name "vE Normalisation" + SID "2200" + Ports [2, 1] + Position [390, 138, 435, 207] + NamePlacement "alternate" + ShowName off + Inputs "*/" + InputSameDT off + RndMeth "Floor" + } + Block { + BlockType Math + Name "vE power" + SID "2201" + Ports [1, 1] + Position [95, 15, 125, 45] + Operator "magnitude^2" + } + Block { + BlockType Math + Name "vL power" + SID "2202" + Ports [1, 1] + Position [90, 285, 120, 315] + Operator "magnitude^2" + } + Block { + BlockType Outport + Name "code_error" + SID "2203" + Position [465, 168, 495, 182] + IconDisplay "Port number" + } + Line { + SrcBlock "vL power" + SrcPort 1 + Points [40, 0] + DstBlock "Sum3" + DstPort 2 + } + Line { + SrcBlock "Sum3" + SrcPort 1 + DstBlock "Sqrt1" + DstPort 1 + } + Line { + SrcBlock "L power" + SrcPort 1 + Points [40, 0] + DstBlock "Sum3" + DstPort 1 + } + Line { + SrcBlock "E power" + SrcPort 1 + Points [40, 0] + DstBlock "Sum2" + DstPort 2 + } + Line { + SrcBlock "Sum2" + SrcPort 1 + DstBlock "Sqrt" + DstPort 1 + } + Line { + SrcBlock "vE Normalisation" + SrcPort 1 + DstBlock "code_error" + DstPort 1 + } + Line { + SrcBlock "Sum1" + SrcPort 1 + DstBlock "vE Normalisation" + DstPort 2 + } + Line { + SrcBlock "Sum" + SrcPort 1 + DstBlock "vE Normalisation" + DstPort 1 + } + Line { + SrcBlock "vL" + SrcPort 1 + DstBlock "vL power" + DstPort 1 + } + Line { + SrcBlock "vE" + SrcPort 1 + DstBlock "vE power" + DstPort 1 + } + Line { + SrcBlock "vE power" + SrcPort 1 + Points [40, 0] + DstBlock "Sum2" + DstPort 1 + } + Line { + SrcBlock "L" + SrcPort 1 + DstBlock "L power" + DstPort 1 + } + Line { + SrcBlock "E" + SrcPort 1 + DstBlock "E power" + DstPort 1 + } + Line { + SrcBlock "Sqrt" + SrcPort 1 + Points [20, 0] + Branch { + Points [60, 0] + DstBlock "Sum1" + DstPort 1 + } + Branch { + DstBlock "Sum" + DstPort 1 + } + } + Line { + SrcBlock "Sqrt1" + SrcPort 1 + Points [15, 0] + Branch { + Points [60, 0] + DstBlock "Sum1" + DstPort 2 + } + Branch { + DstBlock "Sum" + DstPort 2 + } + } + } + } + Block { + BlockType Outport + Name "code_nco" + SID "2204" + Position [435, 128, 465, 142] + IconDisplay "Port number" + } + Line { + SrcBlock "vL" + SrcPort 1 + DstBlock "DLL discriminator" + DstPort 4 + } + Line { + SrcBlock "vE" + SrcPort 1 + DstBlock "DLL discriminator" + DstPort 1 + } + Line { + SrcBlock "E" + SrcPort 1 + DstBlock "DLL discriminator" + DstPort 2 + } + Line { + SrcBlock "L" + SrcPort 1 + DstBlock "DLL discriminator" + DstPort 3 + } + Line { + SrcBlock "DLL Filter" + SrcPort 1 + DstBlock "code_nco" + DstPort 1 + } + Line { + SrcBlock "DLL discriminator" + SrcPort 1 + DstBlock "DLL Filter" + DstPort 1 + } + Line { + SrcBlock "enable_tracking" + SrcPort 1 + DstBlock "DLL Filter" + DstPort 2 + } + } + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion1" + SID "2205" + Position [640, 215, 680, 255] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion2" + SID "2206" + Position [200, 140, 240, 180] + ShowName off + OutDataTypeStr "double" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion3" + SID "2207" + Position [640, 620, 680, 660] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion4" + SID "2208" + Position [640, 540, 680, 580] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion5" + SID "2209" + Position [200, 215, 240, 255] + ShowName off + OutDataTypeStr "double" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion6" + SID "2210" + Position [180, 530, 220, 570] + ShowName off + OutDataTypeStr "double" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion7" + SID "2211" + Position [200, 65, 240, 105] + ShowName off + OutDataTypeStr "double" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion8" + SID "2212" + Position [200, 290, 240, 330] + ShowName off + OutDataTypeStr "double" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion9" + SID "2213" + Position [180, 580, 220, 620] + ShowName off + OutDataTypeStr "double" + } + Block { + BlockType Mux + Name "Mux" + SID "2214" + Ports [5, 1] + Position [360, 359, 365, 491] + ShowName off + Inputs "5" + DisplayOption "bar" + } + Block { + BlockType RealImagToComplex + Name "Real-Imag to\nComplex" + SID "2215" + Ports [2, 1] + Position [125, 121, 160, 194] + ShowName off + Input "Real and imag" + } + Block { + BlockType RealImagToComplex + Name "Real-Imag to\nComplex1" + SID "2216" + Ports [2, 1] + Position [125, 196, 160, 269] + ShowName off + Input "Real and imag" + } + Block { + BlockType RealImagToComplex + Name "Real-Imag to\nComplex2" + SID "2217" + Ports [2, 1] + Position [125, 511, 160, 584] + ShowName off + Input "Real and imag" + } + Block { + BlockType RealImagToComplex + Name "Real-Imag to\nComplex3" + SID "2218" + Ports [2, 1] + Position [125, 46, 160, 119] + ShowName off + Input "Real and imag" + } + Block { + BlockType RealImagToComplex + Name "Real-Imag to\nComplex4" + SID "2219" + Ports [2, 1] + Position [125, 271, 160, 344] + ShowName off + Input "Real and imag" + } + Block { + BlockType Outport + Name "control_id_" + SID "2220" + Position [725, 13, 755, 27] + IconDisplay "Port number" + } + Block { + BlockType Outport + Name "code_nco" + SID "2221" + Position [725, 228, 755, 242] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Outport + Name "carr_nco" + SID "2222" + Position [725, 553, 755, 567] + Port "3" + IconDisplay "Port number" + } + Block { + BlockType Outport + Name "carrier_doppler_Hz" + SID "2223" + Position [725, 633, 755, 647] + Port "4" + IconDisplay "Port number" + } + Block { + BlockType Outport + Name "EPL Scope" + SID "2224" + Position [385, 418, 415, 432] + Port "5" + IconDisplay "Port number" + } + Line { + SrcBlock "Data Type \nConversion8" + SrcPort 1 + Points [10, 0] + Branch { + DstBlock "Code Tracking\n(DLL)" + DstPort 4 + } + Branch { + Points [0, 165] + DstBlock "Abs3" + DstPort 1 + } + } + Line { + SrcBlock "Data Type \nConversion7" + SrcPort 1 + Points [50, 0] + Branch { + DstBlock "Code Tracking\n(DLL)" + DstPort 1 + } + Branch { + DstBlock "Abs4" + DstPort 1 + } + } + Line { + SrcBlock "d_vL_Q" + SrcPort 1 + DstBlock "Real-Imag to\nComplex4" + DstPort 2 + } + Line { + SrcBlock "d_vL_I" + SrcPort 1 + DstBlock "Real-Imag to\nComplex4" + DstPort 1 + } + Line { + SrcBlock "Real-Imag to\nComplex4" + SrcPort 1 + DstBlock "Data Type \nConversion8" + DstPort 1 + } + Line { + SrcBlock "d_vE_Q" + SrcPort 1 + DstBlock "Real-Imag to\nComplex3" + DstPort 2 + } + Line { + SrcBlock "d_vE_I" + SrcPort 1 + DstBlock "Real-Imag to\nComplex3" + DstPort 1 + } + Line { + SrcBlock "Real-Imag to\nComplex3" + SrcPort 1 + DstBlock "Data Type \nConversion7" + DstPort 1 + } + Line { + SrcBlock "Mux" + SrcPort 1 + DstBlock "EPL Scope" + DstPort 1 + } + Line { + SrcBlock "enable_tracking" + SrcPort 1 + Points [120, 0] + Branch { + DstBlock "Carrier Tracking (PLL)" + DstPort 3 + } + Branch { + Points [0, 60; 225, 0] + DstBlock "Code Tracking\n(DLL)" + DstPort 5 + } + } + Line { + SrcBlock "Data Type \nConversion3" + SrcPort 1 + DstBlock "carrier_doppler_Hz" + DstPort 1 + } + Line { + SrcBlock "d_acq_carrier_doppler_Hz" + SrcPort 1 + DstBlock "Data Type \nConversion9" + DstPort 1 + } + Line { + SrcBlock "Data Type \nConversion6" + SrcPort 1 + Points [5, 0] + Branch { + DstBlock "Carrier Tracking (PLL)" + DstPort 1 + } + Branch { + Points [0, 0; 0, -125] + DstBlock "Abs1" + DstPort 1 + } + } + Line { + SrcBlock "Data Type \nConversion5" + SrcPort 1 + Points [20, 0] + Branch { + Points [0, 215] + DstBlock "Abs" + DstPort 1 + } + Branch { + DstBlock "Code Tracking\n(DLL)" + DstPort 3 + } + } + Line { + SrcBlock "Data Type \nConversion2" + SrcPort 1 + Points [40, 0] + Branch { + Points [0, 240] + DstBlock "Abs2" + DstPort 1 + } + Branch { + DstBlock "Code Tracking\n(DLL)" + DstPort 2 + } + } + Line { + SrcBlock "d_P_Q" + SrcPort 1 + DstBlock "Real-Imag to\nComplex2" + DstPort 2 + } + Line { + SrcBlock "d_P_I" + SrcPort 1 + DstBlock "Real-Imag to\nComplex2" + DstPort 1 + } + Line { + SrcBlock "d_L_Q" + SrcPort 1 + DstBlock "Real-Imag to\nComplex1" + DstPort 2 + } + Line { + SrcBlock "d_L_I" + SrcPort 1 + DstBlock "Real-Imag to\nComplex1" + DstPort 1 + } + Line { + SrcBlock "control_id" + SrcPort 1 + DstBlock "control_id_" + DstPort 1 + } + Line { + SrcBlock "Data Type \nConversion4" + SrcPort 1 + DstBlock "carr_nco" + DstPort 1 + } + Line { + SrcBlock "Data Type \nConversion1" + SrcPort 1 + DstBlock "code_nco" + DstPort 1 + } + Line { + SrcBlock "d_E_Q" + SrcPort 1 + DstBlock "Real-Imag to\nComplex" + DstPort 2 + } + Line { + SrcBlock "d_E_I" + SrcPort 1 + DstBlock "Real-Imag to\nComplex" + DstPort 1 + } + Line { + SrcBlock "Real-Imag to\nComplex2" + SrcPort 1 + DstBlock "Data Type \nConversion6" + DstPort 1 + } + Line { + SrcBlock "Real-Imag to\nComplex1" + SrcPort 1 + DstBlock "Data Type \nConversion5" + DstPort 1 + } + Line { + SrcBlock "Carrier Tracking (PLL)" + SrcPort 1 + DstBlock "Data Type \nConversion4" + DstPort 1 + } + Line { + SrcBlock "Real-Imag to\nComplex" + SrcPort 1 + DstBlock "Data Type \nConversion2" + DstPort 1 + } + Line { + SrcBlock "Code Tracking\n(DLL)" + SrcPort 1 + DstBlock "Data Type \nConversion1" + DstPort 1 + } + Line { + SrcBlock "Carrier Tracking (PLL)" + SrcPort 2 + DstBlock "Data Type \nConversion3" + DstPort 1 + } + Line { + SrcBlock "Abs4" + SrcPort 1 + DstBlock "Mux" + DstPort 1 + } + Line { + SrcBlock "Abs2" + SrcPort 1 + DstBlock "Mux" + DstPort 2 + } + Line { + SrcBlock "Abs1" + SrcPort 1 + DstBlock "Mux" + DstPort 3 + } + Line { + SrcBlock "Abs" + SrcPort 1 + DstBlock "Mux" + DstPort 4 + } + Line { + SrcBlock "Abs3" + SrcPort 1 + DstBlock "Mux" + DstPort 5 + } + Line { + SrcBlock "Data Type \nConversion9" + SrcPort 1 + DstBlock "Carrier Tracking (PLL)" + DstPort 2 + } + } + } + Block { + BlockType SubSystem + Name "gnss_sdr_galileo_e1_tcp_connector_tracking_rx" + SID "2088" + Ports [0, 13] + Position [25, 19, 205, 391] + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "gnss_sdr_galileo_e1_tcp_connector_tracking_rx" + Location [2, 82, 1670, 1004] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "41" + Block { + BlockType Reference + Name "Multiport\nSelector" + SID "2225" + Ports [1, 52] + Position [180, 19, 355, 2201] + ShowName off + LibraryVersion "1.462" + SourceBlock "dspindex/Multiport\nSelector" + SourceType "Multiport Selector" + rowsOrCols "Rows" + idxCellArray "{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33," + "34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52}" + idxErrMode "Clip Index" + } + Block { + BlockType Reference + Name "RX" + SID "2226" + Ports [0, 1] + Position [15, 1046, 150, 1164] + LibraryVersion "1.84" + DialogController "instrumentcreatedialog" + DialogControllerArgs "DataTag4" + SourceBlock "instrumentlib/TCP//IP Receive" + SourceType "TCP/IP Receive" + Host "84.88.61.86" + Port "2070" + DataSize "52" + EnableBlockingMode on + Timeout "5" + SampleTime "-1" + DataType "uint8" + ByteOrder "BigEndian" + } + Block { + BlockType SubSystem + Name "Subsystem" + SID "2227" + Ports [4, 1] + Position [525, 536, 630, 704] + ShowName off + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "Subsystem" + Location [528, 347, 1021, 603] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "2228" + Position [25, 178, 55, 192] + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "2229" + Position [25, 133, 55, 147] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In3" + SID "2230" + Position [25, 88, 55, 102] + Port "3" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In4" + SID "2231" + Position [25, 43, 55, 57] + Port "4" + IconDisplay "Port number" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion1" + SID "2232" + Position [100, 75, 140, 115] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion2" + SID "2233" + Position [100, 120, 140, 160] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion3" + SID "2234" + Position [100, 165, 140, 205] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion4" + SID "2235" + Position [100, 30, 140, 70] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion5" + SID "2236" + Position [365, 100, 405, 140] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType SubSystem + Name "hex2float" + SID "2237" + Ports [4, 1] + Position [190, 25, 320, 210] + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "hex2float" + Location [13, 125, 1281, 839] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "2238" + Position [50, 48, 80, 62] + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "2239" + Position [25, 248, 55, 262] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In3" + SID "2240" + Position [50, 433, 80, 447] + Port "3" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In4" + SID "2241" + Position [50, 528, 80, 542] + Port "4" + IconDisplay "Port number" + } + Block { + BlockType Reference + Name "Bitwise\nOperator" + SID "2242" + Ports [1, 1] + Position [375, 161, 415, 199] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('01111111')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator1" + SID "2243" + Ports [1, 1] + Position [255, 251, 295, 289] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('10000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator2" + SID "2244" + Ports [1, 1] + Position [285, 26, 325, 64] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('10000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator3" + SID "2245" + Ports [1, 1] + Position [255, 336, 295, 374] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('01111111')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Constant + Name "Constant4" + SID "2246" + Position [855, 280, 885, 310] + Value "127" + } + Block { + BlockType Constant + Name "Constant5" + SID "2247" + Position [650, 655, 740, 685] + Value "8388608" + } + Block { + BlockType Constant + Name "Constant7" + SID "2248" + Position [740, 45, 770, 75] + Value "-1" + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion" + SID "2249" + Position [105, 38, 180, 72] + OutDataTypeStr "uint8" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion1" + SID "2250" + Position [105, 238, 180, 272] + OutDataTypeStr "uint8" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion2" + SID "2251" + Position [110, 333, 185, 367] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion3" + SID "2252" + Position [105, 423, 180, 457] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion4" + SID "2253" + Position [105, 518, 180, 552] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion5" + SID "2254" + Position [800, 653, 875, 687] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion7" + SID "2255" + Position [670, 118, 745, 152] + OutDataTypeStr "double" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Display + Name "Display3" + SID "2256" + Ports [1] + Position [460, 162, 550, 188] + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "2257" + Ports [1] + Position [670, 217, 760, 243] + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Exponent" + SID "2258" + Ports [1] + Position [715, 282, 805, 308] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Mantissa" + SID "2259" + Ports [1] + Position [1015, 558, 1295, 592] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction" + SID "2260" + Ports [2, 1] + Position [825, 102, 855, 133] + Operator "pow" + } + Block { + BlockType Product + Name "Product" + SID "2261" + Ports [2, 1] + Position [1225, 277, 1255, 308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Reference + Name "Shift\nArithmetic" + SID "2262" + Ports [1, 1] + Position [565, 215, 645, 255] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-1" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic1" + SID "2263" + Ports [1, 1] + Position [335, 255, 415, 295] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "7" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic2" + SID "2264" + Ports [1, 1] + Position [360, 25, 440, 65] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "7" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic3" + SID "2265" + Ports [1, 1] + Position [370, 335, 450, 375] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-16" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic4" + SID "2266" + Ports [1, 1] + Position [375, 420, 455, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-8" + nBinPtShiftRight "0" + } + Block { + BlockType Display + Name "Sign" + SID "2267" + Ports [1] + Position [480, 32, 570, 58] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType SubSystem + Name "Subsystem" + SID "2268" + Ports [2, 1] + Position [1125, 350, 1165, 410] + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "Subsystem" + Location [2, 82, 1653, 1004] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "2269" + Position [25, 235, 55, 250] + BlockRotation 270 + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "2270" + Position [220, 358, 250, 372] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Reference + Name "Bitwise\nOperator1" + SID "2271" + Ports [1, 1] + Position [410, 241, 450, 279] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0100000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator10" + SID "2272" + Ports [1, 1] + Position [425, 1086, 465, 1124] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000001000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator11" + SID "2273" + Ports [1, 1] + Position [425, 1266, 465, 1304] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000100000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator12" + SID "2274" + Ports [1, 1] + Position [425, 1446, 465, 1484] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000010000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator13" + SID "2275" + Ports [1, 1] + Position [425, 1636, 465, 1674] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000001000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator14" + SID "2276" + Ports [1, 1] + Position [425, 1836, 465, 1874] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000100000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator15" + SID "2277" + Ports [1, 1] + Position [425, 2046, 465, 2084] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000010000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator16" + SID "2278" + Ports [1, 1] + Position [425, 2276, 465, 2314] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000001000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator17" + SID "2279" + Ports [1, 1] + Position [425, 2521, 465, 2559] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000100000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator18" + SID "2280" + Ports [1, 1] + Position [425, 2776, 465, 2814] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000010000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator19" + SID "2281" + Ports [1, 1] + Position [425, 3041, 465, 3079] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000001000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator20" + SID "2282" + Ports [1, 1] + Position [425, 3316, 465, 3354] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000100000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator21" + SID "2283" + Ports [1, 1] + Position [425, 3596, 465, 3634] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000010000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator22" + SID "2284" + Ports [1, 1] + Position [425, 3886, 465, 3924] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000001000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator23" + SID "2285" + Ports [1, 1] + Position [425, 4181, 465, 4219] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000100000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator24" + SID "2286" + Ports [1, 1] + Position [425, 4486, 465, 4524] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000010000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator25" + SID "2287" + Ports [1, 1] + Position [425, 4796, 465, 4834] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000001000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator26" + SID "2288" + Ports [1, 1] + Position [430, 5111, 470, 5149] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000100')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator27" + SID "2289" + Ports [1, 1] + Position [430, 5431, 470, 5469] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000010')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator28" + SID "2290" + Ports [1, 1] + Position [430, 5756, 470, 5794] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000001')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator6" + SID "2291" + Ports [1, 1] + Position [415, 426, 455, 464] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0010000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator7" + SID "2292" + Ports [1, 1] + Position [415, 576, 455, 614] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0001000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator8" + SID "2293" + Ports [1, 1] + Position [420, 736, 460, 774] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000100000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator9" + SID "2294" + Ports [1, 1] + Position [425, 906, 465, 944] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000010000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Compare\nTo Zero1" + SID "2295" + Ports [1, 1] + Position [480, 245, 510, 275] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero10" + SID "2296" + Ports [1, 1] + Position [495, 1840, 525, 1870] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero11" + SID "2297" + Ports [1, 1] + Position [495, 2050, 525, 2080] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero12" + SID "2298" + Ports [1, 1] + Position [495, 2280, 525, 2310] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero13" + SID "2299" + Ports [1, 1] + Position [495, 2525, 525, 2555] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero14" + SID "2300" + Ports [1, 1] + Position [495, 2780, 525, 2810] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero15" + SID "2301" + Ports [1, 1] + Position [495, 3045, 525, 3075] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero16" + SID "2302" + Ports [1, 1] + Position [495, 3320, 525, 3350] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero17" + SID "2303" + Ports [1, 1] + Position [495, 3600, 525, 3630] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero18" + SID "2304" + Ports [1, 1] + Position [495, 3890, 525, 3920] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero19" + SID "2305" + Ports [1, 1] + Position [495, 4185, 525, 4215] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero2" + SID "2306" + Ports [1, 1] + Position [485, 430, 515, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero20" + SID "2307" + Ports [1, 1] + Position [495, 4490, 525, 4520] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero21" + SID "2308" + Ports [1, 1] + Position [495, 4800, 525, 4830] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero22" + SID "2309" + Ports [1, 1] + Position [500, 5115, 530, 5145] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero23" + SID "2310" + Ports [1, 1] + Position [500, 5435, 530, 5465] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero24" + SID "2311" + Ports [1, 1] + Position [500, 5760, 530, 5790] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero3" + SID "2312" + Ports [1, 1] + Position [485, 580, 515, 610] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero4" + SID "2313" + Ports [1, 1] + Position [490, 740, 520, 770] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero5" + SID "2314" + Ports [1, 1] + Position [495, 910, 525, 940] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero6" + SID "2315" + Ports [1, 1] + Position [495, 1090, 525, 1120] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero7" + SID "2316" + Ports [1, 1] + Position [495, 1270, 525, 1300] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero8" + SID "2317" + Ports [1, 1] + Position [495, 1450, 525, 1480] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero9" + SID "2318" + Ports [1, 1] + Position [495, 1640, 525, 1670] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Constant + Name "Constant1" + SID "2319" + Position [360, 145, 390, 175] + Value "2" + } + Block { + BlockType Constant + Name "Constant10" + SID "2320" + Position [365, 480, 395, 510] + Value "2" + } + Block { + BlockType Constant + Name "Constant11" + SID "2321" + Position [335, 550, 365, 580] + } + Block { + BlockType Constant + Name "Constant12" + SID "2322" + Position [370, 640, 400, 670] + Value "2" + } + Block { + BlockType Constant + Name "Constant13" + SID "2323" + Position [340, 710, 370, 740] + } + Block { + BlockType Constant + Name "Constant14" + SID "2324" + Position [375, 810, 405, 840] + Value "2" + } + Block { + BlockType Constant + Name "Constant15" + SID "2325" + Position [345, 880, 375, 910] + } + Block { + BlockType Constant + Name "Constant16" + SID "2326" + Position [375, 990, 405, 1020] + Value "2" + } + Block { + BlockType Constant + Name "Constant17" + SID "2327" + Position [345, 1060, 375, 1090] + } + Block { + BlockType Constant + Name "Constant18" + SID "2328" + Position [375, 1170, 405, 1200] + Value "2" + } + Block { + BlockType Constant + Name "Constant19" + SID "2329" + Position [345, 1240, 375, 1270] + } + Block { + BlockType Constant + Name "Constant2" + SID "2330" + Position [345, 400, 375, 430] + } + Block { + BlockType Constant + Name "Constant20" + SID "2331" + Position [375, 1350, 405, 1380] + Value "2" + } + Block { + BlockType Constant + Name "Constant21" + SID "2332" + Position [345, 1420, 375, 1450] + } + Block { + BlockType Constant + Name "Constant22" + SID "2333" + Position [375, 1540, 405, 1570] + Value "2" + } + Block { + BlockType Constant + Name "Constant23" + SID "2334" + Position [345, 1610, 375, 1640] + } + Block { + BlockType Constant + Name "Constant24" + SID "2335" + Position [375, 1740, 405, 1770] + Value "2" + } + Block { + BlockType Constant + Name "Constant25" + SID "2336" + Position [345, 1810, 375, 1840] + } + Block { + BlockType Constant + Name "Constant26" + SID "2337" + Position [375, 1950, 405, 1980] + Value "2" + } + Block { + BlockType Constant + Name "Constant27" + SID "2338" + Position [345, 2020, 375, 2050] + } + Block { + BlockType Constant + Name "Constant28" + SID "2339" + Position [375, 2180, 405, 2210] + Value "2" + } + Block { + BlockType Constant + Name "Constant29" + SID "2340" + Position [345, 2250, 375, 2280] + } + Block { + BlockType Constant + Name "Constant30" + SID "2341" + Position [375, 2425, 405, 2455] + Value "2" + } + Block { + BlockType Constant + Name "Constant31" + SID "2342" + Position [345, 2495, 375, 2525] + } + Block { + BlockType Constant + Name "Constant32" + SID "2343" + Position [375, 2680, 405, 2710] + Value "2" + } + Block { + BlockType Constant + Name "Constant33" + SID "2344" + Position [345, 2750, 375, 2780] + } + Block { + BlockType Constant + Name "Constant34" + SID "2345" + Position [375, 2945, 405, 2975] + Value "2" + } + Block { + BlockType Constant + Name "Constant35" + SID "2346" + Position [345, 3015, 375, 3045] + } + Block { + BlockType Constant + Name "Constant36" + SID "2347" + Position [375, 3220, 405, 3250] + Value "2" + } + Block { + BlockType Constant + Name "Constant37" + SID "2348" + Position [345, 3290, 375, 3320] + } + Block { + BlockType Constant + Name "Constant38" + SID "2349" + Position [375, 3500, 405, 3530] + Value "2" + } + Block { + BlockType Constant + Name "Constant39" + SID "2350" + Position [345, 3570, 375, 3600] + } + Block { + BlockType Constant + Name "Constant40" + SID "2351" + Position [375, 3790, 405, 3820] + Value "2" + } + Block { + BlockType Constant + Name "Constant41" + SID "2352" + Position [345, 3860, 375, 3890] + } + Block { + BlockType Constant + Name "Constant42" + SID "2353" + Position [375, 4085, 405, 4115] + Value "2" + } + Block { + BlockType Constant + Name "Constant43" + SID "2354" + Position [345, 4155, 375, 4185] + } + Block { + BlockType Constant + Name "Constant44" + SID "2355" + Position [375, 4390, 405, 4420] + Value "2" + } + Block { + BlockType Constant + Name "Constant45" + SID "2356" + Position [345, 4460, 375, 4490] + } + Block { + BlockType Constant + Name "Constant46" + SID "2357" + Position [375, 4700, 405, 4730] + Value "2" + } + Block { + BlockType Constant + Name "Constant47" + SID "2358" + Position [345, 4770, 375, 4800] + } + Block { + BlockType Constant + Name "Constant48" + SID "2359" + Position [380, 5015, 410, 5045] + Value "2" + } + Block { + BlockType Constant + Name "Constant49" + SID "2360" + Position [350, 5085, 380, 5115] + } + Block { + BlockType Constant + Name "Constant50" + SID "2361" + Position [380, 5335, 410, 5365] + Value "2" + } + Block { + BlockType Constant + Name "Constant51" + SID "2362" + Position [350, 5405, 380, 5435] + } + Block { + BlockType Constant + Name "Constant52" + SID "2363" + Position [380, 5660, 410, 5690] + Value "2" + } + Block { + BlockType Constant + Name "Constant53" + SID "2364" + Position [350, 5730, 380, 5760] + } + Block { + BlockType Constant + Name "Constant8" + SID "2365" + Position [365, 330, 395, 360] + Value "2" + } + Block { + BlockType Display + Name "Display1" + SID "2366" + Ports [1] + Position [730, 507, 820, 533] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display2" + SID "2367" + Ports [1] + Position [775, 657, 865, 683] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display3" + SID "2368" + Ports [1] + Position [740, 857, 830, 883] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "2369" + Ports [1] + Position [770, 1057, 860, 1083] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display5" + SID "2370" + Ports [1] + Position [735, 332, 825, 358] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display6" + SID "2371" + Ports [1] + Position [770, 1187, 860, 1213] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display7" + SID "2372" + Ports [1] + Position [640, 197, 730, 223] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display8" + SID "2373" + Ports [1] + Position [490, 317, 580, 343] + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction1" + SID "2374" + Ports [2, 1] + Position [420, 177, 450, 208] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction10" + SID "2375" + Ports [2, 1] + Position [435, 1772, 465, 1803] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction11" + SID "2376" + Ports [2, 1] + Position [435, 1982, 465, 2013] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction12" + SID "2377" + Ports [2, 1] + Position [435, 2212, 465, 2243] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction13" + SID "2378" + Ports [2, 1] + Position [435, 2457, 465, 2488] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction14" + SID "2379" + Ports [2, 1] + Position [435, 2712, 465, 2743] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction15" + SID "2380" + Ports [2, 1] + Position [435, 2977, 465, 3008] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction16" + SID "2381" + Ports [2, 1] + Position [435, 3252, 465, 3283] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction17" + SID "2382" + Ports [2, 1] + Position [435, 3532, 465, 3563] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction18" + SID "2383" + Ports [2, 1] + Position [435, 3822, 465, 3853] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction19" + SID "2384" + Ports [2, 1] + Position [435, 4117, 465, 4148] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction2" + SID "2385" + Ports [2, 1] + Position [425, 362, 455, 393] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction20" + SID "2386" + Ports [2, 1] + Position [435, 4422, 465, 4453] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction21" + SID "2387" + Ports [2, 1] + Position [435, 4732, 465, 4763] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction22" + SID "2388" + Ports [2, 1] + Position [440, 5047, 470, 5078] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction23" + SID "2389" + Ports [2, 1] + Position [440, 5367, 470, 5398] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction24" + SID "2390" + Ports [2, 1] + Position [440, 5692, 470, 5723] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction3" + SID "2391" + Ports [2, 1] + Position [425, 512, 455, 543] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction4" + SID "2392" + Ports [2, 1] + Position [430, 672, 460, 703] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction5" + SID "2393" + Ports [2, 1] + Position [435, 842, 465, 873] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction6" + SID "2394" + Ports [2, 1] + Position [435, 1022, 465, 1053] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction7" + SID "2395" + Ports [2, 1] + Position [435, 1202, 465, 1233] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction8" + SID "2396" + Ports [2, 1] + Position [435, 1382, 465, 1413] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction9" + SID "2397" + Ports [2, 1] + Position [435, 1572, 465, 1603] + Operator "pow" + } + Block { + BlockType Product + Name "Product1" + SID "2398" + Ports [2, 1] + Position [555, 202, 585, 233] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product10" + SID "2399" + Ports [2, 1] + Position [570, 1797, 600, 1828] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product11" + SID "2400" + Ports [2, 1] + Position [570, 2007, 600, 2038] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product12" + SID "2401" + Ports [2, 1] + Position [570, 2237, 600, 2268] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product13" + SID "2402" + Ports [2, 1] + Position [570, 2482, 600, 2513] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product14" + SID "2403" + Ports [2, 1] + Position [570, 2737, 600, 2768] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product15" + SID "2404" + Ports [2, 1] + Position [570, 3002, 600, 3033] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product16" + SID "2405" + Ports [2, 1] + Position [570, 3277, 600, 3308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product17" + SID "2406" + Ports [2, 1] + Position [570, 3557, 600, 3588] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product18" + SID "2407" + Ports [2, 1] + Position [570, 3847, 600, 3878] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product19" + SID "2408" + Ports [2, 1] + Position [570, 4142, 600, 4173] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product2" + SID "2409" + Ports [2, 1] + Position [560, 387, 590, 418] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product20" + SID "2410" + Ports [2, 1] + Position [570, 4447, 600, 4478] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product21" + SID "2411" + Ports [2, 1] + Position [570, 4757, 600, 4788] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product22" + SID "2412" + Ports [2, 1] + Position [575, 5072, 605, 5103] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product23" + SID "2413" + Ports [2, 1] + Position [575, 5392, 605, 5423] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product24" + SID "2414" + Ports [2, 1] + Position [575, 5717, 605, 5748] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product3" + SID "2415" + Ports [2, 1] + Position [560, 537, 590, 568] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product4" + SID "2416" + Ports [2, 1] + Position [565, 697, 595, 728] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product5" + SID "2417" + Ports [2, 1] + Position [570, 867, 600, 898] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product6" + SID "2418" + Ports [2, 1] + Position [570, 1047, 600, 1078] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product7" + SID "2419" + Ports [2, 1] + Position [570, 1227, 600, 1258] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product8" + SID "2420" + Ports [2, 1] + Position [570, 1407, 600, 1438] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product9" + SID "2421" + Ports [2, 1] + Position [570, 1597, 600, 1628] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum1" + SID "2422" + Ports [2, 1] + Position [380, 380, 400, 400] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum10" + SID "2423" + Ports [2, 1] + Position [380, 1400, 400, 1420] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum11" + SID "2424" + Ports [2, 1] + Position [380, 1590, 400, 1610] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum12" + SID "2425" + Ports [2, 1] + Position [380, 1790, 400, 1810] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum13" + SID "2426" + Ports [2, 1] + Position [380, 2000, 400, 2020] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum14" + SID "2427" + Ports [2, 1] + Position [380, 2230, 400, 2250] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum15" + SID "2428" + Ports [2, 1] + Position [380, 2475, 400, 2495] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum16" + SID "2429" + Ports [2, 1] + Position [380, 2730, 400, 2750] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum17" + SID "2430" + Ports [2, 1] + Position [380, 2995, 400, 3015] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum18" + SID "2431" + Ports [2, 1] + Position [380, 3270, 400, 3290] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum19" + SID "2432" + Ports [2, 1] + Position [380, 3550, 400, 3570] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum20" + SID "2433" + Ports [2, 1] + Position [380, 3840, 400, 3860] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum21" + SID "2434" + Ports [2, 1] + Position [380, 4135, 400, 4155] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum22" + SID "2435" + Ports [2, 1] + Position [380, 4440, 400, 4460] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum23" + SID "2436" + Ports [2, 1] + Position [380, 4750, 400, 4770] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum24" + SID "2437" + Ports [2, 1] + Position [385, 5065, 405, 5085] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum25" + SID "2438" + Ports [2, 1] + Position [385, 5385, 405, 5405] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum26" + SID "2439" + Ports [2, 1] + Position [385, 5710, 405, 5730] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum27" + SID "2440" + Ports [24, 1] + Position [760, 3171, 820, 3479] + ShowName off + Inputs "|++++++++++++++++++++++++" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum5" + SID "2441" + Ports [2, 1] + Position [370, 530, 390, 550] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum6" + SID "2442" + Ports [2, 1] + Position [375, 690, 395, 710] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum7" + SID "2443" + Ports [2, 1] + Position [380, 860, 400, 880] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum8" + SID "2444" + Ports [2, 1] + Position [380, 1040, 400, 1060] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum9" + SID "2445" + Ports [2, 1] + Position [380, 1220, 400, 1240] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "Out1" + SID "2446" + Position [845, 3318, 875, 3332] + IconDisplay "Port number" + } + Line { + SrcBlock "Product1" + SrcPort 1 + Points [15, 0] + Branch { + Points [110, 0; 0, 3225] + DstBlock "Sum27" + DstPort 24 + } + Branch { + Points [0, -10] + DstBlock "Display7" + DstPort 1 + } + } + Line { + SrcBlock "Sum1" + SrcPort 1 + Points [0, -5] + Branch { + Points [-50, 0] + DstBlock "Sum5" + DstPort 1 + } + Branch { + Points [5, 0] + Branch { + Points [0, -55] + DstBlock "Display8" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction2" + DstPort 2 + } + } + } + Line { + SrcBlock "Constant2" + SrcPort 1 + DstBlock "Sum1" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction1" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product1" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero1" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product1" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator1" + SrcPort 1 + DstBlock "Compare\nTo Zero1" + DstPort 1 + } + Line { + SrcBlock "Constant1" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction1" + DstPort 1 + } + Line { + SrcBlock "Sum27" + SrcPort 1 + DstBlock "Out1" + DstPort 1 + } + Line { + SrcBlock "In2" + SrcPort 1 + Points [15, 0] + Branch { + Points [0, -105] + DstBlock "Bitwise\nOperator1" + DstPort 1 + } + Branch { + Points [0, 80] + Branch { + Points [0, 150] + Branch { + Points [0, 155] + Branch { + Points [0, 175] + Branch { + Points [0, 180; 5, 0] + Branch { + Points [-5, 0; 0, 175] + Branch { + Points [0, 185] + Branch { + Points [0, 190] + Branch { + Points [0, 195] + Branch { + Points [0, 215] + Branch { + Points [0, 230] + Branch { + Points [0, 240] + Branch { + Points [0, 260] + Branch { + Points [0, 265] + Branch { + Points [0, 275] + Branch { + Points [0, 280] + Branch { + Points [0, 285] + Branch { + Points [0, 300] + Branch { + Points [0, 305] + Branch { + Points [0, 310] + Branch { + Points [0, 315] + Branch { + Points [0, 320] + Branch { + Points [0, 325] + DstBlock "Bitwise\nOperator28" + DstPort 1 + } + Branch { + DstBlock "Bitwise\nOperator27" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator26" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator25" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator24" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator23" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator22" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator21" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator20" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator19" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator18" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator17" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator16" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator15" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator14" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator13" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator12" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator11" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator10" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator9" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator8" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator7" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator6" + DstPort 1 + } + } + } + Line { + SrcBlock "In1" + SrcPort 1 + Points [0, -10; 280, 0] + Branch { + Points [0, 170] + DstBlock "Sum1" + DstPort 1 + } + Branch { + Points [0, -20] + DstBlock "Math\nFunction1" + DstPort 2 + } + } + Line { + SrcBlock "Product24" + SrcPort 1 + Points [135, 0] + DstBlock "Sum27" + DstPort 1 + } + Line { + SrcBlock "Product23" + SrcPort 1 + Points [135, 0] + DstBlock "Sum27" + DstPort 2 + } + Line { + SrcBlock "Product22" + SrcPort 1 + Points [35, 0; 0, -1655] + DstBlock "Sum27" + DstPort 23 + } + Line { + SrcBlock "Product21" + SrcPort 1 + Points [40, 0; 0, -1350] + DstBlock "Sum27" + DstPort 22 + } + Line { + SrcBlock "Product20" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 21 + } + Line { + SrcBlock "Product19" + SrcPort 1 + Points [40, 0; 0, -755] + DstBlock "Sum27" + DstPort 20 + } + Line { + SrcBlock "Product18" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 19 + } + Line { + SrcBlock "Product17" + SrcPort 1 + Points [40, 0; 0, -190] + DstBlock "Sum27" + DstPort 18 + } + Line { + SrcBlock "Product16" + SrcPort 1 + Points [40, 0; 0, 80] + DstBlock "Sum27" + DstPort 17 + } + Line { + SrcBlock "Product15" + SrcPort 1 + Points [40, 0; 0, 345] + DstBlock "Sum27" + DstPort 16 + } + Line { + SrcBlock "Product14" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 15 + } + Line { + SrcBlock "Product13" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 14 + } + Line { + SrcBlock "Product12" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 13 + } + Line { + SrcBlock "Product11" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 12 + } + Line { + SrcBlock "Product10" + SrcPort 1 + Points [40, 0; 0, 1500] + DstBlock "Sum27" + DstPort 11 + } + Line { + SrcBlock "Product9" + SrcPort 1 + Points [40, 0; 0, 1690] + DstBlock "Sum27" + DstPort 10 + } + Line { + SrcBlock "Product8" + SrcPort 1 + Points [40, 0; 0, 1870] + DstBlock "Sum27" + DstPort 9 + } + Line { + SrcBlock "Product7" + SrcPort 1 + Points [95, 0] + Branch { + Points [0, -45] + DstBlock "Display6" + DstPort 1 + } + Branch { + Points [45, 0] + DstBlock "Sum27" + DstPort 8 + } + } + Line { + SrcBlock "Product6" + SrcPort 1 + Points [40, 0; 0, 5] + Branch { + DstBlock "Display4" + DstPort 1 + } + Branch { + Points [0, 2205] + DstBlock "Sum27" + DstPort 7 + } + } + Line { + SrcBlock "Product5" + SrcPort 1 + Points [15, 0] + Branch { + Points [0, -15] + DstBlock "Display3" + DstPort 1 + } + Branch { + Points [0, 2380] + DstBlock "Sum27" + DstPort 6 + } + } + Line { + SrcBlock "Product4" + SrcPort 1 + Points [105, 0] + Branch { + Points [0, -45] + DstBlock "Display2" + DstPort 1 + } + Branch { + Points [40, 0] + DstBlock "Sum27" + DstPort 5 + } + } + Line { + SrcBlock "Product3" + SrcPort 1 + Points [105, 0] + Branch { + Points [0, -35] + DstBlock "Display1" + DstPort 1 + } + Branch { + Points [45, 0] + DstBlock "Sum27" + DstPort 4 + } + } + Line { + SrcBlock "Product2" + SrcPort 1 + Points [40, 0] + Branch { + Points [0, -60] + DstBlock "Display5" + DstPort 1 + } + Branch { + Points [0, 2830] + DstBlock "Sum27" + DstPort 3 + } + } + Line { + SrcBlock "Sum26" + SrcPort 1 + Points [5, 0; 0, -5] + DstBlock "Math\nFunction24" + DstPort 2 + } + Line { + SrcBlock "Constant53" + SrcPort 1 + DstBlock "Sum26" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction24" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product24" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero24" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product24" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator28" + SrcPort 1 + DstBlock "Compare\nTo Zero24" + DstPort 1 + } + Line { + SrcBlock "Constant52" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction24" + DstPort 1 + } + Line { + SrcBlock "Sum25" + SrcPort 1 + Points [5, 0; 0, -5; 5, 0] + Branch { + Points [-50, 0] + DstBlock "Sum26" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction23" + DstPort 2 + } + } + Line { + SrcBlock "Constant51" + SrcPort 1 + DstBlock "Sum25" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction23" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product23" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero23" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product23" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator27" + SrcPort 1 + DstBlock "Compare\nTo Zero23" + DstPort 1 + } + Line { + SrcBlock "Constant50" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction23" + DstPort 1 + } + Line { + SrcBlock "Sum24" + SrcPort 1 + Points [5, 0; 0, -5; 5, 0] + Branch { + Points [-50, 0] + DstBlock "Sum25" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction22" + DstPort 2 + } + } + Line { + SrcBlock "Constant49" + SrcPort 1 + DstBlock "Sum24" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction22" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product22" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero22" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product22" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator26" + SrcPort 1 + DstBlock "Compare\nTo Zero22" + DstPort 1 + } + Line { + SrcBlock "Constant48" + SrcPort 1 + Points [5, 0; 0, 25] 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BlockType Inport + Name "In1" + SID "2464" + Position [50, 48, 80, 62] + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "2465" + Position [25, 248, 55, 262] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In3" + SID "2466" + Position [50, 433, 80, 447] + Port "3" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In4" + SID "2467" + Position [50, 528, 80, 542] + Port "4" + IconDisplay "Port number" + } + Block { + BlockType Reference + Name "Bitwise\nOperator" + SID "2468" + Ports [1, 1] + Position [375, 161, 415, 199] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('01111111')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator1" + SID "2469" + Ports [1, 1] + Position [255, 251, 295, 289] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('10000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator2" + SID "2470" + Ports [1, 1] + Position [285, 26, 325, 64] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('10000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator3" + SID "2471" + Ports [1, 1] + Position [255, 336, 295, 374] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('01111111')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Constant + Name "Constant4" + SID "2472" + Position [855, 280, 885, 310] + Value "127" + } + Block { + BlockType Constant + Name "Constant5" + SID "2473" + Position [650, 655, 740, 685] + Value "8388608" + } + Block { + BlockType Constant + Name "Constant7" + SID "2474" + Position [740, 45, 770, 75] + Value "-1" + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion" + SID "2475" + Position [105, 38, 180, 72] + OutDataTypeStr "uint8" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion1" + SID "2476" + Position [105, 238, 180, 272] + OutDataTypeStr "uint8" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion2" + SID "2477" + Position [110, 333, 185, 367] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion3" + SID "2478" + Position [105, 423, 180, 457] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion4" + SID "2479" + Position [105, 518, 180, 552] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion5" + SID "2480" + Position [800, 653, 875, 687] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion7" + SID "2481" + Position [670, 118, 745, 152] + OutDataTypeStr "double" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Display + Name "Display3" + SID "2482" + Ports [1] + Position [460, 162, 550, 188] + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "2483" + Ports [1] + Position [670, 217, 760, 243] + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Exponent" + SID "2484" + Ports [1] + Position [715, 282, 805, 308] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Mantissa" + SID "2485" + Ports [1] + Position [1015, 558, 1295, 592] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction" + SID "2486" + Ports [2, 1] + Position [825, 102, 855, 133] + Operator "pow" + } + Block { + BlockType Product + Name "Product" + SID "2487" + Ports [2, 1] + Position [1225, 277, 1255, 308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Reference + Name "Shift\nArithmetic" + SID "2488" + Ports [1, 1] + Position [565, 215, 645, 255] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-1" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic1" + SID "2489" + Ports [1, 1] + Position [335, 255, 415, 295] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "7" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic2" + SID "2490" + Ports [1, 1] + Position [360, 25, 440, 65] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "7" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic3" + SID "2491" + Ports [1, 1] + Position [370, 335, 450, 375] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels 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nBitShiftRight "-8" + nBinPtShiftRight "0" + } + Block { + BlockType Display + Name "Sign" + SID "2493" + Ports [1] + Position [480, 32, 570, 58] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType SubSystem + Name "Subsystem" + SID "2494" + Ports [2, 1] + Position [1125, 350, 1165, 410] + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "Subsystem" + Location [2, 82, 1653, 1004] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "2495" + Position [25, 235, 55, 250] + BlockRotation 270 + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "2496" + Position [220, 358, 250, 372] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Reference + Name "Bitwise\nOperator1" + SID "2497" + Ports [1, 1] + Position [410, 241, 450, 279] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0100000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator10" + SID "2498" + Ports [1, 1] + Position [425, 1086, 465, 1124] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000001000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator11" + SID "2499" + Ports [1, 1] + Position [425, 1266, 465, 1304] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000100000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator12" + SID "2500" + Ports [1, 1] + Position [425, 1446, 465, 1484] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000010000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator13" + SID "2501" + Ports [1, 1] + Position [425, 1636, 465, 1674] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000001000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator14" + SID "2502" + Ports [1, 1] + Position [425, 1836, 465, 1874] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000100000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator15" + SID "2503" + Ports [1, 1] + Position [425, 2046, 465, 2084] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000010000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator16" + SID "2504" + Ports [1, 1] + Position [425, 2276, 465, 2314] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000001000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator17" + SID "2505" + Ports [1, 1] + Position [425, 2521, 465, 2559] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000100000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator18" + SID "2506" + Ports [1, 1] + Position [425, 2776, 465, 2814] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000010000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator19" + SID "2507" + Ports [1, 1] + Position [425, 3041, 465, 3079] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000001000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator20" + SID "2508" + Ports [1, 1] + Position [425, 3316, 465, 3354] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000100000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator21" + SID "2509" + Ports [1, 1] + Position [425, 3596, 465, 3634] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000010000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator22" + SID "2510" + Ports [1, 1] + Position [425, 3886, 465, 3924] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000001000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator23" + SID "2511" + Ports [1, 1] + Position [425, 4181, 465, 4219] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000100000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator24" + SID "2512" + Ports [1, 1] + Position [425, 4486, 465, 4524] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000010000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator25" + SID "2513" + Ports [1, 1] + Position [425, 4796, 465, 4834] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000001000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator26" + SID "2514" + Ports [1, 1] + Position [430, 5111, 470, 5149] + LibraryVersion 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BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator6" + SID "2517" + Ports [1, 1] + Position [415, 426, 455, 464] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0010000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator7" + SID "2518" + Ports [1, 1] + Position [415, 576, 455, 614] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0001000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator8" + SID "2519" + Ports [1, 1] + Position [420, 736, 460, 774] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000100000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator9" + SID "2520" + Ports [1, 1] + Position [425, 906, 465, 944] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000010000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Compare\nTo Zero1" + SID "2521" + Ports [1, 1] + Position [480, 245, 510, 275] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero10" + SID "2522" + Ports [1, 1] + Position [495, 1840, 525, 1870] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero11" + SID "2523" + Ports [1, 1] + Position [495, 2050, 525, 2080] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero12" + SID "2524" + Ports [1, 1] + Position [495, 2280, 525, 2310] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero13" + SID "2525" + Ports [1, 1] + Position [495, 2525, 525, 2555] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero14" + SID "2526" + Ports [1, 1] + Position [495, 2780, 525, 2810] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero15" + SID "2527" + Ports [1, 1] + Position [495, 3045, 525, 3075] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero16" + SID "2528" + Ports [1, 1] + Position [495, 3320, 525, 3350] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero17" + SID "2529" + Ports [1, 1] + Position [495, 3600, 525, 3630] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero18" + SID "2530" + Ports [1, 1] + Position [495, 3890, 525, 3920] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero19" + SID "2531" + Ports [1, 1] + Position [495, 4185, 525, 4215] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero2" + SID "2532" + Ports [1, 1] + Position [485, 430, 515, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero20" + SID "2533" + Ports [1, 1] + Position [495, 4490, 525, 4520] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero21" + SID "2534" + Ports [1, 1] + Position [495, 4800, 525, 4830] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero22" + SID "2535" + Ports [1, 1] + Position [500, 5115, 530, 5145] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero23" + SID "2536" + Ports [1, 1] + Position [500, 5435, 530, 5465] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero24" + SID "2537" + Ports [1, 1] + Position [500, 5760, 530, 5790] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero3" + SID "2538" + Ports [1, 1] + Position [485, 580, 515, 610] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero4" + SID "2539" + Ports [1, 1] + Position [490, 740, 520, 770] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero5" + SID "2540" + Ports [1, 1] + Position [495, 910, 525, 940] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero6" + SID "2541" + Ports [1, 1] + Position [495, 1090, 525, 1120] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero7" + SID "2542" + Ports [1, 1] + Position [495, 1270, 525, 1300] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero8" + SID "2543" + Ports [1, 1] + Position [495, 1450, 525, 1480] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero9" + SID "2544" + Ports [1, 1] + Position [495, 1640, 525, 1670] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Constant + Name "Constant1" + SID "2545" + Position [360, 145, 390, 175] + Value "2" + } + Block { + BlockType Constant + Name "Constant10" + SID "2546" + Position [365, 480, 395, 510] + Value "2" + } + Block { + BlockType Constant + Name "Constant11" + SID "2547" + Position [335, 550, 365, 580] + } + Block { + BlockType Constant + Name "Constant12" + SID "2548" + Position [370, 640, 400, 670] + Value "2" + } + Block { + BlockType Constant + Name "Constant13" + SID "2549" + Position [340, 710, 370, 740] + } + Block { + BlockType Constant + Name "Constant14" + SID "2550" + Position [375, 810, 405, 840] + Value "2" + } + Block { + BlockType Constant + Name "Constant15" + SID "2551" + Position [345, 880, 375, 910] + } + Block { + BlockType Constant + Name "Constant16" + SID "2552" + Position [375, 990, 405, 1020] + Value "2" + } + Block { + BlockType Constant + Name "Constant17" + SID "2553" + Position [345, 1060, 375, 1090] + } + Block { + BlockType Constant + Name "Constant18" + SID "2554" + Position [375, 1170, 405, 1200] + Value "2" + } + Block { + BlockType Constant + Name "Constant19" + SID "2555" + Position [345, 1240, 375, 1270] + } + Block { + BlockType Constant + Name "Constant2" + SID "2556" + Position [345, 400, 375, 430] + } + Block { + BlockType Constant + Name "Constant20" + SID "2557" + Position [375, 1350, 405, 1380] + Value "2" + } + Block { + BlockType Constant + Name "Constant21" + SID "2558" + Position [345, 1420, 375, 1450] + } + Block { + BlockType Constant + Name "Constant22" + SID "2559" + Position [375, 1540, 405, 1570] + Value "2" + } + Block { + BlockType Constant + Name "Constant23" + SID "2560" + Position [345, 1610, 375, 1640] + } + Block { + BlockType Constant + Name "Constant24" + SID "2561" + Position [375, 1740, 405, 1770] + Value "2" + } + Block { + BlockType Constant + Name "Constant25" + SID "2562" + Position [345, 1810, 375, 1840] + } + Block { + BlockType Constant + Name "Constant26" + SID "2563" + Position [375, 1950, 405, 1980] + Value "2" + } + Block { + BlockType Constant + Name "Constant27" + SID "2564" + Position [345, 2020, 375, 2050] + } + Block { + BlockType Constant + Name "Constant28" + SID "2565" + Position [375, 2180, 405, 2210] + Value "2" + } + Block { + BlockType Constant + Name "Constant29" + SID "2566" + Position [345, 2250, 375, 2280] + } + Block { + BlockType Constant + Name "Constant30" + SID "2567" + Position [375, 2425, 405, 2455] + Value "2" + } + Block { + BlockType Constant + Name "Constant31" + SID "2568" + Position [345, 2495, 375, 2525] + } + Block { + BlockType Constant + Name "Constant32" + SID "2569" + Position [375, 2680, 405, 2710] + Value "2" + } + Block { + BlockType Constant + Name "Constant33" + SID "2570" + Position [345, 2750, 375, 2780] + } + Block { + BlockType Constant + Name "Constant34" + SID "2571" + Position [375, 2945, 405, 2975] + Value "2" + } + Block { + BlockType Constant + Name "Constant35" + SID "2572" + Position [345, 3015, 375, 3045] + } + Block { + BlockType Constant + Name "Constant36" + SID "2573" + Position [375, 3220, 405, 3250] + Value "2" + } + Block { + BlockType Constant + Name "Constant37" + SID "2574" + Position [345, 3290, 375, 3320] + } + Block { + BlockType Constant + Name "Constant38" + SID "2575" + Position [375, 3500, 405, 3530] + Value "2" + } + Block { + BlockType Constant + Name "Constant39" + SID "2576" + Position [345, 3570, 375, 3600] + } + Block { + BlockType Constant + Name "Constant40" + SID "2577" + Position [375, 3790, 405, 3820] + Value "2" + } + Block { + BlockType Constant + Name "Constant41" + SID "2578" + Position [345, 3860, 375, 3890] + } + Block { + BlockType Constant + Name "Constant42" + SID "2579" + Position [375, 4085, 405, 4115] + Value "2" + } + Block { + BlockType Constant + Name "Constant43" + SID "2580" + Position [345, 4155, 375, 4185] + } + Block { + BlockType Constant + Name "Constant44" + SID "2581" + Position [375, 4390, 405, 4420] + Value "2" + } + Block { + BlockType Constant + Name "Constant45" + SID "2582" + Position [345, 4460, 375, 4490] + } + Block { + BlockType Constant + Name "Constant46" + SID "2583" + Position [375, 4700, 405, 4730] + Value "2" + } + Block { + BlockType Constant + Name "Constant47" + SID "2584" + Position [345, 4770, 375, 4800] + } + Block { + BlockType Constant + Name "Constant48" + SID "2585" + Position [380, 5015, 410, 5045] + Value "2" + } + Block { + BlockType Constant + Name "Constant49" + SID "2586" + Position [350, 5085, 380, 5115] + } + Block { + BlockType Constant + Name "Constant50" + SID "2587" + Position [380, 5335, 410, 5365] + Value "2" + } + Block { + BlockType Constant + Name "Constant51" + SID "2588" + Position [350, 5405, 380, 5435] + } + Block { + BlockType Constant + Name "Constant52" + SID "2589" + Position [380, 5660, 410, 5690] + Value "2" + } + Block { + BlockType Constant + Name "Constant53" + SID "2590" + Position [350, 5730, 380, 5760] + } + Block { + BlockType Constant + Name "Constant8" + SID "2591" + Position [365, 330, 395, 360] + Value "2" + } + Block { + BlockType Display + Name "Display1" + SID "2592" + Ports [1] + Position [730, 507, 820, 533] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display2" + SID "2593" + Ports [1] + Position [775, 657, 865, 683] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display3" + SID "2594" + Ports [1] + Position [740, 857, 830, 883] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "2595" + Ports [1] + Position [770, 1057, 860, 1083] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display5" + SID "2596" + Ports [1] + Position [735, 332, 825, 358] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display6" + SID "2597" + Ports [1] + Position [770, 1187, 860, 1213] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display7" + SID "2598" + Ports [1] + Position [640, 197, 730, 223] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display8" + SID "2599" + Ports [1] + Position [490, 317, 580, 343] + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction1" + SID "2600" + Ports [2, 1] + Position [420, 177, 450, 208] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction10" + SID "2601" + Ports [2, 1] + Position [435, 1772, 465, 1803] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction11" + SID "2602" + Ports [2, 1] + Position [435, 1982, 465, 2013] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction12" + SID "2603" + Ports [2, 1] + Position [435, 2212, 465, 2243] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction13" + SID "2604" + Ports [2, 1] + Position [435, 2457, 465, 2488] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction14" + SID "2605" + Ports [2, 1] + Position [435, 2712, 465, 2743] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction15" + SID "2606" + Ports [2, 1] + Position [435, 2977, 465, 3008] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction16" + SID "2607" + Ports [2, 1] + Position [435, 3252, 465, 3283] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction17" + SID "2608" + Ports [2, 1] + Position [435, 3532, 465, 3563] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction18" + SID "2609" + Ports [2, 1] + Position [435, 3822, 465, 3853] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction19" + SID "2610" + Ports [2, 1] + Position [435, 4117, 465, 4148] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction2" + SID "2611" + Ports [2, 1] + Position [425, 362, 455, 393] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction20" + SID "2612" + Ports [2, 1] + Position [435, 4422, 465, 4453] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction21" + SID "2613" + Ports [2, 1] + Position [435, 4732, 465, 4763] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction22" + SID "2614" + Ports [2, 1] + Position [440, 5047, 470, 5078] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction23" + SID "2615" + Ports [2, 1] + Position [440, 5367, 470, 5398] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction24" + SID "2616" + Ports [2, 1] + Position [440, 5692, 470, 5723] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction3" + SID "2617" + Ports [2, 1] + Position [425, 512, 455, 543] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction4" + SID "2618" + Ports [2, 1] + Position [430, 672, 460, 703] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction5" + SID "2619" + Ports [2, 1] + Position [435, 842, 465, 873] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction6" + SID "2620" + Ports [2, 1] + Position [435, 1022, 465, 1053] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction7" + SID "2621" + Ports [2, 1] + Position [435, 1202, 465, 1233] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction8" + SID "2622" + Ports [2, 1] + Position [435, 1382, 465, 1413] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction9" + SID "2623" + Ports [2, 1] + Position [435, 1572, 465, 1603] + Operator "pow" + } + Block { + BlockType Product + Name "Product1" + SID "2624" + Ports [2, 1] + Position [555, 202, 585, 233] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product10" + SID "2625" + Ports [2, 1] + Position [570, 1797, 600, 1828] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product11" + SID "2626" + Ports [2, 1] + Position [570, 2007, 600, 2038] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product12" + SID "2627" + Ports [2, 1] + Position [570, 2237, 600, 2268] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product13" + SID "2628" + Ports [2, 1] + Position [570, 2482, 600, 2513] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product14" + SID "2629" + Ports [2, 1] + Position [570, 2737, 600, 2768] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product15" + SID "2630" + Ports [2, 1] + Position [570, 3002, 600, 3033] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product16" + SID "2631" + Ports [2, 1] + Position [570, 3277, 600, 3308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product17" + SID "2632" + Ports [2, 1] + Position [570, 3557, 600, 3588] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product18" + SID "2633" + Ports [2, 1] + Position [570, 3847, 600, 3878] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product19" + SID "2634" + Ports [2, 1] + Position [570, 4142, 600, 4173] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product2" + SID "2635" + Ports [2, 1] + Position [560, 387, 590, 418] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product20" + SID "2636" + Ports [2, 1] + Position [570, 4447, 600, 4478] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product21" + SID "2637" + Ports [2, 1] + Position [570, 4757, 600, 4788] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product22" + SID "2638" + Ports [2, 1] + Position [575, 5072, 605, 5103] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product23" + SID "2639" + Ports [2, 1] + Position [575, 5392, 605, 5423] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product24" + SID "2640" + Ports [2, 1] + Position [575, 5717, 605, 5748] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product3" + SID "2641" + Ports [2, 1] + Position [560, 537, 590, 568] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product4" + SID "2642" + Ports [2, 1] + Position [565, 697, 595, 728] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product5" + SID "2643" + Ports [2, 1] + Position [570, 867, 600, 898] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product6" + SID "2644" + Ports [2, 1] + Position [570, 1047, 600, 1078] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product7" + SID "2645" + Ports [2, 1] + Position [570, 1227, 600, 1258] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product8" + SID "2646" + Ports [2, 1] + Position [570, 1407, 600, 1438] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product9" + SID "2647" + Ports [2, 1] + Position [570, 1597, 600, 1628] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum1" + SID "2648" + Ports [2, 1] + Position [380, 380, 400, 400] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum10" + SID "2649" + Ports [2, 1] + Position [380, 1400, 400, 1420] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum11" + SID "2650" + Ports [2, 1] + Position [380, 1590, 400, 1610] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum12" + SID "2651" + Ports [2, 1] + Position [380, 1790, 400, 1810] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum13" + SID "2652" + Ports [2, 1] + Position [380, 2000, 400, 2020] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum14" + SID "2653" + Ports [2, 1] + Position [380, 2230, 400, 2250] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum15" + SID "2654" + Ports [2, 1] + Position [380, 2475, 400, 2495] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum16" + SID "2655" + Ports [2, 1] + Position [380, 2730, 400, 2750] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum17" + SID "2656" + Ports [2, 1] + Position [380, 2995, 400, 3015] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum18" + SID "2657" + Ports [2, 1] + Position [380, 3270, 400, 3290] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum19" + SID "2658" + Ports [2, 1] + Position [380, 3550, 400, 3570] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum20" + SID "2659" + Ports [2, 1] + Position [380, 3840, 400, 3860] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum21" + SID "2660" + Ports [2, 1] + Position [380, 4135, 400, 4155] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum22" + SID "2661" + Ports [2, 1] + Position [380, 4440, 400, 4460] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum23" + SID "2662" + Ports [2, 1] + Position [380, 4750, 400, 4770] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum24" + SID "2663" + Ports [2, 1] + Position [385, 5065, 405, 5085] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum25" + SID "2664" + Ports [2, 1] + Position [385, 5385, 405, 5405] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum26" + SID "2665" + Ports [2, 1] + Position [385, 5710, 405, 5730] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum27" + SID "2666" + Ports [24, 1] + Position [760, 3171, 820, 3479] + ShowName off + Inputs "|++++++++++++++++++++++++" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum5" + SID "2667" + Ports [2, 1] + Position [370, 530, 390, 550] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum6" + SID "2668" + Ports [2, 1] + Position [375, 690, 395, 710] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum7" + SID "2669" + Ports [2, 1] + Position [380, 860, 400, 880] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum8" + SID "2670" + Ports [2, 1] + Position [380, 1040, 400, 1060] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum9" + SID "2671" + Ports [2, 1] + Position [380, 1220, 400, 1240] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "Out1" + SID "2672" + Position [845, 3318, 875, 3332] + IconDisplay "Port number" + } + Line { + SrcBlock "Constant8" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction2" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator6" + SrcPort 1 + DstBlock "Compare\nTo Zero2" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero2" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product2" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction2" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product2" + DstPort 1 + } + Line { + SrcBlock "Constant10" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction3" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator7" + SrcPort 1 + DstBlock "Compare\nTo Zero3" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero3" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product3" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction3" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product3" + DstPort 1 + } + Line { + SrcBlock "Constant11" + SrcPort 1 + DstBlock "Sum5" + DstPort 2 + } + Line { + SrcBlock "Sum5" + SrcPort 1 + Points [0, 0; 5, 0] + Branch { + Points [0, 10; -40, 0] + DstBlock "Sum6" + DstPort 1 + } + Branch { + Points [0, -5] + DstBlock "Math\nFunction3" + DstPort 2 + } + } + Line { + SrcBlock "Constant12" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction4" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator8" + SrcPort 1 + DstBlock "Compare\nTo Zero4" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero4" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product4" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction4" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product4" + DstPort 1 + } + Line { + SrcBlock "Constant13" + SrcPort 1 + DstBlock "Sum6" + DstPort 2 + } + Line { + SrcBlock "Sum6" + SrcPort 1 + Points [0, 0; 5, 0] + Branch { + Points [-40, 0] + DstBlock "Sum7" + DstPort 1 + } + Branch { + Points [0, -5] + DstBlock "Math\nFunction4" + DstPort 2 + } + } + Line { + SrcBlock "Constant14" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction5" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator9" + SrcPort 1 + DstBlock "Compare\nTo Zero5" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero5" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product5" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction5" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product5" + DstPort 1 + } + Line { + SrcBlock "Constant15" + SrcPort 1 + DstBlock "Sum7" + DstPort 2 + } + Line { + SrcBlock "Sum7" + SrcPort 1 + Points [0, 0; 5, 0] + Branch { + Points [-45, 0] + DstBlock "Sum8" + DstPort 1 + } + Branch { + Points [0, -5] + DstBlock "Math\nFunction5" + DstPort 2 + } + } + Line { + SrcBlock "Constant16" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction6" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator10" + SrcPort 1 + DstBlock "Compare\nTo Zero6" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero6" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product6" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction6" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product6" + DstPort 1 + } + Line { + SrcBlock "Constant17" + SrcPort 1 + DstBlock "Sum8" + DstPort 2 + } + Line { + SrcBlock "Sum8" + SrcPort 1 + Points [0, 0; 5, 0] + Branch { + Points [-45, 0] + DstBlock "Sum9" + DstPort 1 + } + Branch { + Points [0, -5] + DstBlock "Math\nFunction6" + DstPort 2 + } + } + Line { + SrcBlock "Constant18" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction7" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator11" + SrcPort 1 + DstBlock "Compare\nTo Zero7" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero7" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product7" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction7" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product7" + DstPort 1 + } + Line { + SrcBlock "Constant19" + SrcPort 1 + DstBlock "Sum9" + DstPort 2 + } + Line { + SrcBlock "Sum9" + SrcPort 1 + Points [5, 0; 0, -5; 5, 0] + Branch { + DstBlock "Math\nFunction7" + DstPort 2 + } + Branch { + Points [0, 5; -50, 0] + DstBlock "Sum10" + DstPort 1 + } + } + Line { + SrcBlock "Constant20" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction8" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator12" + SrcPort 1 + DstBlock "Compare\nTo Zero8" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero8" + SrcPort 1 + Points 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FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "hex2float" + Location [13, 125, 1281, 839] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "2679:246" + Position [50, 48, 80, 62] + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "2679:247" + Position [25, 248, 55, 262] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In3" + SID "2679:248" + Position [50, 433, 80, 447] + Port "3" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In4" + SID "2679:249" + Position [50, 528, 80, 542] + Port "4" + IconDisplay "Port number" + } + Block { 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Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000100000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator15" + SID "2679:285" + Ports [1, 1] + Position [425, 2046, 465, 2084] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000010000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator16" + SID "2679:286" + Ports [1, 1] + Position [425, 2276, 465, 2314] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000001000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator17" + SID "2679:287" + Ports [1, 1] + Position [425, 2521, 465, 2559] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000100000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator18" + SID "2679:288" + Ports [1, 1] + Position [425, 2776, 465, 2814] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000010000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator19" + SID "2679:289" + Ports [1, 1] + Position [425, 3041, 465, 3079] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000001000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator20" + SID "2679:290" + Ports [1, 1] + Position [425, 3316, 465, 3354] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000100000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator21" + SID "2679:291" + Ports [1, 1] + Position [425, 3596, 465, 3634] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000010000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator22" + SID "2679:292" + Ports [1, 1] + Position [425, 3886, 465, 3924] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000001000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator23" + SID "2679:293" + Ports [1, 1] + Position [425, 4181, 465, 4219] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000100000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator24" + SID "2679:294" + Ports [1, 1] + Position [425, 4486, 465, 4524] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000010000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator25" + SID "2679:295" + Ports [1, 1] + Position [425, 4796, 465, 4834] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000001000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator26" + SID "2679:296" + Ports [1, 1] + Position [430, 5111, 470, 5149] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000100')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator27" + SID "2679:297" + Ports [1, 1] + Position [430, 5431, 470, 5469] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000010')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator28" + SID "2679:298" + Ports [1, 1] + Position [430, 5756, 470, 5794] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000001')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator6" + SID "2679:299" + Ports [1, 1] + Position [415, 426, 455, 464] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0010000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator7" + SID "2679:300" + Ports [1, 1] + Position [415, 576, 455, 614] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0001000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator8" + SID "2679:301" + Ports [1, 1] + Position [420, 736, 460, 774] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000100000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator9" + SID "2679:302" + Ports [1, 1] + Position [425, 906, 465, 944] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000010000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Compare\nTo Zero1" + SID "2679:303" + Ports [1, 1] + Position [480, 245, 510, 275] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero10" + SID "2679:304" + Ports [1, 1] + Position [495, 1840, 525, 1870] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero11" + SID "2679:305" + Ports [1, 1] + Position [495, 2050, 525, 2080] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero12" + SID "2679:306" + Ports [1, 1] + Position [495, 2280, 525, 2310] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero13" + SID "2679:307" + Ports [1, 1] + Position [495, 2525, 525, 2555] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero14" + SID "2679:308" + Ports [1, 1] + Position [495, 2780, 525, 2810] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero15" + SID "2679:309" + Ports [1, 1] + Position [495, 3045, 525, 3075] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero16" + SID "2679:310" + Ports [1, 1] + Position [495, 3320, 525, 3350] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero17" + SID "2679:311" + Ports [1, 1] + Position [495, 3600, 525, 3630] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero18" + SID "2679:312" + Ports [1, 1] + Position [495, 3890, 525, 3920] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero19" + SID "2679:313" + Ports [1, 1] + Position [495, 4185, 525, 4215] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero2" + SID "2679:314" + Ports [1, 1] + Position [485, 430, 515, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero20" + SID "2679:315" + Ports [1, 1] + Position [495, 4490, 525, 4520] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero21" + SID "2679:316" + Ports [1, 1] + Position [495, 4800, 525, 4830] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero22" + SID "2679:317" + Ports [1, 1] + Position [500, 5115, 530, 5145] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero23" + SID "2679:318" + Ports [1, 1] + Position [500, 5435, 530, 5465] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero24" + SID "2679:319" + Ports [1, 1] + Position [500, 5760, 530, 5790] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero3" + SID "2679:320" + Ports [1, 1] + Position [485, 580, 515, 610] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero4" + SID "2679:321" + Ports [1, 1] + Position [490, 740, 520, 770] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero5" + SID "2679:322" + Ports [1, 1] + Position [495, 910, 525, 940] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero6" + SID "2679:323" + Ports [1, 1] + Position [495, 1090, 525, 1120] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero7" + SID "2679:324" + Ports [1, 1] + Position [495, 1270, 525, 1300] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero8" + SID "2679:325" + Ports [1, 1] + Position [495, 1450, 525, 1480] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero9" + SID "2679:326" + Ports [1, 1] + Position [495, 1640, 525, 1670] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Constant + Name "Constant1" + SID "2679:327" + Position [360, 145, 390, 175] + Value "2" + } + Block { + BlockType Constant + Name "Constant10" + SID "2679:328" + Position [365, 480, 395, 510] + Value "2" + } + Block { + BlockType Constant + Name "Constant11" + SID "2679:329" + Position [335, 550, 365, 580] + } + Block { + BlockType Constant + Name "Constant12" + SID "2679:330" + Position [370, 640, 400, 670] + Value "2" + } + Block { + BlockType Constant + Name "Constant13" + SID "2679:331" + Position [340, 710, 370, 740] + } + Block { + BlockType Constant + Name "Constant14" + SID "2679:332" + Position [375, 810, 405, 840] + Value "2" + } + Block { + BlockType Constant + Name "Constant15" + SID "2679:333" + Position [345, 880, 375, 910] + } + Block { + BlockType Constant + Name "Constant16" + SID "2679:334" + Position [375, 990, 405, 1020] + Value "2" + } + Block { + BlockType Constant + Name "Constant17" + SID "2679:335" + Position [345, 1060, 375, 1090] + } + Block { + BlockType Constant + Name "Constant18" + SID "2679:336" + Position [375, 1170, 405, 1200] + Value "2" + } + Block { + BlockType Constant + Name "Constant19" + SID "2679:337" + Position [345, 1240, 375, 1270] + } + Block { + BlockType Constant + Name "Constant2" + SID "2679:338" + Position [345, 400, 375, 430] + } + Block { + BlockType Constant + Name "Constant20" + SID "2679:339" + Position [375, 1350, 405, 1380] + Value "2" + } + Block { + BlockType Constant + Name "Constant21" + SID "2679:340" + Position [345, 1420, 375, 1450] + } + Block { + BlockType Constant + Name "Constant22" + SID "2679:341" + Position [375, 1540, 405, 1570] + Value "2" + } + Block { + BlockType Constant + Name "Constant23" + SID "2679:342" + Position [345, 1610, 375, 1640] + } + Block { + BlockType Constant + Name "Constant24" + SID "2679:343" + Position [375, 1740, 405, 1770] + Value "2" + } + Block { + BlockType Constant + Name "Constant25" + SID "2679:344" + Position [345, 1810, 375, 1840] + } + Block { + BlockType Constant + Name "Constant26" + SID "2679:345" + Position [375, 1950, 405, 1980] + Value "2" + } + Block { + BlockType Constant + Name "Constant27" + SID "2679:346" + Position [345, 2020, 375, 2050] + } + Block { + BlockType Constant + Name "Constant28" + SID "2679:347" + Position [375, 2180, 405, 2210] + Value "2" + } + Block { + BlockType Constant + Name "Constant29" + SID "2679:348" + Position [345, 2250, 375, 2280] + } + Block { + BlockType Constant + Name "Constant30" + SID "2679:349" + Position [375, 2425, 405, 2455] + Value "2" + } + Block { + BlockType Constant + Name "Constant31" + SID "2679:350" + Position [345, 2495, 375, 2525] + } + Block { + BlockType Constant + Name "Constant32" + SID "2679:351" + Position [375, 2680, 405, 2710] + Value "2" + } + Block { + BlockType Constant + Name "Constant33" + SID "2679:352" + Position [345, 2750, 375, 2780] + } + Block { + BlockType Constant + Name "Constant34" + SID "2679:353" + Position [375, 2945, 405, 2975] + Value "2" + } + Block { + BlockType Constant + Name "Constant35" + SID "2679:354" + Position [345, 3015, 375, 3045] + } + Block { + BlockType Constant + Name "Constant36" + SID "2679:355" + Position [375, 3220, 405, 3250] + Value "2" + } + Block { + BlockType Constant + Name "Constant37" + SID "2679:356" + Position [345, 3290, 375, 3320] + } + Block { + BlockType Constant + Name "Constant38" + SID "2679:357" + Position [375, 3500, 405, 3530] + Value "2" + } + Block { + BlockType Constant + Name "Constant39" + SID "2679:358" + Position [345, 3570, 375, 3600] + } + Block { + BlockType Constant + Name "Constant40" + SID "2679:359" + Position [375, 3790, 405, 3820] + Value "2" + } + Block { + BlockType Constant + Name "Constant41" + SID "2679:360" + Position [345, 3860, 375, 3890] + } + Block { + BlockType Constant + Name "Constant42" + SID "2679:361" + Position [375, 4085, 405, 4115] + Value "2" + } + Block { + BlockType Constant + Name "Constant43" + SID "2679:362" + Position [345, 4155, 375, 4185] + } + Block { + BlockType Constant + Name "Constant44" + SID "2679:363" + Position [375, 4390, 405, 4420] + Value "2" + } + Block { + BlockType Constant + Name "Constant45" + SID "2679:364" + Position [345, 4460, 375, 4490] + } + Block { + BlockType Constant + Name "Constant46" + SID "2679:365" + Position [375, 4700, 405, 4730] + Value "2" + } + Block { + BlockType Constant + Name "Constant47" + SID "2679:366" + Position [345, 4770, 375, 4800] + } + Block { + BlockType Constant + Name "Constant48" + SID "2679:367" + Position [380, 5015, 410, 5045] + Value "2" + } + Block { + BlockType Constant + Name "Constant49" + SID "2679:368" + Position [350, 5085, 380, 5115] + } + Block { + BlockType Constant + Name "Constant50" + SID "2679:369" + Position [380, 5335, 410, 5365] + Value "2" + } + Block { + BlockType Constant + Name "Constant51" + SID "2679:370" + Position [350, 5405, 380, 5435] + } + Block { + BlockType Constant + Name "Constant52" + SID "2679:371" + Position [380, 5660, 410, 5690] + Value "2" + } + Block { + BlockType Constant + Name "Constant53" + SID "2679:372" + Position [350, 5730, 380, 5760] + } + Block { + BlockType Constant + Name "Constant8" + SID "2679:373" + Position [365, 330, 395, 360] + Value "2" + } + Block { + BlockType Display + Name "Display1" + SID "2679:374" + Ports [1] + Position [730, 507, 820, 533] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display2" + SID "2679:375" + Ports [1] + Position [775, 657, 865, 683] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display3" + SID "2679:376" + Ports [1] + Position [740, 857, 830, 883] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "2679:377" + Ports [1] + Position [770, 1057, 860, 1083] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display5" + SID "2679:378" + Ports [1] + Position [735, 332, 825, 358] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display6" + SID "2679:379" + Ports [1] + Position [770, 1187, 860, 1213] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display7" + SID "2679:380" + Ports [1] + Position [640, 197, 730, 223] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display8" + SID "2679:381" + Ports [1] + Position [490, 317, 580, 343] + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction1" + SID "2679:382" + Ports [2, 1] + Position [420, 177, 450, 208] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction10" + SID "2679:383" + Ports [2, 1] + Position [435, 1772, 465, 1803] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction11" + SID "2679:384" + Ports [2, 1] + Position [435, 1982, 465, 2013] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction12" + SID "2679:385" + Ports [2, 1] + Position [435, 2212, 465, 2243] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction13" + SID "2679:386" + Ports [2, 1] + Position [435, 2457, 465, 2488] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction14" + SID "2679:387" + Ports [2, 1] + Position [435, 2712, 465, 2743] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction15" + SID "2679:388" + Ports [2, 1] + Position [435, 2977, 465, 3008] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction16" + SID "2679:389" + Ports [2, 1] + Position [435, 3252, 465, 3283] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction17" + SID "2679:390" + Ports [2, 1] + Position [435, 3532, 465, 3563] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction18" + SID "2679:391" + Ports [2, 1] + Position [435, 3822, 465, 3853] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction19" + SID "2679:392" + Ports [2, 1] + Position [435, 4117, 465, 4148] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction2" + SID "2679:393" + Ports [2, 1] + Position [425, 362, 455, 393] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction20" + SID "2679:394" + Ports [2, 1] + Position [435, 4422, 465, 4453] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction21" + SID "2679:395" + Ports [2, 1] + Position [435, 4732, 465, 4763] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction22" + SID "2679:396" + Ports [2, 1] + Position [440, 5047, 470, 5078] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction23" + SID "2679:397" + Ports [2, 1] + Position [440, 5367, 470, 5398] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction24" + SID "2679:398" + Ports [2, 1] + Position [440, 5692, 470, 5723] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction3" + SID "2679:399" + Ports [2, 1] + Position [425, 512, 455, 543] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction4" + SID "2679:400" + Ports [2, 1] + Position [430, 672, 460, 703] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction5" + SID "2679:401" + Ports [2, 1] + Position [435, 842, 465, 873] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction6" + SID "2679:402" + Ports [2, 1] + Position [435, 1022, 465, 1053] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction7" + SID "2679:403" + Ports [2, 1] + Position [435, 1202, 465, 1233] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction8" + SID "2679:404" + Ports [2, 1] + Position [435, 1382, 465, 1413] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction9" + SID "2679:405" + Ports [2, 1] + Position [435, 1572, 465, 1603] + Operator "pow" + } + Block { + BlockType Product + Name "Product1" + SID "2679:406" + Ports [2, 1] + Position [555, 202, 585, 233] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product10" + SID "2679:407" + Ports [2, 1] + Position [570, 1797, 600, 1828] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product11" + SID "2679:408" + Ports [2, 1] + Position [570, 2007, 600, 2038] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product12" + SID "2679:409" + Ports [2, 1] + Position [570, 2237, 600, 2268] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product13" + SID "2679:410" + Ports [2, 1] + Position [570, 2482, 600, 2513] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product14" + SID "2679:411" + Ports [2, 1] + Position [570, 2737, 600, 2768] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product15" + SID "2679:412" + Ports [2, 1] + Position [570, 3002, 600, 3033] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product16" + SID "2679:413" + Ports [2, 1] + Position [570, 3277, 600, 3308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product17" + SID "2679:414" + Ports [2, 1] + Position [570, 3557, 600, 3588] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product18" + SID "2679:415" + Ports [2, 1] + Position [570, 3847, 600, 3878] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product19" + SID "2679:416" + Ports [2, 1] + Position [570, 4142, 600, 4173] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product2" + SID "2679:417" + Ports [2, 1] + Position [560, 387, 590, 418] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product20" + SID "2679:418" + Ports [2, 1] + Position [570, 4447, 600, 4478] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product21" + SID "2679:419" + Ports [2, 1] + Position [570, 4757, 600, 4788] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product22" + SID "2679:420" + Ports [2, 1] + Position [575, 5072, 605, 5103] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product23" + SID "2679:421" + Ports [2, 1] + Position [575, 5392, 605, 5423] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product24" + SID "2679:422" + Ports [2, 1] + Position [575, 5717, 605, 5748] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product3" + SID "2679:423" + Ports [2, 1] + Position [560, 537, 590, 568] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product4" + SID "2679:424" + Ports [2, 1] + Position [565, 697, 595, 728] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product5" + SID "2679:425" + Ports [2, 1] + Position [570, 867, 600, 898] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product6" + SID "2679:426" + Ports [2, 1] + Position [570, 1047, 600, 1078] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product7" + SID "2679:427" + Ports [2, 1] + Position [570, 1227, 600, 1258] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product8" + SID "2679:428" + Ports [2, 1] + Position [570, 1407, 600, 1438] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product9" + SID "2679:429" + Ports [2, 1] + Position [570, 1597, 600, 1628] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum1" + SID "2679:430" + Ports [2, 1] + Position [380, 380, 400, 400] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum10" + SID "2679:431" + Ports [2, 1] + Position [380, 1400, 400, 1420] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum11" + SID "2679:432" + Ports [2, 1] + Position [380, 1590, 400, 1610] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum12" + SID "2679:433" + Ports [2, 1] + Position [380, 1790, 400, 1810] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum13" + SID "2679:434" + Ports [2, 1] + Position [380, 2000, 400, 2020] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum14" + SID "2679:435" + Ports [2, 1] + Position [380, 2230, 400, 2250] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum15" + SID "2679:436" + Ports [2, 1] + Position [380, 2475, 400, 2495] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum16" + SID "2679:437" + Ports [2, 1] + Position [380, 2730, 400, 2750] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum17" + SID "2679:438" + Ports [2, 1] + Position [380, 2995, 400, 3015] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum18" + SID "2679:439" + Ports [2, 1] + Position [380, 3270, 400, 3290] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum19" + SID "2679:440" + Ports [2, 1] + Position [380, 3550, 400, 3570] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum20" + SID "2679:441" + Ports [2, 1] + Position [380, 3840, 400, 3860] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum21" + SID "2679:442" + Ports [2, 1] + Position [380, 4135, 400, 4155] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum22" + SID "2679:443" + Ports [2, 1] + Position [380, 4440, 400, 4460] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum23" + SID "2679:444" + Ports [2, 1] + Position [380, 4750, 400, 4770] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum24" + SID "2679:445" + Ports [2, 1] + Position [385, 5065, 405, 5085] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum25" + SID "2679:446" + Ports [2, 1] + Position [385, 5385, 405, 5405] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum26" + SID "2679:447" + Ports [2, 1] + Position [385, 5710, 405, 5730] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum27" + SID "2679:448" + Ports [24, 1] + Position [760, 3171, 820, 3479] + ShowName off + Inputs "|++++++++++++++++++++++++" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum5" + SID "2679:449" + Ports [2, 1] + Position [370, 530, 390, 550] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum6" + SID "2679:450" + Ports [2, 1] + Position [375, 690, 395, 710] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum7" + SID "2679:451" + Ports [2, 1] + Position [380, 860, 400, 880] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum8" + SID "2679:452" + Ports [2, 1] + Position [380, 1040, 400, 1060] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum9" + SID "2679:453" + Ports [2, 1] + Position [380, 1220, 400, 1240] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "Out1" + SID "2679:454" + Position [845, 3318, 875, 3332] + IconDisplay "Port number" + } + Line { + SrcBlock "Constant8" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction2" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator6" + SrcPort 1 + DstBlock "Compare\nTo Zero2" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero2" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product2" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction2" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product2" + DstPort 1 + } + Line { + SrcBlock "Constant10" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction3" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator7" + SrcPort 1 + DstBlock "Compare\nTo Zero3" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero3" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product3" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction3" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product3" + DstPort 1 + } + Line { + SrcBlock "Constant11" + SrcPort 1 + DstBlock "Sum5" + DstPort 2 + } + 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Block { + BlockType Display + Name "Exponent" + SID "2680:492" + Ports [1] + Position [715, 282, 805, 308] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Mantissa" + SID "2680:493" + Ports [1] + Position [1015, 558, 1295, 592] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction" + SID "2680:494" + Ports [2, 1] + Position [825, 102, 855, 133] + Operator "pow" + } + Block { + BlockType Product + Name "Product" + SID "2680:495" + Ports [2, 1] + Position [1225, 277, 1255, 308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Reference + Name "Shift\nArithmetic" + SID "2680:496" + Ports [1, 1] + Position [565, 215, 645, 255] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-1" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic1" + SID "2680:497" + Ports [1, 1] + Position [335, 255, 415, 295] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "7" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic2" + SID "2680:498" + Ports [1, 1] + Position [360, 25, 440, 65] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "7" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic3" + SID "2680:499" + Ports [1, 1] + Position [370, 335, 450, 375] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-16" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic4" + SID "2680:500" + Ports [1, 1] + Position [375, 420, 455, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-8" + nBinPtShiftRight "0" + } + Block { + BlockType Display + Name "Sign" + SID "2680:501" + Ports [1] + Position [480, 32, 570, 58] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType SubSystem + Name "Subsystem" + SID "2680:502" + Ports [2, 1] + Position [1125, 350, 1165, 410] + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "Subsystem" + Location [2, 82, 1653, 1004] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "2680:503" + Position [25, 235, 55, 250] + BlockRotation 270 + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "2680:504" + Position [220, 358, 250, 372] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Reference + Name "Bitwise\nOperator1" + SID "2680:505" + Ports [1, 1] + Position [410, 241, 450, 279] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0100000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator10" + SID "2680:506" + Ports [1, 1] + Position [425, 1086, 465, 1124] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000001000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator11" + SID "2680:507" + Ports [1, 1] + Position [425, 1266, 465, 1304] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000100000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator12" + SID "2680:508" + Ports [1, 1] + Position [425, 1446, 465, 1484] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000010000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator13" + SID "2680:509" + Ports [1, 1] + Position [425, 1636, 465, 1674] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000001000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator14" + SID "2680:510" + Ports [1, 1] + Position [425, 1836, 465, 1874] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000100000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator15" + SID "2680:511" + Ports [1, 1] + Position [425, 2046, 465, 2084] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000010000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator16" + SID "2680:512" + Ports [1, 1] + Position [425, 2276, 465, 2314] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000001000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator17" + SID "2680:513" + Ports [1, 1] + Position [425, 2521, 465, 2559] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000100000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator18" + SID "2680:514" + Ports [1, 1] + Position [425, 2776, 465, 2814] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000010000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator19" + SID "2680:515" + Ports [1, 1] + Position [425, 3041, 465, 3079] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000001000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator20" + SID "2680:516" + Ports [1, 1] + Position [425, 3316, 465, 3354] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000100000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator21" + SID "2680:517" + Ports [1, 1] + Position [425, 3596, 465, 3634] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000010000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator22" + SID "2680:518" + Ports [1, 1] + Position [425, 3886, 465, 3924] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000001000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator23" + SID "2680:519" + Ports [1, 1] + Position [425, 4181, 465, 4219] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000100000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator24" + SID "2680:520" + Ports [1, 1] + Position [425, 4486, 465, 4524] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000010000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator25" + SID "2680:521" + Ports [1, 1] + Position [425, 4796, 465, 4834] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000001000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator26" + SID "2680:522" + Ports [1, 1] + Position [430, 5111, 470, 5149] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000100')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator27" + SID "2680:523" + Ports [1, 1] + Position [430, 5431, 470, 5469] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000010')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator28" + SID "2680:524" + Ports [1, 1] + Position [430, 5756, 470, 5794] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000001')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator6" + SID "2680:525" + Ports [1, 1] + Position [415, 426, 455, 464] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0010000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator7" + SID "2680:526" + Ports [1, 1] + Position [415, 576, 455, 614] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0001000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator8" + SID "2680:527" + Ports [1, 1] + Position [420, 736, 460, 774] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000100000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator9" + SID "2680:528" + Ports [1, 1] + Position [425, 906, 465, 944] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000010000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Compare\nTo Zero1" + SID "2680:529" + Ports [1, 1] + Position [480, 245, 510, 275] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero10" + SID "2680:530" + Ports [1, 1] + Position [495, 1840, 525, 1870] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero11" + SID "2680:531" + Ports [1, 1] + Position [495, 2050, 525, 2080] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero12" + SID "2680:532" + Ports [1, 1] + Position [495, 2280, 525, 2310] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero13" + SID "2680:533" + Ports [1, 1] + Position [495, 2525, 525, 2555] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero14" + SID "2680:534" + Ports [1, 1] + Position [495, 2780, 525, 2810] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero15" + SID "2680:535" + Ports [1, 1] + Position [495, 3045, 525, 3075] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero16" + SID "2680:536" + Ports [1, 1] + Position [495, 3320, 525, 3350] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero17" + SID "2680:537" + Ports [1, 1] + Position [495, 3600, 525, 3630] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero18" + SID "2680:538" + Ports [1, 1] + Position [495, 3890, 525, 3920] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero19" + SID "2680:539" + Ports [1, 1] + Position [495, 4185, 525, 4215] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero2" + SID "2680:540" + Ports [1, 1] + Position [485, 430, 515, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero20" + SID "2680:541" + Ports [1, 1] + Position [495, 4490, 525, 4520] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero21" + SID "2680:542" + Ports [1, 1] + Position [495, 4800, 525, 4830] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero22" + SID "2680:543" + Ports [1, 1] + Position [500, 5115, 530, 5145] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero23" + SID "2680:544" + Ports [1, 1] + Position [500, 5435, 530, 5465] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero24" + SID "2680:545" + Ports [1, 1] + Position [500, 5760, 530, 5790] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero3" + SID "2680:546" + Ports [1, 1] + Position [485, 580, 515, 610] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero4" + SID "2680:547" + Ports [1, 1] + Position [490, 740, 520, 770] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero5" + SID "2680:548" + Ports [1, 1] + Position [495, 910, 525, 940] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero6" + SID "2680:549" + Ports [1, 1] + Position [495, 1090, 525, 1120] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero7" + SID "2680:550" + Ports [1, 1] + Position [495, 1270, 525, 1300] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero8" + SID "2680:551" + Ports [1, 1] + Position [495, 1450, 525, 1480] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero9" + SID "2680:552" + Ports [1, 1] + Position [495, 1640, 525, 1670] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Constant + Name "Constant1" + SID "2680:553" + Position [360, 145, 390, 175] + Value "2" + } + Block { + BlockType Constant + Name "Constant10" + SID "2680:554" + Position [365, 480, 395, 510] + Value "2" + } + Block { + BlockType Constant + Name "Constant11" + SID "2680:555" + Position [335, 550, 365, 580] + } + Block { + BlockType Constant + Name "Constant12" + SID "2680:556" + Position [370, 640, 400, 670] + Value "2" + } + Block { + BlockType Constant + Name "Constant13" + SID "2680:557" + Position [340, 710, 370, 740] + } + Block { + BlockType Constant + Name "Constant14" + SID "2680:558" + Position [375, 810, 405, 840] + Value "2" + } + Block { + BlockType Constant + Name "Constant15" + SID "2680:559" + Position [345, 880, 375, 910] + } + Block { + BlockType Constant + Name "Constant16" + SID "2680:560" + Position [375, 990, 405, 1020] + Value "2" + } + Block { + BlockType Constant + Name "Constant17" + SID "2680:561" + Position [345, 1060, 375, 1090] + } + Block { + BlockType Constant + Name "Constant18" + SID "2680:562" + Position [375, 1170, 405, 1200] + Value "2" + } + Block { + BlockType Constant + Name "Constant19" + SID "2680:563" + Position [345, 1240, 375, 1270] + } + Block { + BlockType Constant + Name "Constant2" + SID "2680:564" + Position [345, 400, 375, 430] + } + Block { + BlockType Constant + Name "Constant20" + SID "2680:565" + Position [375, 1350, 405, 1380] + Value "2" + } + Block { + BlockType Constant + Name "Constant21" + SID "2680:566" + Position [345, 1420, 375, 1450] + } + Block { + BlockType Constant + Name "Constant22" + SID "2680:567" + Position [375, 1540, 405, 1570] + Value "2" + } + Block { + BlockType Constant + Name "Constant23" + SID "2680:568" + Position [345, 1610, 375, 1640] + } + Block { + BlockType Constant + Name "Constant24" + SID "2680:569" + Position [375, 1740, 405, 1770] + Value "2" + } + Block { + BlockType Constant + Name "Constant25" + SID "2680:570" + Position [345, 1810, 375, 1840] + } + Block { + BlockType Constant + Name "Constant26" + SID "2680:571" + Position [375, 1950, 405, 1980] + Value "2" + } + Block { + BlockType Constant + Name "Constant27" + SID "2680:572" + Position [345, 2020, 375, 2050] + } + Block { + BlockType Constant + Name "Constant28" + SID "2680:573" + Position [375, 2180, 405, 2210] + Value "2" + } + Block { + BlockType Constant + Name "Constant29" + SID "2680:574" + Position [345, 2250, 375, 2280] + } + Block { + BlockType Constant + Name "Constant30" + SID "2680:575" + Position [375, 2425, 405, 2455] + Value "2" + } + Block { + BlockType Constant + Name "Constant31" + SID "2680:576" + Position [345, 2495, 375, 2525] + } + Block { + BlockType Constant + Name "Constant32" + SID "2680:577" + Position [375, 2680, 405, 2710] + Value "2" + } + Block { + BlockType Constant + Name "Constant33" + SID "2680:578" + Position [345, 2750, 375, 2780] + } + Block { + BlockType Constant + Name "Constant34" + SID "2680:579" + Position [375, 2945, 405, 2975] + Value "2" + } + Block { + BlockType Constant + Name "Constant35" + SID "2680:580" + Position [345, 3015, 375, 3045] + } + Block { + BlockType Constant + Name "Constant36" + SID "2680:581" + Position [375, 3220, 405, 3250] + Value "2" + } + Block { + BlockType Constant + Name "Constant37" + SID "2680:582" + Position [345, 3290, 375, 3320] + } + Block { + BlockType Constant + Name "Constant38" + SID "2680:583" + Position [375, 3500, 405, 3530] + Value "2" + } + Block { + BlockType Constant + Name "Constant39" + SID "2680:584" + Position [345, 3570, 375, 3600] + } + Block { + BlockType Constant + Name "Constant40" + SID "2680:585" + Position [375, 3790, 405, 3820] + Value "2" + } + Block { + BlockType Constant + Name "Constant41" + SID "2680:586" + Position [345, 3860, 375, 3890] + } + Block { + BlockType Constant + Name "Constant42" + SID "2680:587" + Position [375, 4085, 405, 4115] + Value "2" + } + Block { + BlockType Constant + Name "Constant43" + SID "2680:588" + Position [345, 4155, 375, 4185] + } + Block { + BlockType Constant + Name "Constant44" + SID "2680:589" + Position [375, 4390, 405, 4420] + Value "2" + } + Block { + BlockType Constant + Name "Constant45" + SID "2680:590" + Position [345, 4460, 375, 4490] + } + Block { + BlockType Constant + Name "Constant46" + SID "2680:591" + Position [375, 4700, 405, 4730] + Value "2" + } + Block { + BlockType Constant + Name "Constant47" + SID "2680:592" + Position [345, 4770, 375, 4800] + } + Block { + BlockType Constant + Name "Constant48" + SID "2680:593" + Position [380, 5015, 410, 5045] + Value "2" + } + Block { + BlockType Constant + Name "Constant49" + SID "2680:594" + Position [350, 5085, 380, 5115] + } + Block { + BlockType Constant + Name "Constant50" + SID "2680:595" + Position [380, 5335, 410, 5365] + Value "2" + } + Block { + BlockType Constant + Name "Constant51" + SID "2680:596" + Position [350, 5405, 380, 5435] + } + Block { + BlockType Constant + Name "Constant52" + SID "2680:597" + Position [380, 5660, 410, 5690] + Value "2" + } + Block { + BlockType Constant + Name "Constant53" + SID "2680:598" + Position [350, 5730, 380, 5760] + } + Block { + BlockType Constant + Name "Constant8" + SID "2680:599" + Position [365, 330, 395, 360] + Value "2" + } + Block { + BlockType Display + Name "Display1" + SID "2680:600" + Ports [1] + Position [730, 507, 820, 533] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display2" + SID "2680:601" + Ports [1] + Position [775, 657, 865, 683] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display3" + SID "2680:602" + Ports [1] + Position [740, 857, 830, 883] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "2680:603" + Ports [1] + Position [770, 1057, 860, 1083] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display5" + SID "2680:604" + Ports [1] + Position [735, 332, 825, 358] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display6" + SID "2680:605" + Ports [1] + Position [770, 1187, 860, 1213] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display7" + SID "2680:606" + Ports [1] + Position [640, 197, 730, 223] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display8" + SID "2680:607" + Ports [1] + Position [490, 317, 580, 343] + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction1" + SID "2680:608" + Ports [2, 1] + Position [420, 177, 450, 208] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction10" + SID "2680:609" + Ports [2, 1] + Position [435, 1772, 465, 1803] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction11" + SID "2680:610" + Ports [2, 1] + Position [435, 1982, 465, 2013] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction12" + SID "2680:611" + Ports [2, 1] + Position [435, 2212, 465, 2243] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction13" + SID "2680:612" + Ports [2, 1] + Position [435, 2457, 465, 2488] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction14" + SID "2680:613" + Ports [2, 1] + Position [435, 2712, 465, 2743] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction15" + SID "2680:614" + Ports [2, 1] + Position [435, 2977, 465, 3008] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction16" + SID "2680:615" + Ports [2, 1] + Position [435, 3252, 465, 3283] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction17" + SID "2680:616" + Ports [2, 1] + Position [435, 3532, 465, 3563] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction18" + SID "2680:617" + Ports [2, 1] + Position [435, 3822, 465, 3853] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction19" + SID "2680:618" + Ports [2, 1] + Position [435, 4117, 465, 4148] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction2" + SID "2680:619" + Ports [2, 1] + Position [425, 362, 455, 393] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction20" + SID "2680:620" + Ports [2, 1] + Position [435, 4422, 465, 4453] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction21" + SID "2680:621" + Ports [2, 1] + Position [435, 4732, 465, 4763] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction22" + SID "2680:622" + Ports [2, 1] + Position [440, 5047, 470, 5078] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction23" + SID "2680:623" + Ports [2, 1] + Position [440, 5367, 470, 5398] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction24" + SID "2680:624" + Ports [2, 1] + Position [440, 5692, 470, 5723] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction3" + SID "2680:625" + Ports [2, 1] + Position [425, 512, 455, 543] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction4" + SID "2680:626" + Ports [2, 1] + Position [430, 672, 460, 703] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction5" + SID "2680:627" + Ports [2, 1] + Position [435, 842, 465, 873] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction6" + SID "2680:628" + Ports [2, 1] + Position [435, 1022, 465, 1053] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction7" + SID "2680:629" + Ports [2, 1] + Position [435, 1202, 465, 1233] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction8" + SID "2680:630" + Ports [2, 1] + Position [435, 1382, 465, 1413] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction9" + SID "2680:631" + Ports [2, 1] + Position [435, 1572, 465, 1603] + Operator "pow" + } + Block { + BlockType Product + Name "Product1" + SID "2680:632" + Ports [2, 1] + Position [555, 202, 585, 233] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product10" + SID "2680:633" + Ports [2, 1] + Position [570, 1797, 600, 1828] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product11" + SID "2680:634" + Ports [2, 1] + Position [570, 2007, 600, 2038] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product12" + SID "2680:635" + Ports [2, 1] + Position [570, 2237, 600, 2268] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product13" + SID "2680:636" + Ports [2, 1] + Position [570, 2482, 600, 2513] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product14" + SID "2680:637" + Ports [2, 1] + Position [570, 2737, 600, 2768] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product15" + SID "2680:638" + Ports [2, 1] + Position [570, 3002, 600, 3033] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product16" + SID "2680:639" + Ports [2, 1] + Position [570, 3277, 600, 3308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product17" + SID "2680:640" + Ports [2, 1] + Position [570, 3557, 600, 3588] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product18" + SID "2680:641" + Ports [2, 1] + Position [570, 3847, 600, 3878] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product19" + SID "2680:642" + Ports [2, 1] + Position [570, 4142, 600, 4173] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product2" + SID "2680:643" + Ports [2, 1] + Position [560, 387, 590, 418] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product20" + SID "2680:644" + Ports [2, 1] + Position [570, 4447, 600, 4478] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product21" + SID "2680:645" + Ports [2, 1] + Position [570, 4757, 600, 4788] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product22" + SID "2680:646" + Ports [2, 1] + Position [575, 5072, 605, 5103] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product23" + SID "2680:647" + Ports [2, 1] + Position [575, 5392, 605, 5423] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product24" + SID "2680:648" + Ports [2, 1] + Position [575, 5717, 605, 5748] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product3" + SID "2680:649" + Ports [2, 1] + Position [560, 537, 590, 568] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product4" + SID "2680:650" + Ports [2, 1] + Position [565, 697, 595, 728] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product5" + SID "2680:651" + Ports [2, 1] + Position [570, 867, 600, 898] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product6" + SID "2680:652" + Ports [2, 1] + Position [570, 1047, 600, 1078] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product7" + SID "2680:653" + Ports [2, 1] + Position [570, 1227, 600, 1258] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product8" + SID "2680:654" + Ports [2, 1] + Position [570, 1407, 600, 1438] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product9" + SID "2680:655" + Ports [2, 1] + Position [570, 1597, 600, 1628] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum1" + SID "2680:656" + Ports [2, 1] + Position [380, 380, 400, 400] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum10" + SID "2680:657" + Ports [2, 1] + Position [380, 1400, 400, 1420] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum11" + SID "2680:658" + Ports [2, 1] + Position [380, 1590, 400, 1610] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum12" + SID "2680:659" + Ports [2, 1] + Position [380, 1790, 400, 1810] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum13" + SID "2680:660" + Ports [2, 1] + Position [380, 2000, 400, 2020] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum14" + SID "2680:661" + Ports [2, 1] + Position [380, 2230, 400, 2250] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum15" + SID "2680:662" + Ports [2, 1] + Position [380, 2475, 400, 2495] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum16" + SID "2680:663" + Ports [2, 1] + Position [380, 2730, 400, 2750] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum17" + SID "2680:664" + Ports [2, 1] + Position [380, 2995, 400, 3015] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum18" + SID "2680:665" + Ports [2, 1] + Position [380, 3270, 400, 3290] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum19" + SID "2680:666" + Ports [2, 1] + Position [380, 3550, 400, 3570] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum20" + SID "2680:667" + Ports [2, 1] + Position [380, 3840, 400, 3860] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum21" + SID "2680:668" + Ports [2, 1] + Position [380, 4135, 400, 4155] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum22" + SID "2680:669" + Ports [2, 1] + Position [380, 4440, 400, 4460] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum23" + SID "2680:670" + Ports [2, 1] + Position [380, 4750, 400, 4770] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum24" + SID "2680:671" + Ports [2, 1] + Position [385, 5065, 405, 5085] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum25" + SID "2680:672" + Ports [2, 1] + Position [385, 5385, 405, 5405] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum26" + SID "2680:673" + Ports [2, 1] + Position [385, 5710, 405, 5730] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum27" + SID "2680:674" + Ports [24, 1] + Position [760, 3171, 820, 3479] + ShowName off + Inputs "|++++++++++++++++++++++++" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum5" + SID "2680:675" + Ports [2, 1] + Position [370, 530, 390, 550] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum6" + SID "2680:676" + Ports [2, 1] + Position [375, 690, 395, 710] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum7" + SID "2680:677" + Ports [2, 1] + Position [380, 860, 400, 880] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum8" + SID "2680:678" + Ports [2, 1] + Position [380, 1040, 400, 1060] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum9" + SID "2680:679" + Ports [2, 1] + Position [380, 1220, 400, 1240] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "Out1" + SID "2680:680" + Position [845, 3318, 875, 3332] + IconDisplay "Port number" + } + Line { + SrcBlock "Product1" + SrcPort 1 + Points [15, 0] + Branch { + Points [110, 0; 0, 3225] + DstBlock "Sum27" + DstPort 24 + } + Branch { + Points [0, -10] + DstBlock "Display7" + DstPort 1 + } + } + Line { + SrcBlock "Sum1" + SrcPort 1 + Points [0, -5] + Branch { + Points [-50, 0] + DstBlock "Sum5" + DstPort 1 + } + Branch { + Points [5, 0] + Branch { + Points [0, -55] + DstBlock "Display8" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction2" + DstPort 2 + } + } + } + Line { + SrcBlock "Constant2" + SrcPort 1 + DstBlock "Sum1" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction1" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product1" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero1" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product1" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator1" + SrcPort 1 + DstBlock "Compare\nTo Zero1" + DstPort 1 + } + Line { + SrcBlock "Constant1" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction1" + DstPort 1 + } + Line { + SrcBlock "Sum27" + SrcPort 1 + DstBlock "Out1" + DstPort 1 + } + Line { + SrcBlock "In2" + SrcPort 1 + Points [15, 0] + Branch { + Points [0, -105] + DstBlock "Bitwise\nOperator1" + DstPort 1 + } + Branch { + Points [0, 80] + Branch { + Points [0, 150] + Branch { + Points [0, 155] + Branch { + Points [0, 175] + Branch { + Points [0, 180; 5, 0] + Branch { + Points [-5, 0; 0, 175] + Branch { + Points [0, 185] + Branch { + Points [0, 190] + Branch { + Points [0, 195] + Branch { + Points [0, 215] + Branch { + Points [0, 230] + Branch { + Points [0, 240] + Branch { + Points [0, 260] + Branch { + Points [0, 265] + Branch { + Points [0, 275] + Branch { + Points [0, 280] + Branch { + Points [0, 285] + Branch { + Points [0, 300] + Branch { + Points [0, 305] + Branch { + Points [0, 310] + Branch { + Points [0, 315] + Branch { + Points [0, 320] + Branch { + Points [0, 325] + DstBlock "Bitwise\nOperator28" + DstPort 1 + } + Branch { + DstBlock "Bitwise\nOperator27" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator26" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator25" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator24" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator23" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator22" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator21" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator20" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator19" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator18" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator17" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator16" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator15" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator14" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator13" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator12" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator11" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator10" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator9" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator8" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator7" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator6" + DstPort 1 + } + } + } + Line { + SrcBlock "In1" + SrcPort 1 + Points [0, -10; 280, 0] + Branch { + Points [0, 170] + DstBlock "Sum1" + DstPort 1 + } + Branch { + Points [0, -20] + DstBlock "Math\nFunction1" + DstPort 2 + } + } + Line { + SrcBlock "Product24" + SrcPort 1 + Points [135, 0] + DstBlock "Sum27" + DstPort 1 + } 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"Sum27" + DstPort 15 + } + Line { + SrcBlock "Product13" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 14 + } + Line { + SrcBlock "Product12" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 13 + } + Line { + SrcBlock "Product11" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 12 + } + Line { + SrcBlock "Product10" + SrcPort 1 + Points [40, 0; 0, 1500] + DstBlock "Sum27" + DstPort 11 + } + Line { + SrcBlock "Product9" + SrcPort 1 + Points [40, 0; 0, 1690] + DstBlock "Sum27" + DstPort 10 + } + Line { + SrcBlock "Product8" + SrcPort 1 + Points [40, 0; 0, 1870] + DstBlock "Sum27" + DstPort 9 + } + Line { + SrcBlock "Product7" + SrcPort 1 + Points [95, 0] + Branch { + Points [0, -45] + DstBlock "Display6" + DstPort 1 + } + Branch { + Points [45, 0] + DstBlock "Sum27" + DstPort 8 + } + } + Line { + SrcBlock "Product6" + SrcPort 1 + Points [40, 0; 0, 5] + Branch { + DstBlock "Display4" + DstPort 1 + } + Branch { + Points [0, 2205] + DstBlock "Sum27" + DstPort 7 + } + } + Line { + SrcBlock "Product5" + SrcPort 1 + Points [15, 0] + Branch { + Points [0, -15] + DstBlock "Display3" + DstPort 1 + } + Branch { + Points [0, 2380] + DstBlock "Sum27" + DstPort 6 + } + } + Line { + SrcBlock "Product4" + SrcPort 1 + Points [105, 0] + Branch { + Points [0, -45] + DstBlock "Display2" + DstPort 1 + } + Branch { + Points [40, 0] + DstBlock "Sum27" + DstPort 5 + } + } + Line { + SrcBlock "Product3" + SrcPort 1 + Points [105, 0] + Branch { + Points [0, -35] + DstBlock "Display1" + DstPort 1 + } + Branch { + Points [45, 0] + DstBlock "Sum27" + DstPort 4 + } + } + Line { + SrcBlock "Product2" + SrcPort 1 + Points [40, 0] + Branch { + Points [0, -60] + DstBlock "Display5" + DstPort 1 + } + Branch { + Points [0, 2830] + DstBlock "Sum27" + DstPort 3 + } + } + Line { + SrcBlock "Sum26" + SrcPort 1 + Points [5, 0; 0, -5] + DstBlock "Math\nFunction24" + DstPort 2 + } + Line { + SrcBlock "Constant53" + SrcPort 1 + DstBlock "Sum26" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction24" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product24" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero24" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product24" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator28" + SrcPort 1 + DstBlock "Compare\nTo Zero24" + DstPort 1 + } + Line { + SrcBlock "Constant52" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction24" + DstPort 1 + } + Line { + SrcBlock "Sum25" + SrcPort 1 + Points [5, 0; 0, -5; 5, 0] + Branch { + Points [-50, 0] + DstBlock "Sum26" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction23" + DstPort 2 + } + } + Line { + SrcBlock "Constant51" + SrcPort 1 + DstBlock "Sum25" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction23" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product23" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero23" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product23" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator27" + SrcPort 1 + DstBlock "Compare\nTo Zero23" + DstPort 1 + } + Line { + SrcBlock "Constant50" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction23" + DstPort 1 + } + Line { + SrcBlock "Sum24" + SrcPort 1 + Points [5, 0; 0, -5; 5, 0] + Branch { + Points [-50, 0] + DstBlock "Sum25" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction22" + DstPort 2 + } + } + Line { + SrcBlock "Constant49" + SrcPort 1 + DstBlock "Sum24" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction22" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product22" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero22" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product22" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator26" + SrcPort 1 + DstBlock "Compare\nTo Zero22" + DstPort 1 + } + Line { + SrcBlock "Constant48" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction22" + DstPort 1 + } + Line { + SrcBlock "Sum23" + SrcPort 1 + Points [5, 0; 0, -5] + Branch { + Points [-40, 0] + DstBlock "Sum24" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction21" + DstPort 2 + } + } + Line { + SrcBlock "Constant47" + SrcPort 1 + DstBlock "Sum23" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction21" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product21" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero21" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product21" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator25" + SrcPort 1 + DstBlock "Compare\nTo Zero21" + DstPort 1 + } + Line { + SrcBlock "Constant46" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction21" + DstPort 1 + } + Line { + SrcBlock "Sum22" + SrcPort 1 + Points [5, 0; 0, -5] + Branch { + Points [-45, 0] + DstBlock "Sum23" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction20" + DstPort 2 + } + } + Line { + SrcBlock "Constant45" + SrcPort 1 + DstBlock "Sum22" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction20" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product20" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero20" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product20" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator24" + SrcPort 1 + DstBlock "Compare\nTo Zero20" + DstPort 1 + } + Line { + SrcBlock "Constant44" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction20" + DstPort 1 + } + Line { + SrcBlock "Sum21" + SrcPort 1 + Points [5, 0; 0, -5] + Branch { + Points [-45, 0] + DstBlock "Sum22" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction19" + DstPort 2 + } + } + Line { + SrcBlock "Constant43" + SrcPort 1 + DstBlock "Sum21" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction19" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product19" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero19" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product19" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator23" + SrcPort 1 + DstBlock "Compare\nTo Zero19" + DstPort 1 + } + Line { + SrcBlock "Constant42" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction19" + DstPort 1 + } + Line { + SrcBlock "Sum20" + SrcPort 1 + Points [5, 0; 0, -5; 5, 0] + Branch { + Points [-50, 0] + DstBlock "Sum21" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction18" + DstPort 2 + } + } + Line { + SrcBlock "Constant41" + SrcPort 1 + DstBlock "Sum20" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction18" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product18" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero18" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product18" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator22" + SrcPort 1 + DstBlock "Compare\nTo Zero18" + DstPort 1 + } + Line { + SrcBlock "Constant40" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction18" + DstPort 1 + } + Line { + SrcBlock "Sum19" + SrcPort 1 + Points [5, 0; 0, -5; 5, 0] + Branch { + Points [-50, 0] + DstBlock "Sum20" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction17" + DstPort 2 + } + } + Line { + SrcBlock "Constant39" + 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{ + BlockType Reference + Name "Bitwise\nOperator1" + SID "2681:703" + Ports [1, 1] + Position [255, 251, 295, 289] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('10000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator2" + SID "2681:704" + Ports [1, 1] + Position [285, 26, 325, 64] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('10000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator3" + SID "2681:705" + Ports [1, 1] + Position [255, 336, 295, 374] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('01111111')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Constant + Name "Constant4" + SID "2681:706" + Position [855, 280, 885, 310] + Value "127" + } + Block { + BlockType Constant + Name "Constant5" + SID "2681:707" + Position [650, 655, 740, 685] + Value "8388608" + } + Block { + BlockType Constant + Name "Constant7" + SID "2681:708" + Position [740, 45, 770, 75] + Value "-1" + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion" + SID "2681:709" + Position [105, 38, 180, 72] + OutDataTypeStr "uint8" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion1" + SID "2681:710" + Position [105, 238, 180, 272] + OutDataTypeStr "uint8" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion2" + SID "2681:711" + Position [110, 333, 185, 367] + OutDataTypeStr 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Block { + BlockType Reference + Name "Shift\nArithmetic" + SID "2681:722" + Ports [1, 1] + Position [565, 215, 645, 255] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-1" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic1" + SID "2681:723" + Ports [1, 1] + Position [335, 255, 415, 295] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "7" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic2" + SID "2681:724" + Ports [1, 1] + Position [360, 25, 440, 65] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "7" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic3" + SID "2681:725" + Ports [1, 1] + Position [370, 335, 450, 375] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-16" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic4" + SID "2681:726" + Ports [1, 1] + Position [375, 420, 455, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-8" + nBinPtShiftRight "0" + } + Block { + BlockType Display + Name "Sign" + SID "2681:727" + Ports [1] + Position [480, 32, 570, 58] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType SubSystem + Name "Subsystem" + SID "2681:728" + Ports [2, 1] + Position [1125, 350, 1165, 410] + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "Subsystem" + Location [2, 82, 1653, 1004] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "2681:729" + Position [25, 235, 55, 250] + BlockRotation 270 + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "2681:730" + Position [220, 358, 250, 372] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Reference + Name "Bitwise\nOperator1" + SID "2681:731" + Ports [1, 1] + Position [410, 241, 450, 279] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0100000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator10" + SID "2681:732" + Ports [1, 1] + Position [425, 1086, 465, 1124] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000001000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator11" + SID "2681:733" + Ports [1, 1] + Position [425, 1266, 465, 1304] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000100000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator12" + SID "2681:734" + Ports [1, 1] + Position [425, 1446, 465, 1484] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000010000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator13" + SID "2681:735" + Ports [1, 1] + Position [425, 1636, 465, 1674] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000001000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator14" + SID "2681:736" + Ports [1, 1] + Position [425, 1836, 465, 1874] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000100000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator15" + SID "2681:737" + Ports [1, 1] + Position [425, 2046, 465, 2084] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000010000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator16" + SID "2681:738" + Ports [1, 1] + Position [425, 2276, 465, 2314] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000001000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator17" + SID "2681:739" + Ports [1, 1] + Position [425, 2521, 465, 2559] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000100000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator18" + SID "2681:740" + Ports [1, 1] + Position [425, 2776, 465, 2814] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000010000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator19" + SID "2681:741" + Ports [1, 1] + Position [425, 3041, 465, 3079] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000001000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator20" + SID "2681:742" + Ports [1, 1] + Position [425, 3316, 465, 3354] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000100000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator21" + SID "2681:743" + Ports [1, 1] + Position [425, 3596, 465, 3634] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000010000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator22" + SID "2681:744" + Ports [1, 1] + Position [425, 3886, 465, 3924] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000001000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator23" + SID "2681:745" + Ports [1, 1] + Position [425, 4181, 465, 4219] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000100000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator24" + SID "2681:746" + Ports [1, 1] + Position [425, 4486, 465, 4524] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000010000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator25" + SID "2681:747" + Ports [1, 1] + Position [425, 4796, 465, 4834] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000001000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator26" + SID "2681:748" + Ports [1, 1] + Position [430, 5111, 470, 5149] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000100')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator27" + SID "2681:749" + Ports [1, 1] + Position [430, 5431, 470, 5469] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000010')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator28" + SID "2681:750" + Ports [1, 1] + Position [430, 5756, 470, 5794] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000001')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator6" + SID "2681:751" + Ports [1, 1] + Position [415, 426, 455, 464] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0010000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator7" + SID "2681:752" + Ports [1, 1] + Position [415, 576, 455, 614] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0001000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator8" + SID "2681:753" + Ports [1, 1] + Position [420, 736, 460, 774] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000100000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator9" + SID "2681:754" + Ports [1, 1] + Position [425, 906, 465, 944] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000010000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Compare\nTo Zero1" + SID "2681:755" + Ports [1, 1] + Position [480, 245, 510, 275] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero10" + SID "2681:756" + Ports [1, 1] + Position [495, 1840, 525, 1870] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero11" + SID "2681:757" + Ports [1, 1] + Position [495, 2050, 525, 2080] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero12" + SID "2681:758" + Ports [1, 1] + Position [495, 2280, 525, 2310] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero13" + SID "2681:759" + Ports [1, 1] + Position [495, 2525, 525, 2555] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero14" + SID "2681:760" + Ports [1, 1] + Position [495, 2780, 525, 2810] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero15" + SID "2681:761" + Ports [1, 1] + Position [495, 3045, 525, 3075] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero16" + SID "2681:762" + Ports [1, 1] + Position [495, 3320, 525, 3350] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero17" + SID "2681:763" + Ports [1, 1] + Position [495, 3600, 525, 3630] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero18" + SID "2681:764" + Ports [1, 1] + Position [495, 3890, 525, 3920] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero19" + SID "2681:765" + Ports [1, 1] + Position [495, 4185, 525, 4215] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero2" + SID "2681:766" + Ports [1, 1] + Position [485, 430, 515, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero20" + SID "2681:767" + Ports [1, 1] + Position [495, 4490, 525, 4520] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero21" + SID "2681:768" + Ports [1, 1] + Position [495, 4800, 525, 4830] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero22" + SID "2681:769" + Ports [1, 1] + Position [500, 5115, 530, 5145] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero23" + SID "2681:770" + Ports [1, 1] + Position [500, 5435, 530, 5465] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero24" + SID "2681:771" + Ports [1, 1] + Position [500, 5760, 530, 5790] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero3" + SID "2681:772" + Ports [1, 1] + Position [485, 580, 515, 610] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero4" + SID "2681:773" + Ports [1, 1] + Position [490, 740, 520, 770] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero5" + SID "2681:774" + Ports [1, 1] + Position [495, 910, 525, 940] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero6" + SID "2681:775" + Ports [1, 1] + Position [495, 1090, 525, 1120] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero7" + SID "2681:776" + Ports [1, 1] + Position [495, 1270, 525, 1300] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero8" + SID "2681:777" + Ports [1, 1] + Position [495, 1450, 525, 1480] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero9" + SID "2681:778" + Ports [1, 1] + Position [495, 1640, 525, 1670] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Constant + Name "Constant1" + SID "2681:779" + Position [360, 145, 390, 175] + Value "2" + } + Block { + BlockType Constant + Name "Constant10" + SID "2681:780" + Position [365, 480, 395, 510] + Value "2" + } + Block { + BlockType Constant + Name "Constant11" + SID "2681:781" + Position [335, 550, 365, 580] + } + Block { + BlockType Constant + Name "Constant12" + SID "2681:782" + Position [370, 640, 400, 670] + Value "2" + } + Block { + BlockType Constant + Name "Constant13" + SID "2681:783" + Position [340, 710, 370, 740] + } + Block { + BlockType Constant + Name "Constant14" + SID "2681:784" + Position [375, 810, 405, 840] + Value "2" + } + Block { + BlockType Constant + Name "Constant15" + SID "2681:785" + Position [345, 880, 375, 910] + } + Block { + BlockType Constant + Name "Constant16" + SID "2681:786" + Position [375, 990, 405, 1020] + Value "2" + } + Block { + BlockType Constant + Name "Constant17" + SID "2681:787" + Position [345, 1060, 375, 1090] + } + Block { + BlockType Constant + Name "Constant18" + SID "2681:788" + Position [375, 1170, 405, 1200] + Value "2" + } + Block { + BlockType Constant + Name "Constant19" + SID "2681:789" + Position [345, 1240, 375, 1270] + } + Block { + BlockType Constant + Name "Constant2" + SID "2681:790" + Position [345, 400, 375, 430] + } + Block { + BlockType Constant + Name "Constant20" + SID "2681:791" + Position [375, 1350, 405, 1380] + Value "2" + } + Block { + BlockType Constant + Name "Constant21" + SID "2681:792" + Position [345, 1420, 375, 1450] + } + Block { + BlockType Constant + Name "Constant22" + SID "2681:793" + Position [375, 1540, 405, 1570] + Value "2" + } + Block { + BlockType Constant + Name "Constant23" + SID "2681:794" + Position [345, 1610, 375, 1640] + } + Block { + BlockType Constant + Name "Constant24" + SID "2681:795" + Position [375, 1740, 405, 1770] + Value "2" + } + Block { + BlockType Constant + Name "Constant25" + SID "2681:796" + Position [345, 1810, 375, 1840] + } + Block { + BlockType Constant + Name "Constant26" + SID "2681:797" + Position [375, 1950, 405, 1980] + Value "2" + } + Block { + BlockType Constant + Name "Constant27" + SID "2681:798" + Position [345, 2020, 375, 2050] + } + Block { + BlockType Constant + Name "Constant28" + SID "2681:799" + Position [375, 2180, 405, 2210] + Value "2" + } + Block { + BlockType Constant + Name "Constant29" + SID "2681:800" + Position [345, 2250, 375, 2280] + } + Block { + BlockType Constant + Name "Constant30" + SID "2681:801" + Position [375, 2425, 405, 2455] + Value "2" + } + Block { + BlockType Constant + Name "Constant31" + SID "2681:802" + Position [345, 2495, 375, 2525] + } + Block { + BlockType Constant + Name "Constant32" + SID "2681:803" + Position [375, 2680, 405, 2710] + Value "2" + } + Block { + BlockType Constant + Name "Constant33" + SID "2681:804" + Position [345, 2750, 375, 2780] + } + Block { + BlockType Constant + Name "Constant34" + SID "2681:805" + Position [375, 2945, 405, 2975] + Value "2" + } + Block { + BlockType Constant + Name "Constant35" + SID "2681:806" + Position [345, 3015, 375, 3045] + } + Block { + BlockType Constant + Name "Constant36" + SID "2681:807" + Position [375, 3220, 405, 3250] + Value "2" + } + Block { + BlockType Constant + Name "Constant37" + SID "2681:808" + Position [345, 3290, 375, 3320] + } + Block { + BlockType Constant + Name "Constant38" + SID "2681:809" + Position [375, 3500, 405, 3530] + Value "2" + } + Block { + BlockType Constant + Name "Constant39" + SID "2681:810" + Position [345, 3570, 375, 3600] + } + Block { + BlockType Constant + Name "Constant40" + SID "2681:811" + Position [375, 3790, 405, 3820] + Value "2" + } + Block { + BlockType Constant + Name "Constant41" + SID "2681:812" + Position [345, 3860, 375, 3890] + } + Block { + BlockType Constant + Name "Constant42" + SID "2681:813" + Position [375, 4085, 405, 4115] + Value "2" + } + Block { + BlockType Constant + Name "Constant43" + SID "2681:814" + Position [345, 4155, 375, 4185] + } + Block { + BlockType Constant + Name "Constant44" + SID "2681:815" + Position [375, 4390, 405, 4420] + Value "2" + } + Block { + BlockType Constant + Name "Constant45" + SID "2681:816" + Position [345, 4460, 375, 4490] + } + Block { + BlockType Constant + Name "Constant46" + SID "2681:817" + Position [375, 4700, 405, 4730] + Value "2" + } + Block { + BlockType Constant + Name "Constant47" + SID "2681:818" + Position [345, 4770, 375, 4800] + } + Block { + BlockType Constant + Name "Constant48" + SID "2681:819" + Position [380, 5015, 410, 5045] + Value "2" + } + Block { + BlockType Constant + Name "Constant49" + SID "2681:820" + Position [350, 5085, 380, 5115] + } + Block { + BlockType Constant + Name "Constant50" + SID "2681:821" + Position [380, 5335, 410, 5365] + Value "2" + } + Block { + BlockType Constant + Name "Constant51" + SID "2681:822" + Position [350, 5405, 380, 5435] + } + Block { + BlockType Constant + Name "Constant52" + SID "2681:823" + Position [380, 5660, 410, 5690] + Value "2" + } + Block { + BlockType Constant + Name "Constant53" + SID "2681:824" + Position [350, 5730, 380, 5760] + } + Block { + BlockType Constant + Name "Constant8" + SID "2681:825" + Position [365, 330, 395, 360] + Value "2" + } + Block { + BlockType Display + Name "Display1" + SID "2681:826" + Ports [1] + Position [730, 507, 820, 533] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display2" + SID "2681:827" + Ports [1] + Position [775, 657, 865, 683] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display3" + SID "2681:828" + Ports [1] + Position [740, 857, 830, 883] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "2681:829" + Ports [1] + Position [770, 1057, 860, 1083] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display5" + SID "2681:830" + Ports [1] + Position [735, 332, 825, 358] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display6" + SID "2681:831" + Ports [1] + Position [770, 1187, 860, 1213] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display7" + SID "2681:832" + Ports [1] + Position [640, 197, 730, 223] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display8" + SID "2681:833" + Ports [1] + Position [490, 317, 580, 343] + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction1" + SID "2681:834" + Ports [2, 1] + Position [420, 177, 450, 208] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction10" + SID "2681:835" + Ports [2, 1] + Position [435, 1772, 465, 1803] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction11" + SID "2681:836" + Ports [2, 1] + Position [435, 1982, 465, 2013] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction12" + SID "2681:837" + Ports [2, 1] + Position [435, 2212, 465, 2243] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction13" + SID "2681:838" + Ports [2, 1] + Position [435, 2457, 465, 2488] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction14" + SID "2681:839" + Ports [2, 1] + Position [435, 2712, 465, 2743] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction15" + SID "2681:840" + Ports [2, 1] + Position [435, 2977, 465, 3008] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction16" + SID "2681:841" + Ports [2, 1] + Position [435, 3252, 465, 3283] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction17" + SID "2681:842" + Ports [2, 1] + Position [435, 3532, 465, 3563] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction18" + SID "2681:843" + Ports [2, 1] + Position [435, 3822, 465, 3853] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction19" + SID "2681:844" + Ports [2, 1] + Position [435, 4117, 465, 4148] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction2" + SID "2681:845" + Ports [2, 1] + Position [425, 362, 455, 393] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction20" + SID "2681:846" + Ports [2, 1] + Position [435, 4422, 465, 4453] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction21" + SID "2681:847" + Ports [2, 1] + Position [435, 4732, 465, 4763] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction22" + SID "2681:848" + Ports [2, 1] + Position [440, 5047, 470, 5078] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction23" + SID "2681:849" + Ports [2, 1] + Position [440, 5367, 470, 5398] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction24" + SID "2681:850" + Ports [2, 1] + Position [440, 5692, 470, 5723] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction3" + SID "2681:851" + Ports [2, 1] + Position [425, 512, 455, 543] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction4" + SID "2681:852" + Ports [2, 1] + Position [430, 672, 460, 703] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction5" + SID "2681:853" + Ports [2, 1] + Position [435, 842, 465, 873] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction6" + SID "2681:854" + Ports [2, 1] + Position [435, 1022, 465, 1053] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction7" + SID "2681:855" + Ports [2, 1] + Position [435, 1202, 465, 1233] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction8" + SID "2681:856" + Ports [2, 1] + Position [435, 1382, 465, 1413] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction9" + SID "2681:857" + Ports [2, 1] + Position [435, 1572, 465, 1603] + Operator "pow" + } + Block { + BlockType Product + Name "Product1" + SID "2681:858" + Ports [2, 1] + Position [555, 202, 585, 233] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product10" + SID "2681:859" + Ports [2, 1] + Position [570, 1797, 600, 1828] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product11" + SID "2681:860" + Ports [2, 1] + Position [570, 2007, 600, 2038] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product12" + SID "2681:861" + Ports [2, 1] + Position [570, 2237, 600, 2268] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product13" + SID "2681:862" + Ports [2, 1] + Position [570, 2482, 600, 2513] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product14" + SID "2681:863" + Ports [2, 1] + Position [570, 2737, 600, 2768] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product15" + SID "2681:864" + Ports [2, 1] + Position [570, 3002, 600, 3033] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product16" + SID "2681:865" + Ports [2, 1] + Position [570, 3277, 600, 3308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product17" + SID "2681:866" + Ports [2, 1] + Position [570, 3557, 600, 3588] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product18" + SID "2681:867" + Ports [2, 1] + Position [570, 3847, 600, 3878] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product19" + SID "2681:868" + Ports [2, 1] + Position [570, 4142, 600, 4173] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product2" + SID "2681:869" + Ports [2, 1] + Position [560, 387, 590, 418] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product20" + SID "2681:870" + Ports [2, 1] + Position [570, 4447, 600, 4478] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product21" + SID "2681:871" + Ports [2, 1] + Position [570, 4757, 600, 4788] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product22" + SID "2681:872" + Ports [2, 1] + Position [575, 5072, 605, 5103] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product23" + SID "2681:873" + Ports [2, 1] + Position [575, 5392, 605, 5423] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product24" + SID "2681:874" + Ports [2, 1] + Position [575, 5717, 605, 5748] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product3" + SID "2681:875" + Ports [2, 1] + Position [560, 537, 590, 568] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product4" + SID "2681:876" + Ports [2, 1] + Position [565, 697, 595, 728] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product5" + SID "2681:877" + Ports [2, 1] + Position [570, 867, 600, 898] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product6" + SID "2681:878" + Ports [2, 1] + Position [570, 1047, 600, 1078] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product7" + SID "2681:879" + Ports [2, 1] + Position [570, 1227, 600, 1258] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product8" + SID "2681:880" + Ports [2, 1] + Position [570, 1407, 600, 1438] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product9" + SID "2681:881" + Ports [2, 1] + Position [570, 1597, 600, 1628] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum1" + SID "2681:882" + Ports [2, 1] + Position [380, 380, 400, 400] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum10" + SID "2681:883" + Ports [2, 1] + Position [380, 1400, 400, 1420] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum11" + SID "2681:884" + Ports [2, 1] + Position [380, 1590, 400, 1610] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum12" + SID "2681:885" + Ports [2, 1] + Position [380, 1790, 400, 1810] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum13" + SID "2681:886" + Ports [2, 1] + Position [380, 2000, 400, 2020] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum14" + SID "2681:887" + Ports [2, 1] + Position [380, 2230, 400, 2250] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum15" + SID "2681:888" + Ports [2, 1] + Position [380, 2475, 400, 2495] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum16" + SID "2681:889" + Ports [2, 1] + Position [380, 2730, 400, 2750] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum17" + SID "2681:890" + Ports [2, 1] + Position [380, 2995, 400, 3015] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum18" + SID "2681:891" + Ports [2, 1] + Position [380, 3270, 400, 3290] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum19" + SID "2681:892" + Ports [2, 1] + Position [380, 3550, 400, 3570] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum20" + SID "2681:893" + Ports [2, 1] + Position [380, 3840, 400, 3860] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum21" + SID "2681:894" + Ports [2, 1] + Position [380, 4135, 400, 4155] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum22" + SID "2681:895" + Ports [2, 1] + Position [380, 4440, 400, 4460] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum23" + SID "2681:896" + Ports [2, 1] + Position [380, 4750, 400, 4770] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum24" + SID "2681:897" + Ports [2, 1] + Position [385, 5065, 405, 5085] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum25" + SID "2681:898" + Ports [2, 1] + Position [385, 5385, 405, 5405] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum26" + SID "2681:899" + Ports [2, 1] + Position [385, 5710, 405, 5730] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum27" + SID "2681:900" + Ports [24, 1] + Position [760, 3171, 820, 3479] + ShowName off + Inputs "|++++++++++++++++++++++++" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum5" + SID "2681:901" + Ports [2, 1] + Position [370, 530, 390, 550] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum6" + SID "2681:902" + Ports [2, 1] + Position [375, 690, 395, 710] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum7" + SID "2681:903" + Ports [2, 1] + Position [380, 860, 400, 880] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum8" + SID "2681:904" + Ports [2, 1] + Position [380, 1040, 400, 1060] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum9" + SID "2681:905" + Ports [2, 1] + Position [380, 1220, 400, 1240] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "Out1" + SID "2681:906" + Position [845, 3318, 875, 3332] + IconDisplay "Port number" + } + Line { + SrcBlock "Constant8" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction2" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator6" + SrcPort 1 + DstBlock "Compare\nTo Zero2" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero2" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product2" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction2" + SrcPort 1 + Points [40, 0; 0, 15] + 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2 + } + Line { + SrcBlock "Sum7" + SrcPort 1 + Points [0, 0; 5, 0] + Branch { + Points [-45, 0] + DstBlock "Sum8" + DstPort 1 + } + Branch { + Points [0, -5] + DstBlock "Math\nFunction5" + DstPort 2 + } + } + Line { + SrcBlock "Constant16" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction6" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator10" + SrcPort 1 + DstBlock "Compare\nTo Zero6" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero6" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product6" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction6" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product6" + DstPort 1 + } + Line { + SrcBlock "Constant17" + SrcPort 1 + DstBlock "Sum8" + DstPort 2 + } + Line { + SrcBlock "Sum8" + SrcPort 1 + Points [0, 0; 5, 0] + Branch { + Points [-45, 0] + DstBlock "Sum9" + DstPort 1 + } + Branch { + Points [0, -5] + DstBlock "Math\nFunction6" + DstPort 2 + } + } + Line { + SrcBlock "Constant18" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction7" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator11" + SrcPort 1 + DstBlock "Compare\nTo Zero7" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero7" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product7" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction7" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product7" + DstPort 1 + } + Line { + SrcBlock "Constant19" + SrcPort 1 + DstBlock "Sum9" + DstPort 2 + } + Line { + SrcBlock "Sum9" + SrcPort 1 + Points [5, 0; 0, -5; 5, 0] + Branch { + DstBlock "Math\nFunction7" + DstPort 2 + } + Branch { + Points [0, 5; -50, 0] + DstBlock "Sum10" + DstPort 1 + } + } + Line { + SrcBlock "Constant20" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction8" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator12" + SrcPort 1 + DstBlock "Compare\nTo Zero8" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero8" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product8" + DstPort 2 + } + Line { + SrcBlock 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"Math\nFunction9" + DstPort 2 + } + Branch { + Points [-45, 0] + DstBlock "Sum12" + DstPort 1 + } + } + Line { + SrcBlock "Constant24" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction10" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator14" + SrcPort 1 + DstBlock "Compare\nTo Zero10" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero10" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product10" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction10" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product10" + DstPort 1 + } + Line { + SrcBlock "Constant25" + SrcPort 1 + DstBlock "Sum12" + DstPort 2 + } + Line { + SrcBlock "Sum12" + SrcPort 1 + Points [5, 0; 0, -5] + Branch { + DstBlock "Math\nFunction10" + DstPort 2 + } + Branch { + Points [-45, 0] + DstBlock "Sum13" + DstPort 1 + } + } + Line { + SrcBlock "Constant26" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction11" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator15" + SrcPort 1 + DstBlock "Compare\nTo Zero11" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero11" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product11" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction11" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product11" + DstPort 1 + } + Line { + SrcBlock "Constant27" + SrcPort 1 + DstBlock "Sum13" + DstPort 2 + } + Line { + SrcBlock "Sum13" + SrcPort 1 + Points [5, 0; 0, -5] + Branch { + DstBlock "Math\nFunction11" + DstPort 2 + } + Branch { + Points [-45, 0] + DstBlock "Sum14" + DstPort 1 + } + } + Line { + SrcBlock "Constant28" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction12" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator16" + SrcPort 1 + DstBlock "Compare\nTo Zero12" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero12" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product12" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction12" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product12" + DstPort 1 + } + Line { + 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{ + BlockType Reference + Name "Bitwise\nOperator13" + SID "2730" + Ports [1, 1] + Position [425, 1636, 465, 1674] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000001000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator14" + SID "2731" + Ports [1, 1] + Position [425, 1836, 465, 1874] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000100000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator15" + SID "2732" + Ports [1, 1] + Position [425, 2046, 465, 2084] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + 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BitMask "bin2dec('0000000000000000000001000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator26" + SID "2743" + Ports [1, 1] + Position [430, 5111, 470, 5149] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000100')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator27" + SID "2744" + Ports [1, 1] + Position [430, 5431, 470, 5469] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000010')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator28" + SID "2745" + Ports [1, 1] + Position [430, 5756, 470, 5794] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000001')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator6" + SID "2746" + Ports [1, 1] + Position [415, 426, 455, 464] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0010000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator7" + SID "2747" + Ports [1, 1] + Position [415, 576, 455, 614] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0001000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator8" + SID "2748" + Ports [1, 1] + Position [420, 736, 460, 774] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000100000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator9" + SID "2749" + Ports [1, 1] + Position [425, 906, 465, 944] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000010000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Compare\nTo Zero1" + SID "2750" + Ports [1, 1] + Position [480, 245, 510, 275] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero10" + SID "2751" + Ports [1, 1] + Position [495, 1840, 525, 1870] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero11" + SID "2752" + Ports [1, 1] + Position [495, 2050, 525, 2080] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero12" + SID "2753" + Ports [1, 1] + Position [495, 2280, 525, 2310] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero13" + SID "2754" + Ports [1, 1] + Position [495, 2525, 525, 2555] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero14" + SID "2755" + Ports [1, 1] + Position [495, 2780, 525, 2810] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero15" + SID "2756" + Ports [1, 1] + Position [495, 3045, 525, 3075] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero16" + SID "2757" + Ports [1, 1] + Position [495, 3320, 525, 3350] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero17" + SID "2758" + Ports [1, 1] + Position [495, 3600, 525, 3630] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero18" + SID "2759" + Ports [1, 1] + Position [495, 3890, 525, 3920] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero19" + SID "2760" + Ports [1, 1] + Position [495, 4185, 525, 4215] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero2" + SID "2761" + Ports [1, 1] + Position [485, 430, 515, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero20" + SID "2762" + Ports [1, 1] + Position [495, 4490, 525, 4520] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero21" + SID "2763" + Ports [1, 1] + Position [495, 4800, 525, 4830] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero22" + SID "2764" + Ports [1, 1] + Position [500, 5115, 530, 5145] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero23" + SID "2765" + Ports [1, 1] + Position [500, 5435, 530, 5465] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero24" + SID "2766" + Ports [1, 1] + Position [500, 5760, 530, 5790] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero3" + SID "2767" + Ports [1, 1] + Position [485, 580, 515, 610] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero4" + SID "2768" + Ports [1, 1] + Position [490, 740, 520, 770] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero5" + SID "2769" + Ports [1, 1] + Position [495, 910, 525, 940] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero6" + SID "2770" + Ports [1, 1] + Position [495, 1090, 525, 1120] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero7" + SID "2771" + Ports [1, 1] + Position [495, 1270, 525, 1300] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero8" + SID "2772" + Ports [1, 1] + Position [495, 1450, 525, 1480] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero9" + SID "2773" + Ports [1, 1] + Position [495, 1640, 525, 1670] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Constant + Name "Constant1" + SID "2774" + Position [360, 145, 390, 175] + Value "2" + } + Block { + BlockType Constant + Name "Constant10" + SID "2775" + Position [365, 480, 395, 510] + Value "2" + } + Block { + BlockType Constant + Name "Constant11" + SID "2776" + Position [335, 550, 365, 580] + } + Block { + BlockType Constant + Name "Constant12" + SID "2777" + Position [370, 640, 400, 670] + Value "2" + } + Block { + BlockType Constant + Name "Constant13" + SID "2778" + Position [340, 710, 370, 740] + } + Block { + BlockType Constant + Name "Constant14" + SID "2779" + Position [375, 810, 405, 840] + Value "2" + } + Block { + BlockType Constant + Name "Constant15" + SID "2780" + Position [345, 880, 375, 910] + } + Block { + BlockType Constant + Name "Constant16" + SID "2781" + Position [375, 990, 405, 1020] + Value "2" + } + Block { + BlockType Constant + Name "Constant17" + SID "2782" + Position [345, 1060, 375, 1090] + } + Block { + BlockType Constant + Name "Constant18" + SID "2783" + Position [375, 1170, 405, 1200] + Value "2" + } + Block { + BlockType Constant + Name "Constant19" + SID "2784" + Position [345, 1240, 375, 1270] + } + Block { + BlockType Constant + Name "Constant2" + SID "2785" + Position [345, 400, 375, 430] + } + Block { + BlockType Constant + Name "Constant20" + SID "2786" + Position [375, 1350, 405, 1380] + Value "2" + } + Block { + BlockType Constant + Name "Constant21" + SID "2787" + Position [345, 1420, 375, 1450] + } + Block { + BlockType Constant + Name "Constant22" + SID "2788" + Position [375, 1540, 405, 1570] + Value "2" + } + Block { + BlockType Constant + Name "Constant23" + SID "2789" + Position [345, 1610, 375, 1640] + } + Block { + BlockType Constant + Name "Constant24" + SID "2790" + Position [375, 1740, 405, 1770] + Value "2" + } + Block { + BlockType Constant + Name "Constant25" + SID "2791" + Position [345, 1810, 375, 1840] + } + Block { + BlockType Constant + Name "Constant26" + SID "2792" + Position [375, 1950, 405, 1980] + Value "2" + } + Block { + BlockType Constant + Name "Constant27" + SID "2793" + Position [345, 2020, 375, 2050] + } + Block { + BlockType Constant + Name "Constant28" + SID "2794" + Position [375, 2180, 405, 2210] + Value "2" + } + Block { + BlockType Constant + Name "Constant29" + SID "2795" + Position [345, 2250, 375, 2280] + } + Block { + BlockType Constant + Name "Constant30" + SID "2796" + Position [375, 2425, 405, 2455] + Value "2" + } + Block { + BlockType Constant + Name "Constant31" + SID "2797" + Position [345, 2495, 375, 2525] + } + Block { + BlockType Constant + Name "Constant32" + SID "2798" + Position [375, 2680, 405, 2710] + Value "2" + } + Block { + BlockType Constant + Name "Constant33" + SID "2799" + Position [345, 2750, 375, 2780] + } + Block { + BlockType Constant + Name "Constant34" + SID "2800" + Position [375, 2945, 405, 2975] + Value "2" + } + Block { + BlockType Constant + Name "Constant35" + SID "2801" + Position [345, 3015, 375, 3045] + } + Block { + BlockType Constant + Name "Constant36" + SID "2802" + Position [375, 3220, 405, 3250] + Value "2" + } + Block { + BlockType Constant + Name "Constant37" + SID "2803" + Position [345, 3290, 375, 3320] + } + Block { + BlockType Constant + Name "Constant38" + SID "2804" + Position [375, 3500, 405, 3530] + Value "2" + } + Block { + BlockType Constant + Name "Constant39" + SID "2805" + Position [345, 3570, 375, 3600] + } + Block { + BlockType Constant + Name "Constant40" + SID "2806" + Position [375, 3790, 405, 3820] + Value "2" + } + Block { + BlockType Constant + Name "Constant41" + SID "2807" + Position [345, 3860, 375, 3890] + } + Block { + BlockType Constant + Name "Constant42" + SID "2808" + Position [375, 4085, 405, 4115] + Value "2" + } + Block { + BlockType Constant + Name "Constant43" + SID "2809" + Position [345, 4155, 375, 4185] + } + Block { + BlockType Constant + Name "Constant44" + SID "2810" + Position [375, 4390, 405, 4420] + Value "2" + } + Block { + BlockType Constant + Name "Constant45" + SID "2811" + Position [345, 4460, 375, 4490] + } + Block { + BlockType Constant + Name "Constant46" + SID "2812" + Position [375, 4700, 405, 4730] + Value "2" + } + Block { + BlockType Constant + Name "Constant47" + SID "2813" + Position [345, 4770, 375, 4800] + } + Block { + BlockType Constant + Name "Constant48" + SID "2814" + Position [380, 5015, 410, 5045] + Value "2" + } + Block { + BlockType Constant + Name "Constant49" + SID "2815" + Position [350, 5085, 380, 5115] + } + Block { + BlockType Constant + Name "Constant50" + SID "2816" + Position [380, 5335, 410, 5365] + Value "2" + } + Block { + BlockType Constant + Name "Constant51" + SID "2817" + Position [350, 5405, 380, 5435] + } + Block { + BlockType Constant + Name "Constant52" + SID "2818" + Position [380, 5660, 410, 5690] + Value "2" + } + Block { + BlockType Constant + Name "Constant53" + SID "2819" + Position [350, 5730, 380, 5760] + } + Block { + BlockType Constant + Name "Constant8" + SID "2820" + Position [365, 330, 395, 360] + Value "2" + } + Block { + BlockType Display + Name "Display1" + SID "2821" + Ports [1] + Position [730, 507, 820, 533] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display2" + SID "2822" + Ports [1] + Position [775, 657, 865, 683] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display3" + SID "2823" + Ports [1] + Position [740, 857, 830, 883] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "2824" + Ports [1] + Position [770, 1057, 860, 1083] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display5" + SID "2825" + Ports [1] + Position [735, 332, 825, 358] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display6" + SID "2826" + Ports [1] + Position [770, 1187, 860, 1213] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display7" + SID "2827" + Ports [1] + Position [640, 197, 730, 223] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display8" + SID "2828" + Ports [1] + Position [490, 317, 580, 343] + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction1" + SID "2829" + Ports [2, 1] + Position [420, 177, 450, 208] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction10" + SID "2830" + Ports [2, 1] + Position [435, 1772, 465, 1803] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction11" + SID "2831" + Ports [2, 1] + Position [435, 1982, 465, 2013] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction12" + SID "2832" + Ports [2, 1] + Position [435, 2212, 465, 2243] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction13" + SID "2833" + Ports [2, 1] + Position [435, 2457, 465, 2488] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction14" + SID "2834" + Ports [2, 1] + Position [435, 2712, 465, 2743] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction15" + SID "2835" + Ports [2, 1] + Position [435, 2977, 465, 3008] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction16" + SID "2836" + Ports [2, 1] + Position [435, 3252, 465, 3283] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction17" + SID "2837" + Ports [2, 1] + Position [435, 3532, 465, 3563] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction18" + SID "2838" + Ports [2, 1] + Position [435, 3822, 465, 3853] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction19" + SID "2839" + Ports [2, 1] + Position [435, 4117, 465, 4148] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction2" + SID "2840" + Ports [2, 1] + Position [425, 362, 455, 393] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction20" + SID "2841" + Ports [2, 1] + Position [435, 4422, 465, 4453] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction21" + SID "2842" + Ports [2, 1] + Position [435, 4732, 465, 4763] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction22" + SID "2843" + Ports [2, 1] + Position [440, 5047, 470, 5078] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction23" + SID "2844" + Ports [2, 1] + Position [440, 5367, 470, 5398] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction24" + SID "2845" + Ports [2, 1] + Position [440, 5692, 470, 5723] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction3" + SID "2846" + Ports [2, 1] + Position [425, 512, 455, 543] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction4" + SID "2847" + Ports [2, 1] + Position [430, 672, 460, 703] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction5" + SID "2848" + Ports [2, 1] + Position [435, 842, 465, 873] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction6" + SID "2849" + Ports [2, 1] + Position [435, 1022, 465, 1053] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction7" + SID "2850" + Ports [2, 1] + Position [435, 1202, 465, 1233] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction8" + SID "2851" + Ports [2, 1] + Position [435, 1382, 465, 1413] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction9" + SID "2852" + Ports [2, 1] + Position [435, 1572, 465, 1603] + Operator "pow" + } + Block { + BlockType Product + Name "Product1" + SID "2853" + Ports [2, 1] + Position [555, 202, 585, 233] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product10" + SID "2854" + Ports [2, 1] + Position [570, 1797, 600, 1828] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product11" + SID "2855" + Ports [2, 1] + Position [570, 2007, 600, 2038] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product12" + SID "2856" + Ports [2, 1] + Position [570, 2237, 600, 2268] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product13" + SID "2857" + Ports [2, 1] + Position [570, 2482, 600, 2513] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product14" + SID "2858" + Ports [2, 1] + Position [570, 2737, 600, 2768] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product15" + SID "2859" + Ports [2, 1] + Position [570, 3002, 600, 3033] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product16" + SID "2860" + Ports [2, 1] + Position [570, 3277, 600, 3308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product17" + SID "2861" + Ports [2, 1] + Position [570, 3557, 600, 3588] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product18" + SID "2862" + Ports [2, 1] + Position [570, 3847, 600, 3878] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product19" + SID "2863" + Ports [2, 1] + Position [570, 4142, 600, 4173] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product2" + SID "2864" + Ports [2, 1] + Position [560, 387, 590, 418] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product20" + SID "2865" + Ports [2, 1] + Position [570, 4447, 600, 4478] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product21" + SID "2866" + Ports [2, 1] + Position [570, 4757, 600, 4788] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product22" + SID "2867" + Ports [2, 1] + Position [575, 5072, 605, 5103] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product23" + SID "2868" + Ports [2, 1] + Position [575, 5392, 605, 5423] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product24" + SID "2869" + Ports [2, 1] + Position [575, 5717, 605, 5748] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product3" + SID "2870" + Ports [2, 1] + Position [560, 537, 590, 568] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product4" + SID "2871" + Ports [2, 1] + Position [565, 697, 595, 728] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product5" + SID "2872" + Ports [2, 1] + Position [570, 867, 600, 898] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product6" + SID "2873" + Ports [2, 1] + Position [570, 1047, 600, 1078] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product7" + SID "2874" + Ports [2, 1] + Position [570, 1227, 600, 1258] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product8" + SID "2875" + Ports [2, 1] + Position [570, 1407, 600, 1438] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product9" + SID "2876" + Ports [2, 1] + Position [570, 1597, 600, 1628] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum1" + SID "2877" + Ports [2, 1] + Position [380, 380, 400, 400] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum10" + SID "2878" + Ports [2, 1] + Position [380, 1400, 400, 1420] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum11" + SID "2879" + Ports [2, 1] + Position [380, 1590, 400, 1610] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum12" + SID "2880" + Ports [2, 1] + Position [380, 1790, 400, 1810] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum13" + SID "2881" + Ports [2, 1] + Position [380, 2000, 400, 2020] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum14" + SID "2882" + Ports [2, 1] + Position [380, 2230, 400, 2250] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum15" + SID "2883" + Ports [2, 1] + Position [380, 2475, 400, 2495] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum16" + SID "2884" + Ports [2, 1] + Position [380, 2730, 400, 2750] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum17" + SID "2885" + Ports [2, 1] + Position [380, 2995, 400, 3015] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum18" + SID "2886" + Ports [2, 1] + Position [380, 3270, 400, 3290] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum19" + SID "2887" + Ports [2, 1] + Position [380, 3550, 400, 3570] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum20" + SID "2888" + Ports [2, 1] + Position [380, 3840, 400, 3860] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum21" + SID "2889" + Ports [2, 1] + Position [380, 4135, 400, 4155] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum22" + SID "2890" + Ports [2, 1] + Position [380, 4440, 400, 4460] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum23" + SID "2891" + Ports [2, 1] + Position [380, 4750, 400, 4770] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum24" + SID "2892" + Ports [2, 1] + Position [385, 5065, 405, 5085] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum25" + SID "2893" + Ports [2, 1] + Position [385, 5385, 405, 5405] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum26" + SID "2894" + Ports [2, 1] + Position [385, 5710, 405, 5730] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum27" + SID "2895" + Ports [24, 1] + Position [760, 3171, 820, 3479] + ShowName off + Inputs "|++++++++++++++++++++++++" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum5" + SID "2896" + Ports [2, 1] + Position [370, 530, 390, 550] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum6" + SID "2897" + Ports [2, 1] + Position [375, 690, 395, 710] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum7" + SID "2898" + Ports [2, 1] + Position [380, 860, 400, 880] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum8" + SID "2899" + Ports [2, 1] + Position [380, 1040, 400, 1060] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum9" + SID "2900" + Ports [2, 1] + Position [380, 1220, 400, 1240] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "Out1" + SID "2901" + Position [845, 3318, 875, 3332] + IconDisplay "Port number" + } + Line { + SrcBlock "Product1" + SrcPort 1 + Points [15, 0] + Branch { + Points [110, 0; 0, 3225] + DstBlock "Sum27" + DstPort 24 + } + Branch { + Points [0, -10] + DstBlock "Display7" + DstPort 1 + } + } + Line { + SrcBlock "Sum1" + SrcPort 1 + Points [0, -5] + Branch { + Points [-50, 0] + DstBlock "Sum5" + DstPort 1 + } + Branch { + Points [5, 0] + Branch { + Points [0, -55] + DstBlock "Display8" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction2" + DstPort 2 + } + } + } + Line { + SrcBlock "Constant2" + SrcPort 1 + DstBlock "Sum1" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction1" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product1" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero1" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product1" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator1" + SrcPort 1 + DstBlock "Compare\nTo Zero1" + DstPort 1 + } + Line { + SrcBlock "Constant1" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction1" + DstPort 1 + } + Line { + SrcBlock "Sum27" + SrcPort 1 + DstBlock "Out1" + DstPort 1 + } + Line { + SrcBlock "In2" + SrcPort 1 + Points [15, 0] + Branch { + Points [0, -105] + DstBlock "Bitwise\nOperator1" + DstPort 1 + } + Branch { + Points [0, 80] + Branch { + Points [0, 150] + Branch { + Points [0, 155] + Branch { + Points [0, 175] + Branch { + Points [0, 180; 5, 0] + Branch { + Points [-5, 0; 0, 175] + Branch { + Points [0, 185] + Branch { + Points [0, 190] + Branch { + Points [0, 195] + Branch { + Points [0, 215] + Branch { + Points [0, 230] + Branch { + Points [0, 240] + Branch { + Points [0, 260] + Branch { + Points [0, 265] + Branch { + Points [0, 275] + Branch { + Points [0, 280] + Branch { + Points [0, 285] + Branch { + Points [0, 300] + Branch { + Points [0, 305] + Branch { + Points [0, 310] + Branch { + Points [0, 315] + Branch { + Points [0, 320] + Branch { + Points [0, 325] + DstBlock "Bitwise\nOperator28" + DstPort 1 + } + Branch { + DstBlock "Bitwise\nOperator27" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator26" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator25" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator24" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator23" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator22" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator21" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator20" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator19" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator18" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator17" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator16" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator15" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator14" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator13" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator12" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator11" + DstPort 1 + } + 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FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "hex2float" + Location [13, 125, 1281, 839] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "2919" + Position [50, 48, 80, 62] + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "2920" + Position [25, 248, 55, 262] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In3" + SID "2921" + Position [50, 433, 80, 447] + Port "3" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In4" + SID "2922" + Position [50, 528, 80, 542] + Port "4" + IconDisplay "Port number" + } + Block { + BlockType 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"1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000010000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator13" + SID "2956" + Ports [1, 1] + Position [425, 1636, 465, 1674] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000001000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator14" + SID "2957" + Ports [1, 1] + Position [425, 1836, 465, 1874] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000100000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator15" + SID "2958" + Ports [1, 1] + Position [425, 2046, 465, 2084] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000010000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator16" + SID "2959" + Ports [1, 1] + Position [425, 2276, 465, 2314] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000001000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator17" + SID "2960" + Ports [1, 1] + Position [425, 2521, 465, 2559] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000100000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator18" + SID "2961" + Ports [1, 1] + Position [425, 2776, 465, 2814] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000010000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator19" + SID "2962" + Ports [1, 1] + Position [425, 3041, 465, 3079] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000001000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator20" + SID "2963" + Ports [1, 1] + Position [425, 3316, 465, 3354] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000100000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator21" + SID "2964" + Ports [1, 1] + Position [425, 3596, 465, 3634] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000010000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator22" + SID "2965" + Ports [1, 1] + Position [425, 3886, 465, 3924] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000001000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator23" + SID "2966" + Ports [1, 1] + Position [425, 4181, 465, 4219] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000100000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator24" + SID "2967" + Ports [1, 1] + Position [425, 4486, 465, 4524] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000010000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator25" + SID "2968" + Ports [1, 1] + Position [425, 4796, 465, 4834] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000001000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator26" + SID "2969" + Ports [1, 1] + Position [430, 5111, 470, 5149] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000100')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator27" + SID "2970" + Ports [1, 1] + Position [430, 5431, 470, 5469] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000010')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator28" + SID "2971" + Ports [1, 1] + Position [430, 5756, 470, 5794] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000001')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator6" + SID "2972" + Ports [1, 1] + Position [415, 426, 455, 464] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0010000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator7" + SID "2973" + Ports [1, 1] + Position [415, 576, 455, 614] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0001000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator8" + SID "2974" + Ports [1, 1] + Position [420, 736, 460, 774] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000100000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator9" + SID "2975" + Ports [1, 1] + Position [425, 906, 465, 944] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000010000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Compare\nTo Zero1" + SID "2976" + Ports [1, 1] + Position [480, 245, 510, 275] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero10" + SID "2977" + Ports [1, 1] + Position [495, 1840, 525, 1870] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero11" + SID "2978" + Ports [1, 1] + Position [495, 2050, 525, 2080] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero12" + SID "2979" + Ports [1, 1] + Position [495, 2280, 525, 2310] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero13" + SID "2980" + Ports [1, 1] + Position [495, 2525, 525, 2555] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero14" + SID "2981" + Ports [1, 1] + Position [495, 2780, 525, 2810] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero15" + SID "2982" + Ports [1, 1] + Position [495, 3045, 525, 3075] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero16" + SID "2983" + Ports [1, 1] + Position [495, 3320, 525, 3350] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero17" + SID "2984" + Ports [1, 1] + Position [495, 3600, 525, 3630] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero18" + SID "2985" + Ports [1, 1] + Position [495, 3890, 525, 3920] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero19" + SID "2986" + Ports [1, 1] + Position [495, 4185, 525, 4215] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero2" + SID "2987" + Ports [1, 1] + Position [485, 430, 515, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero20" + SID "2988" + Ports [1, 1] + Position [495, 4490, 525, 4520] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero21" + SID "2989" + Ports [1, 1] + Position [495, 4800, 525, 4830] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero22" + SID "2990" + Ports [1, 1] + Position [500, 5115, 530, 5145] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero23" + SID "2991" + Ports [1, 1] + Position [500, 5435, 530, 5465] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero24" + SID "2992" + Ports [1, 1] + Position [500, 5760, 530, 5790] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero3" + SID "2993" + Ports [1, 1] + Position [485, 580, 515, 610] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero4" + SID "2994" + Ports [1, 1] + Position [490, 740, 520, 770] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero5" + SID "2995" + Ports [1, 1] + Position [495, 910, 525, 940] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero6" + SID "2996" + Ports [1, 1] + Position [495, 1090, 525, 1120] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero7" + SID "2997" + Ports [1, 1] + Position [495, 1270, 525, 1300] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero8" + SID "2998" + Ports [1, 1] + Position [495, 1450, 525, 1480] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero9" + SID "2999" + Ports [1, 1] + Position [495, 1640, 525, 1670] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Constant + Name "Constant1" + SID "3000" + Position [360, 145, 390, 175] + Value "2" + } + Block { + BlockType Constant + Name "Constant10" + SID "3001" + Position [365, 480, 395, 510] + Value "2" + } + Block { + BlockType Constant + Name "Constant11" + SID "3002" + Position [335, 550, 365, 580] + } + Block { + BlockType Constant + Name "Constant12" + SID "3003" + Position [370, 640, 400, 670] + Value "2" + } + Block { + BlockType Constant + Name "Constant13" + SID "3004" + Position [340, 710, 370, 740] + } + Block { + BlockType Constant + Name "Constant14" + SID "3005" + Position [375, 810, 405, 840] + Value "2" + } + Block { + BlockType Constant + Name "Constant15" + SID "3006" + Position [345, 880, 375, 910] + } + Block { + BlockType Constant + Name "Constant16" + SID "3007" + Position [375, 990, 405, 1020] + Value "2" + } + Block { + BlockType Constant + Name "Constant17" + SID "3008" + Position [345, 1060, 375, 1090] + } + Block { + BlockType Constant + Name "Constant18" + SID "3009" + Position [375, 1170, 405, 1200] + Value "2" + } + Block { + BlockType Constant + Name "Constant19" + SID "3010" + Position [345, 1240, 375, 1270] + } + Block { + BlockType Constant + Name "Constant2" + SID "3011" + Position [345, 400, 375, 430] + } + Block { + BlockType Constant + Name "Constant20" + SID "3012" + Position [375, 1350, 405, 1380] + Value "2" + } + Block { + BlockType Constant + Name "Constant21" + SID "3013" + Position [345, 1420, 375, 1450] + } + Block { + BlockType Constant + Name "Constant22" + SID "3014" + Position [375, 1540, 405, 1570] + Value "2" + } + Block { + BlockType Constant + Name "Constant23" + SID "3015" + Position [345, 1610, 375, 1640] + } + Block { + BlockType Constant + Name "Constant24" + SID "3016" + Position [375, 1740, 405, 1770] + Value "2" + } + Block { + BlockType Constant + Name "Constant25" + SID "3017" + Position [345, 1810, 375, 1840] + } + Block { + BlockType Constant + Name "Constant26" + SID "3018" + Position [375, 1950, 405, 1980] + Value "2" + } + Block { + BlockType Constant + Name "Constant27" + SID "3019" + Position [345, 2020, 375, 2050] + } + Block { + BlockType Constant + Name "Constant28" + SID "3020" + Position [375, 2180, 405, 2210] + Value "2" + } + Block { + BlockType Constant + Name "Constant29" + SID "3021" + Position [345, 2250, 375, 2280] + } + Block { + BlockType Constant + Name "Constant30" + SID "3022" + Position [375, 2425, 405, 2455] + Value "2" + } + Block { + BlockType Constant + Name "Constant31" + SID "3023" + Position [345, 2495, 375, 2525] + } + Block { + BlockType Constant + Name "Constant32" + SID "3024" + Position [375, 2680, 405, 2710] + Value "2" + } + Block { + BlockType Constant + Name "Constant33" + SID "3025" + Position [345, 2750, 375, 2780] + } + Block { + BlockType Constant + Name "Constant34" + SID "3026" + Position [375, 2945, 405, 2975] + Value "2" + } + Block { + BlockType Constant + Name "Constant35" + SID "3027" + Position [345, 3015, 375, 3045] + } + Block { + BlockType Constant + Name "Constant36" + SID "3028" + Position [375, 3220, 405, 3250] + Value "2" + } + Block { + BlockType Constant + Name "Constant37" + SID "3029" + Position [345, 3290, 375, 3320] + } + Block { + BlockType Constant + Name "Constant38" + SID "3030" + Position [375, 3500, 405, 3530] + Value "2" + } + Block { + BlockType Constant + Name "Constant39" + SID "3031" + Position [345, 3570, 375, 3600] + } + Block { + BlockType Constant + Name "Constant40" + SID "3032" + Position [375, 3790, 405, 3820] + Value "2" + } + Block { + BlockType Constant + Name "Constant41" + SID "3033" + Position [345, 3860, 375, 3890] + } + Block { + BlockType Constant + Name "Constant42" + SID "3034" + Position [375, 4085, 405, 4115] + Value "2" + } + Block { + BlockType Constant + Name "Constant43" + SID "3035" + Position [345, 4155, 375, 4185] + } + Block { + BlockType Constant + Name "Constant44" + SID "3036" + Position [375, 4390, 405, 4420] + Value "2" + } + Block { + BlockType Constant + Name "Constant45" + SID "3037" + Position [345, 4460, 375, 4490] + } + Block { + BlockType Constant + Name "Constant46" + SID "3038" + Position [375, 4700, 405, 4730] + Value "2" + } + Block { + BlockType Constant + Name "Constant47" + SID "3039" + Position [345, 4770, 375, 4800] + } + Block { + BlockType Constant + Name "Constant48" + SID "3040" + Position [380, 5015, 410, 5045] + Value "2" + } + Block { + BlockType Constant + Name "Constant49" + SID "3041" + Position [350, 5085, 380, 5115] + } + Block { + BlockType Constant + Name "Constant50" + SID "3042" + Position [380, 5335, 410, 5365] + Value "2" + } + Block { + BlockType Constant + Name "Constant51" + SID "3043" + Position [350, 5405, 380, 5435] + } + Block { + BlockType Constant + Name "Constant52" + SID "3044" + Position [380, 5660, 410, 5690] + Value "2" + } + Block { + BlockType Constant + Name "Constant53" + SID "3045" + Position [350, 5730, 380, 5760] + } + Block { + BlockType Constant + Name "Constant8" + SID "3046" + Position [365, 330, 395, 360] + Value "2" + } + Block { + BlockType Display + Name "Display1" + SID "3047" + Ports [1] + Position [730, 507, 820, 533] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display2" + SID "3048" + Ports [1] + Position [775, 657, 865, 683] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display3" + SID "3049" + Ports [1] + Position [740, 857, 830, 883] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "3050" + Ports [1] + Position [770, 1057, 860, 1083] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display5" + SID "3051" + Ports [1] + Position [735, 332, 825, 358] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display6" + SID "3052" + Ports [1] + Position [770, 1187, 860, 1213] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display7" + SID "3053" + Ports [1] + Position [640, 197, 730, 223] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display8" + SID "3054" + Ports [1] + Position [490, 317, 580, 343] + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction1" + SID "3055" + Ports [2, 1] + Position [420, 177, 450, 208] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction10" + SID "3056" + Ports [2, 1] + Position [435, 1772, 465, 1803] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction11" + SID "3057" + Ports [2, 1] + Position [435, 1982, 465, 2013] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction12" + SID "3058" + Ports [2, 1] + Position [435, 2212, 465, 2243] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction13" + SID "3059" + Ports [2, 1] + Position [435, 2457, 465, 2488] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction14" + SID "3060" + Ports [2, 1] + Position [435, 2712, 465, 2743] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction15" + SID "3061" + Ports [2, 1] + Position [435, 2977, 465, 3008] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction16" + SID "3062" + Ports [2, 1] + Position [435, 3252, 465, 3283] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction17" + SID "3063" + Ports [2, 1] + Position [435, 3532, 465, 3563] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction18" + SID "3064" + Ports [2, 1] + Position [435, 3822, 465, 3853] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction19" + SID "3065" + Ports [2, 1] + Position [435, 4117, 465, 4148] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction2" + SID "3066" + Ports [2, 1] + Position [425, 362, 455, 393] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction20" + SID "3067" + Ports [2, 1] + Position [435, 4422, 465, 4453] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction21" + SID "3068" + Ports [2, 1] + Position [435, 4732, 465, 4763] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction22" + SID "3069" + Ports [2, 1] + Position [440, 5047, 470, 5078] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction23" + SID "3070" + Ports [2, 1] + Position [440, 5367, 470, 5398] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction24" + SID "3071" + Ports [2, 1] + Position [440, 5692, 470, 5723] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction3" + SID "3072" + Ports [2, 1] + Position [425, 512, 455, 543] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction4" + SID "3073" + Ports [2, 1] + Position [430, 672, 460, 703] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction5" + SID "3074" + Ports [2, 1] + Position [435, 842, 465, 873] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction6" + SID "3075" + Ports [2, 1] + Position [435, 1022, 465, 1053] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction7" + SID "3076" + Ports [2, 1] + Position [435, 1202, 465, 1233] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction8" + SID "3077" + Ports [2, 1] + Position [435, 1382, 465, 1413] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction9" + SID "3078" + Ports [2, 1] + Position [435, 1572, 465, 1603] + Operator "pow" + } + Block { + BlockType Product + Name "Product1" + SID "3079" + Ports [2, 1] + Position [555, 202, 585, 233] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product10" + SID "3080" + Ports [2, 1] + Position [570, 1797, 600, 1828] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product11" + SID "3081" + Ports [2, 1] + Position [570, 2007, 600, 2038] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product12" + SID "3082" + Ports [2, 1] + Position [570, 2237, 600, 2268] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product13" + SID "3083" + Ports [2, 1] + Position [570, 2482, 600, 2513] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product14" + SID "3084" + Ports [2, 1] + Position [570, 2737, 600, 2768] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product15" + SID "3085" + Ports [2, 1] + Position [570, 3002, 600, 3033] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product16" + SID "3086" + Ports [2, 1] + Position [570, 3277, 600, 3308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product17" + SID "3087" + Ports [2, 1] + Position [570, 3557, 600, 3588] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product18" + SID "3088" + Ports [2, 1] + Position [570, 3847, 600, 3878] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product19" + SID "3089" + Ports [2, 1] + Position [570, 4142, 600, 4173] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product2" + SID "3090" + Ports [2, 1] + Position [560, 387, 590, 418] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product20" + SID "3091" + Ports [2, 1] + Position [570, 4447, 600, 4478] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product21" + SID "3092" + Ports [2, 1] + Position [570, 4757, 600, 4788] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product22" + SID "3093" + Ports [2, 1] + Position [575, 5072, 605, 5103] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product23" + SID "3094" + Ports [2, 1] + Position [575, 5392, 605, 5423] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product24" + SID "3095" + Ports [2, 1] + Position [575, 5717, 605, 5748] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product3" + SID "3096" + Ports [2, 1] + Position [560, 537, 590, 568] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product4" + SID "3097" + Ports [2, 1] + Position [565, 697, 595, 728] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product5" + SID "3098" + Ports [2, 1] + Position [570, 867, 600, 898] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product6" + SID "3099" + Ports [2, 1] + Position [570, 1047, 600, 1078] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product7" + SID "3100" + Ports [2, 1] + Position [570, 1227, 600, 1258] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product8" + SID "3101" + Ports [2, 1] + Position [570, 1407, 600, 1438] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product9" + SID "3102" + Ports [2, 1] + Position [570, 1597, 600, 1628] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum1" + SID "3103" + Ports [2, 1] + Position [380, 380, 400, 400] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum10" + SID "3104" + Ports [2, 1] + Position [380, 1400, 400, 1420] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum11" + SID "3105" + Ports [2, 1] + Position [380, 1590, 400, 1610] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum12" + SID "3106" + Ports [2, 1] + Position [380, 1790, 400, 1810] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum13" + SID "3107" + Ports [2, 1] + Position [380, 2000, 400, 2020] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum14" + SID "3108" + Ports [2, 1] + Position [380, 2230, 400, 2250] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum15" + SID "3109" + Ports [2, 1] + Position [380, 2475, 400, 2495] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum16" + SID "3110" + Ports [2, 1] + Position [380, 2730, 400, 2750] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum17" + SID "3111" + Ports [2, 1] + Position [380, 2995, 400, 3015] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum18" + SID "3112" + Ports [2, 1] + Position [380, 3270, 400, 3290] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum19" + SID "3113" + Ports [2, 1] + Position [380, 3550, 400, 3570] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum20" + SID "3114" + Ports [2, 1] + Position [380, 3840, 400, 3860] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum21" + SID "3115" + Ports [2, 1] + Position [380, 4135, 400, 4155] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum22" + SID "3116" + Ports [2, 1] + Position [380, 4440, 400, 4460] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum23" + SID "3117" + Ports [2, 1] + Position [380, 4750, 400, 4770] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum24" + SID "3118" + Ports [2, 1] + Position [385, 5065, 405, 5085] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum25" + SID "3119" + Ports [2, 1] + Position [385, 5385, 405, 5405] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum26" + SID "3120" + Ports [2, 1] + Position [385, 5710, 405, 5730] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum27" + SID "3121" + Ports [24, 1] + Position [760, 3171, 820, 3479] + ShowName off + Inputs "|++++++++++++++++++++++++" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum5" + SID "3122" + Ports [2, 1] + Position [370, 530, 390, 550] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum6" + SID "3123" + Ports [2, 1] + Position [375, 690, 395, 710] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum7" + SID "3124" + Ports [2, 1] + Position [380, 860, 400, 880] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum8" + SID "3125" + Ports [2, 1] + Position [380, 1040, 400, 1060] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum9" + SID "3126" + Ports [2, 1] + Position [380, 1220, 400, 1240] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "Out1" + SID "3127" + Position [845, 3318, 875, 3332] + IconDisplay "Port number" + } + Line { + SrcBlock "Constant8" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction2" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator6" + SrcPort 1 + DstBlock "Compare\nTo Zero2" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero2" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product2" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction2" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product2" + DstPort 1 + } + Line { + SrcBlock "Constant10" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction3" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator7" + SrcPort 1 + DstBlock "Compare\nTo Zero3" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero3" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product3" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction3" + SrcPort 1 + Points [40, 0; 0, 15] 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} + Branch { + Points [-5, 0; 0, 175] + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator11" + DstPort 1 + } + Branch { + Points [0, 185] + Branch { + DstBlock "Bitwise\nOperator12" + DstPort 1 + } + Branch { + Points [0, 190] + Branch { + DstBlock "Bitwise\nOperator13" + DstPort 1 + } + Branch { + Points [0, 195] + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator14" + DstPort 1 + } + Branch { + Points [0, 215] + Branch { + DstBlock "Bitwise\nOperator15" + DstPort 1 + } + Branch { + Points [0, 230] + Branch { + DstBlock "Bitwise\nOperator16" + DstPort 1 + } + Branch { + Points [0, 240] + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator17" + DstPort 1 + } + Branch { + Points [0, 260] + Branch { + DstBlock "Bitwise\nOperator18" + DstPort 1 + } + Branch { + Points [0, 265] + Branch { + DstBlock "Bitwise\nOperator19" + DstPort 1 + } + Branch { + Points [0, 275] + Branch { + DstBlock "Bitwise\nOperator20" + DstPort 1 + } + Branch { + Points [0, 280] + Branch { + DstBlock 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Position [670, 290, 690, 310] + ShowName off + IconShape "round" + Inputs "|++" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum1" + SID "3129" + Ports [3, 1] + Position [845, 400, 875, 430] + ShowName off + IconShape "round" + Inputs "|+++|" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum2" + SID "3130" + Ports [2, 1] + Position [880, 235, 900, 255] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum3" + SID "3131" + Ports [2, 1] + Position [945, 625, 965, 645] + ShowName off + IconShape "round" + Inputs "|++" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name 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DstPort 1 + } + Line { + SrcBlock "Data Type Conversion5" + SrcPort 1 + Points [75, 0] + DstBlock "Sum3" + DstPort 2 + } + Line { + SrcBlock "Subsystem" + SrcPort 1 + Points [25, 0; 0, -30; 5, 0; 0, -50] + DstBlock "Product" + DstPort 2 + } + Line { + SrcBlock "Constant7" + SrcPort 1 + Points [20, 0; 0, 50] + DstBlock "Math\nFunction" + DstPort 1 + } + Line { + SrcBlock "Data Type Conversion7" + SrcPort 1 + Points [60, 0] + DstBlock "Math\nFunction" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction" + SrcPort 1 + Points [175, 0; 0, 165] + DstBlock "Product" + DstPort 1 + } + Line { + SrcBlock "In1" + SrcPort 1 + DstBlock "Data Type Conversion" + DstPort 1 + } + Line { + SrcBlock "Product" + SrcPort 1 + DstBlock "Out1" + DstPort 1 + } + Line { + SrcBlock "In3" + SrcPort 1 + DstBlock "Data Type Conversion3" + DstPort 1 + } + Line { + SrcBlock "In4" + SrcPort 1 + DstBlock "Data Type Conversion4" + DstPort 1 + } + } + } + Block { + BlockType Outport + Name "d_L_Q" + SID "3133" + Position [440, 113, 470, 127] + IconDisplay "Port number" + OutputWhenDisabled "reset" + InitialOutput "0" + } + Line { + SrcBlock "Data Type \nConversion5" + SrcPort 1 + DstBlock "d_L_Q" + DstPort 1 + } + Line { + SrcBlock "hex2float" + SrcPort 1 + DstBlock "Data Type \nConversion5" + DstPort 1 + } + Line { + SrcBlock "Data Type \nConversion4" + SrcPort 1 + DstBlock "hex2float" + DstPort 1 + } + Line { + SrcBlock "Data Type \nConversion1" + SrcPort 1 + DstBlock "hex2float" + DstPort 2 + } + Line { + SrcBlock "Data Type \nConversion2" + SrcPort 1 + DstBlock "hex2float" + DstPort 3 + } + Line { + SrcBlock "Data Type \nConversion3" + SrcPort 1 + DstBlock "hex2float" + DstPort 4 + } + Line { + SrcBlock "In4" + SrcPort 1 + DstBlock "Data Type \nConversion4" + DstPort 1 + } + Line { + SrcBlock "In3" + SrcPort 1 + DstBlock "Data Type \nConversion1" + DstPort 1 + } + Line { + SrcBlock "In2" + SrcPort 1 + DstBlock "Data Type \nConversion2" + DstPort 1 + } + Line { + SrcBlock "In1" + SrcPort 1 + DstBlock "Data Type \nConversion3" + DstPort 1 + } + } + } + Block { + BlockType SubSystem + Name "Subsystem4" + SID "3134" + Ports [4, 1] + Position [525, 1516, 630, 1684] + ShowName off + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "Subsystem4" + Location [528, 347, 1021, 603] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "3135" + Position [25, 178, 55, 192] + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "3136" + Position [25, 133, 55, 147] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In3" + SID "3137" + Position [25, 88, 55, 102] + Port "3" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In4" + SID "3138" + Position [25, 43, 55, 57] + Port "4" + IconDisplay "Port number" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion1" + SID "3139" + Position [100, 75, 140, 115] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion2" + SID "3140" + Position [100, 120, 140, 160] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion3" + SID "3141" + Position [100, 165, 140, 205] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion4" + SID "3142" + Position [100, 30, 140, 70] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion5" + SID "3143" + Position [365, 100, 405, 140] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType SubSystem + Name "hex2float" + SID "3144" + Ports [4, 1] + Position [190, 25, 320, 210] + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "hex2float" + Location [13, 125, 1281, 839] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "3145" + Position [50, 48, 80, 62] + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "3146" + Position [25, 248, 55, 262] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In3" + SID "3147" + Position [50, 433, 80, 447] + Port "3" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In4" + SID "3148" + Position [50, 528, 80, 542] + Port "4" + IconDisplay "Port number" + } + Block { + BlockType Reference + Name "Bitwise\nOperator" + SID "3149" + Ports [1, 1] + Position [375, 161, 415, 199] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('01111111')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator1" + SID "3150" + Ports [1, 1] + Position [255, 251, 295, 289] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('10000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator2" + SID "3151" + Ports [1, 1] + Position [285, 26, 325, 64] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('10000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator3" + SID "3152" + Ports [1, 1] + Position [255, 336, 295, 374] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('01111111')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Constant + Name "Constant4" + SID "3153" + Position [855, 280, 885, 310] + Value "127" + } + Block { + BlockType Constant + Name "Constant5" + SID "3154" + Position [650, 655, 740, 685] + Value "8388608" + } + Block { + BlockType Constant + Name "Constant7" + SID "3155" + Position [740, 45, 770, 75] + Value "-1" + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion" + SID "3156" + Position [105, 38, 180, 72] + OutDataTypeStr "uint8" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion1" + SID "3157" + Position [105, 238, 180, 272] + OutDataTypeStr "uint8" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion2" + SID "3158" + Position [110, 333, 185, 367] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion3" + SID "3159" + Position [105, 423, 180, 457] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion4" + SID "3160" + Position [105, 518, 180, 552] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion5" + SID "3161" + Position [800, 653, 875, 687] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion7" + SID "3162" + Position [670, 118, 745, 152] + OutDataTypeStr "double" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Display + Name "Display3" + SID "3163" + Ports [1] + Position [460, 162, 550, 188] + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "3164" + Ports [1] + Position [670, 217, 760, 243] + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Exponent" + SID "3165" + Ports [1] + Position [715, 282, 805, 308] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Mantissa" + SID "3166" + Ports [1] + Position [1015, 558, 1295, 592] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction" + SID "3167" + Ports [2, 1] + Position [825, 102, 855, 133] + Operator "pow" + } + Block { + BlockType Product + Name "Product" + SID "3168" + Ports [2, 1] + Position [1225, 277, 1255, 308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Reference + Name "Shift\nArithmetic" + SID "3169" + Ports [1, 1] + Position [565, 215, 645, 255] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-1" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic1" + SID "3170" + Ports [1, 1] + Position [335, 255, 415, 295] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "7" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic2" + SID "3171" + Ports [1, 1] + Position [360, 25, 440, 65] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "7" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic3" + SID "3172" + Ports [1, 1] + Position [370, 335, 450, 375] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-16" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic4" + SID "3173" + Ports [1, 1] + Position [375, 420, 455, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-8" + nBinPtShiftRight "0" + } + Block { + BlockType Display + Name "Sign" + SID "3174" + Ports [1] + Position [480, 32, 570, 58] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType SubSystem + Name "Subsystem" + SID "3175" + Ports [2, 1] + Position [1125, 350, 1165, 410] + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "Subsystem" + Location [2, 82, 1653, 1004] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "3176" + Position [25, 235, 55, 250] + BlockRotation 270 + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "3177" + Position [220, 358, 250, 372] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Reference + Name "Bitwise\nOperator1" + SID "3178" + Ports [1, 1] + Position [410, 241, 450, 279] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0100000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator10" + SID "3179" + Ports [1, 1] + Position [425, 1086, 465, 1124] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000001000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator11" + SID "3180" + Ports [1, 1] + Position [425, 1266, 465, 1304] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000100000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator12" + SID "3181" + Ports [1, 1] + Position [425, 1446, 465, 1484] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000010000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator13" + SID "3182" + Ports [1, 1] + Position [425, 1636, 465, 1674] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000001000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator14" + SID "3183" + Ports [1, 1] + Position [425, 1836, 465, 1874] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000100000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator15" + SID "3184" + Ports [1, 1] + Position [425, 2046, 465, 2084] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000010000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator16" + SID "3185" + Ports [1, 1] + Position [425, 2276, 465, 2314] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000001000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator17" + SID "3186" + Ports [1, 1] + Position [425, 2521, 465, 2559] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000100000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator18" + SID "3187" + Ports [1, 1] + Position [425, 2776, 465, 2814] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000010000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator19" + SID "3188" + Ports [1, 1] + Position [425, 3041, 465, 3079] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000001000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator20" + SID "3189" + Ports [1, 1] + Position [425, 3316, 465, 3354] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000100000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator21" + SID "3190" + Ports [1, 1] + Position [425, 3596, 465, 3634] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000010000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator22" + SID "3191" + Ports [1, 1] + Position [425, 3886, 465, 3924] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000001000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator23" + SID "3192" + Ports [1, 1] + Position [425, 4181, 465, 4219] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000100000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator24" + SID "3193" + Ports [1, 1] + Position [425, 4486, 465, 4524] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000010000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator25" + SID "3194" + Ports [1, 1] + Position [425, 4796, 465, 4834] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000001000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator26" + SID "3195" + Ports [1, 1] + Position [430, 5111, 470, 5149] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000100')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator27" + SID "3196" + Ports [1, 1] + Position [430, 5431, 470, 5469] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000010')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator28" + SID "3197" + Ports [1, 1] + Position [430, 5756, 470, 5794] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000001')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator6" + SID "3198" + Ports [1, 1] + Position [415, 426, 455, 464] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0010000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator7" + SID "3199" + Ports [1, 1] + Position [415, 576, 455, 614] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0001000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator8" + SID "3200" + Ports [1, 1] + Position [420, 736, 460, 774] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000100000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator9" + SID "3201" + Ports [1, 1] + Position [425, 906, 465, 944] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000010000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Compare\nTo Zero1" + SID "3202" + Ports [1, 1] + Position [480, 245, 510, 275] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero10" + SID "3203" + Ports [1, 1] + Position [495, 1840, 525, 1870] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero11" + SID "3204" + Ports [1, 1] + Position [495, 2050, 525, 2080] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero12" + SID "3205" + Ports [1, 1] + Position [495, 2280, 525, 2310] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero13" + SID "3206" + Ports [1, 1] + Position [495, 2525, 525, 2555] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero14" + SID "3207" + Ports [1, 1] + Position [495, 2780, 525, 2810] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero15" + SID "3208" + Ports [1, 1] + Position [495, 3045, 525, 3075] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero16" + SID "3209" + Ports [1, 1] + Position [495, 3320, 525, 3350] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero17" + SID "3210" + Ports [1, 1] + Position [495, 3600, 525, 3630] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero18" + SID "3211" + Ports [1, 1] + Position [495, 3890, 525, 3920] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero19" + SID "3212" + Ports [1, 1] + Position [495, 4185, 525, 4215] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero2" + SID "3213" + Ports [1, 1] + Position [485, 430, 515, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero20" + SID "3214" + Ports [1, 1] + Position [495, 4490, 525, 4520] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero21" + SID "3215" + Ports [1, 1] + Position [495, 4800, 525, 4830] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero22" + SID "3216" + Ports [1, 1] + Position [500, 5115, 530, 5145] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero23" + SID "3217" + Ports [1, 1] + Position [500, 5435, 530, 5465] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero24" + SID "3218" + Ports [1, 1] + Position [500, 5760, 530, 5790] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero3" + SID "3219" + Ports [1, 1] + Position [485, 580, 515, 610] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero4" + SID "3220" + Ports [1, 1] + Position [490, 740, 520, 770] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero5" + SID "3221" + Ports [1, 1] + Position [495, 910, 525, 940] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero6" + SID "3222" + Ports [1, 1] + Position [495, 1090, 525, 1120] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero7" + SID "3223" + Ports [1, 1] + Position [495, 1270, 525, 1300] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero8" + SID "3224" + Ports [1, 1] + Position [495, 1450, 525, 1480] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero9" + SID "3225" + Ports [1, 1] + Position [495, 1640, 525, 1670] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Constant + Name "Constant1" + SID "3226" + Position [360, 145, 390, 175] + Value "2" + } + Block { + BlockType Constant + Name "Constant10" + SID "3227" + Position [365, 480, 395, 510] + Value "2" + } + Block { + BlockType Constant + Name "Constant11" + SID "3228" + Position [335, 550, 365, 580] + } + Block { + BlockType Constant + Name "Constant12" + SID "3229" + Position [370, 640, 400, 670] + Value "2" + } + Block { + BlockType Constant + Name "Constant13" + SID "3230" + Position [340, 710, 370, 740] + } + Block { + BlockType Constant + Name "Constant14" + SID "3231" + Position [375, 810, 405, 840] + Value "2" + } + Block { + BlockType Constant + Name "Constant15" + SID "3232" + Position [345, 880, 375, 910] + } + Block { + BlockType Constant + Name "Constant16" + SID "3233" + Position [375, 990, 405, 1020] + Value "2" + } + Block { + BlockType Constant + Name "Constant17" + SID "3234" + Position [345, 1060, 375, 1090] + } + Block { + BlockType Constant + Name "Constant18" + SID "3235" + Position [375, 1170, 405, 1200] + Value "2" + } + Block { + BlockType Constant + Name "Constant19" + SID "3236" + Position [345, 1240, 375, 1270] + } + Block { + BlockType Constant + Name "Constant2" + SID "3237" + Position [345, 400, 375, 430] + } + Block { + BlockType Constant + Name "Constant20" + SID "3238" + Position [375, 1350, 405, 1380] + Value "2" + } + Block { + BlockType Constant + Name "Constant21" + SID "3239" + Position [345, 1420, 375, 1450] + } + Block { + BlockType Constant + Name "Constant22" + SID "3240" + Position [375, 1540, 405, 1570] + Value "2" + } + Block { + BlockType Constant + Name "Constant23" + SID "3241" + Position [345, 1610, 375, 1640] + } + Block { + BlockType Constant + Name "Constant24" + SID "3242" + Position [375, 1740, 405, 1770] + Value "2" + } + Block { + BlockType Constant + Name "Constant25" + SID "3243" + Position [345, 1810, 375, 1840] + } + Block { + BlockType Constant + Name "Constant26" + SID "3244" + Position [375, 1950, 405, 1980] + Value "2" + } + Block { + BlockType Constant + Name "Constant27" + SID "3245" + Position [345, 2020, 375, 2050] + } + Block { + BlockType Constant + Name "Constant28" + SID "3246" + Position [375, 2180, 405, 2210] + Value "2" + } + Block { + BlockType Constant + Name "Constant29" + SID "3247" + Position [345, 2250, 375, 2280] + } + Block { + BlockType Constant + Name "Constant30" + SID "3248" + Position [375, 2425, 405, 2455] + Value "2" + } + Block { + BlockType Constant + Name "Constant31" + SID "3249" + Position [345, 2495, 375, 2525] + } + Block { + BlockType Constant + Name "Constant32" + SID "3250" + Position [375, 2680, 405, 2710] + Value "2" + } + Block { + BlockType Constant + Name "Constant33" + SID "3251" + Position [345, 2750, 375, 2780] + } + Block { + BlockType Constant + Name "Constant34" + SID "3252" + Position [375, 2945, 405, 2975] + Value "2" + } + Block { + BlockType Constant + Name "Constant35" + SID "3253" + Position [345, 3015, 375, 3045] + } + Block { + BlockType Constant + Name "Constant36" + SID "3254" + Position [375, 3220, 405, 3250] + Value "2" + } + Block { + BlockType Constant + Name "Constant37" + SID "3255" + Position [345, 3290, 375, 3320] + } + Block { + BlockType Constant + Name "Constant38" + SID "3256" + Position [375, 3500, 405, 3530] + Value "2" + } + Block { + BlockType Constant + Name "Constant39" + SID "3257" + Position [345, 3570, 375, 3600] + } + Block { + BlockType Constant + Name "Constant40" + SID "3258" + Position [375, 3790, 405, 3820] + Value "2" + } + Block { + BlockType Constant + Name "Constant41" + SID "3259" + Position [345, 3860, 375, 3890] + } + Block { + BlockType Constant + Name "Constant42" + SID "3260" + Position [375, 4085, 405, 4115] + Value "2" + } + Block { + BlockType Constant + Name "Constant43" + SID "3261" + Position [345, 4155, 375, 4185] + } + Block { + BlockType Constant + Name "Constant44" + SID "3262" + Position [375, 4390, 405, 4420] + Value "2" + } + Block { + BlockType Constant + Name "Constant45" + SID "3263" + Position [345, 4460, 375, 4490] + } + Block { + BlockType Constant + Name "Constant46" + SID "3264" + Position [375, 4700, 405, 4730] + Value "2" + } + Block { + BlockType Constant + Name "Constant47" + SID "3265" + Position [345, 4770, 375, 4800] + } + Block { + BlockType Constant + Name "Constant48" + SID "3266" + Position [380, 5015, 410, 5045] + Value "2" + } + Block { + BlockType Constant + Name "Constant49" + SID "3267" + Position [350, 5085, 380, 5115] + } + Block { + BlockType Constant + Name "Constant50" + SID "3268" + Position [380, 5335, 410, 5365] + Value "2" + } + Block { + BlockType Constant + Name "Constant51" + SID "3269" + Position [350, 5405, 380, 5435] + } + Block { + BlockType Constant + Name "Constant52" + SID "3270" + Position [380, 5660, 410, 5690] + Value "2" + } + Block { + BlockType Constant + Name "Constant53" + SID "3271" + Position [350, 5730, 380, 5760] + } + Block { + BlockType Constant + Name "Constant8" + SID "3272" + Position [365, 330, 395, 360] + Value "2" + } + Block { + BlockType Display + Name "Display1" + SID "3273" + Ports [1] + Position [730, 507, 820, 533] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display2" + SID "3274" + Ports [1] + Position [775, 657, 865, 683] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display3" + SID "3275" + Ports [1] + Position [740, 857, 830, 883] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "3276" + Ports [1] + Position [770, 1057, 860, 1083] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display5" + SID "3277" + Ports [1] + Position [735, 332, 825, 358] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display6" + SID "3278" + Ports [1] + Position [770, 1187, 860, 1213] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display7" + SID "3279" + Ports [1] + Position [640, 197, 730, 223] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display8" + SID "3280" + Ports [1] + Position [490, 317, 580, 343] + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction1" + SID "3281" + Ports [2, 1] + Position [420, 177, 450, 208] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction10" + SID "3282" + Ports [2, 1] + Position [435, 1772, 465, 1803] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction11" + SID "3283" + Ports [2, 1] + Position [435, 1982, 465, 2013] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction12" + SID "3284" + Ports [2, 1] + Position [435, 2212, 465, 2243] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction13" + SID "3285" + Ports [2, 1] + Position [435, 2457, 465, 2488] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction14" + SID "3286" + Ports [2, 1] + Position [435, 2712, 465, 2743] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction15" + SID "3287" + Ports [2, 1] + Position [435, 2977, 465, 3008] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction16" + SID "3288" + Ports [2, 1] + Position [435, 3252, 465, 3283] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction17" + SID "3289" + Ports [2, 1] + Position [435, 3532, 465, 3563] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction18" + SID "3290" + Ports [2, 1] + Position [435, 3822, 465, 3853] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction19" + SID "3291" + Ports [2, 1] + Position [435, 4117, 465, 4148] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction2" + SID "3292" + Ports [2, 1] + Position [425, 362, 455, 393] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction20" + SID "3293" + Ports [2, 1] + Position [435, 4422, 465, 4453] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction21" + SID "3294" + Ports [2, 1] + Position [435, 4732, 465, 4763] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction22" + SID "3295" + Ports [2, 1] + Position [440, 5047, 470, 5078] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction23" + SID "3296" + Ports [2, 1] + Position [440, 5367, 470, 5398] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction24" + SID "3297" + Ports [2, 1] + Position [440, 5692, 470, 5723] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction3" + SID "3298" + Ports [2, 1] + Position [425, 512, 455, 543] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction4" + SID "3299" + Ports [2, 1] + Position [430, 672, 460, 703] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction5" + SID "3300" + Ports [2, 1] + Position [435, 842, 465, 873] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction6" + SID "3301" + Ports [2, 1] + Position [435, 1022, 465, 1053] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction7" + SID "3302" + Ports [2, 1] + Position [435, 1202, 465, 1233] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction8" + SID "3303" + Ports [2, 1] + Position [435, 1382, 465, 1413] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction9" + SID "3304" + Ports [2, 1] + Position [435, 1572, 465, 1603] + Operator "pow" + } + Block { + BlockType Product + Name "Product1" + SID "3305" + Ports [2, 1] + Position [555, 202, 585, 233] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product10" + SID "3306" + Ports [2, 1] + Position [570, 1797, 600, 1828] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product11" + SID "3307" + Ports [2, 1] + Position [570, 2007, 600, 2038] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product12" + SID "3308" + Ports [2, 1] + Position [570, 2237, 600, 2268] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product13" + SID "3309" + Ports [2, 1] + Position [570, 2482, 600, 2513] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product14" + SID "3310" + Ports [2, 1] + Position [570, 2737, 600, 2768] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product15" + SID "3311" + Ports [2, 1] + Position [570, 3002, 600, 3033] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product16" + SID "3312" + Ports [2, 1] + Position [570, 3277, 600, 3308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product17" + SID "3313" + Ports [2, 1] + Position [570, 3557, 600, 3588] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product18" + SID "3314" + Ports [2, 1] + Position [570, 3847, 600, 3878] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product19" + SID "3315" + Ports [2, 1] + Position [570, 4142, 600, 4173] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product2" + SID "3316" + Ports [2, 1] + Position [560, 387, 590, 418] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product20" + SID "3317" + Ports [2, 1] + Position [570, 4447, 600, 4478] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product21" + SID "3318" + Ports [2, 1] + Position [570, 4757, 600, 4788] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product22" + SID "3319" + Ports [2, 1] + Position [575, 5072, 605, 5103] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product23" + SID "3320" + Ports [2, 1] + Position [575, 5392, 605, 5423] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product24" + SID "3321" + Ports [2, 1] + Position [575, 5717, 605, 5748] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product3" + SID "3322" + Ports [2, 1] + Position [560, 537, 590, 568] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product4" + SID "3323" + Ports [2, 1] + Position [565, 697, 595, 728] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product5" + SID "3324" + Ports [2, 1] + Position [570, 867, 600, 898] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product6" + SID "3325" + Ports [2, 1] + Position [570, 1047, 600, 1078] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product7" + SID "3326" + Ports [2, 1] + Position [570, 1227, 600, 1258] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product8" + SID "3327" + Ports [2, 1] + Position [570, 1407, 600, 1438] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product9" + SID "3328" + Ports [2, 1] + Position [570, 1597, 600, 1628] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum1" + SID "3329" + Ports [2, 1] + Position [380, 380, 400, 400] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum10" + SID "3330" + Ports [2, 1] + Position [380, 1400, 400, 1420] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum11" + SID "3331" + Ports [2, 1] + Position [380, 1590, 400, 1610] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum12" + SID "3332" + Ports [2, 1] + Position [380, 1790, 400, 1810] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum13" + SID "3333" + Ports [2, 1] + Position [380, 2000, 400, 2020] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum14" + SID "3334" + Ports [2, 1] + Position [380, 2230, 400, 2250] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum15" + SID "3335" + Ports [2, 1] + Position [380, 2475, 400, 2495] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum16" + SID "3336" + Ports [2, 1] + Position [380, 2730, 400, 2750] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum17" + SID "3337" + Ports [2, 1] + Position [380, 2995, 400, 3015] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum18" + SID "3338" + Ports [2, 1] + Position [380, 3270, 400, 3290] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum19" + SID "3339" + Ports [2, 1] + Position [380, 3550, 400, 3570] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum20" + SID "3340" + Ports [2, 1] + Position [380, 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SID "3344" + Ports [2, 1] + Position [385, 5065, 405, 5085] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum25" + SID "3345" + Ports [2, 1] + Position [385, 5385, 405, 5405] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum26" + SID "3346" + Ports [2, 1] + Position [385, 5710, 405, 5730] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum27" + SID "3347" + Ports [24, 1] + Position [760, 3171, 820, 3479] + ShowName off + Inputs "|++++++++++++++++++++++++" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off 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{ + BlockType Constant + Name "Constant4" + SID "3379" + Position [855, 280, 885, 310] + Value "127" + } + Block { + BlockType Constant + Name "Constant5" + SID "3380" + Position [650, 655, 740, 685] + Value "8388608" + } + Block { + BlockType Constant + Name "Constant7" + SID "3381" + Position [740, 45, 770, 75] + Value "-1" + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion" + SID "3382" + Position [105, 38, 180, 72] + OutDataTypeStr "uint8" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion1" + SID "3383" + Position [105, 238, 180, 272] + OutDataTypeStr "uint8" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion2" + SID "3384" + Position [110, 333, 185, 367] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion3" + SID "3385" + Position [105, 423, 180, 457] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion4" + SID "3386" + Position [105, 518, 180, 552] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion5" + SID "3387" + Position [800, 653, 875, 687] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion7" + SID "3388" + Position [670, 118, 745, 152] + OutDataTypeStr "double" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Display + Name "Display3" + SID "3389" + Ports [1] + Position [460, 162, 550, 188] + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "3390" + Ports [1] + Position [670, 217, 760, 243] + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Exponent" + SID "3391" + Ports [1] + Position [715, 282, 805, 308] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Mantissa" + SID "3392" + Ports [1] + Position [1015, 558, 1295, 592] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction" + SID "3393" + Ports [2, 1] + Position [825, 102, 855, 133] + Operator "pow" + } + Block { + BlockType Product + Name "Product" + SID "3394" + Ports [2, 1] + Position [1225, 277, 1255, 308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Reference + Name "Shift\nArithmetic" + SID "3395" + Ports [1, 1] + Position [565, 215, 645, 255] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-1" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic1" + SID "3396" + Ports [1, 1] + Position [335, 255, 415, 295] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "7" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic2" + SID "3397" + Ports [1, 1] + Position [360, 25, 440, 65] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "7" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic3" + SID "3398" + Ports [1, 1] + Position [370, 335, 450, 375] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-16" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic4" + SID "3399" + Ports [1, 1] + Position [375, 420, 455, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-8" + nBinPtShiftRight "0" + } + Block { + BlockType Display + Name "Sign" + SID "3400" + Ports [1] + Position [480, 32, 570, 58] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType SubSystem + Name "Subsystem" + SID "3401" + Ports [2, 1] + Position [1125, 350, 1165, 410] + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "Subsystem" + Location [2, 82, 1653, 1004] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "3402" + Position [25, 235, 55, 250] + BlockRotation 270 + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "3403" + Position [220, 358, 250, 372] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Reference + Name "Bitwise\nOperator1" + SID "3404" + Ports [1, 1] + Position [410, 241, 450, 279] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0100000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator10" + SID "3405" + Ports [1, 1] + Position [425, 1086, 465, 1124] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000001000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator11" + SID "3406" + Ports [1, 1] + Position [425, 1266, 465, 1304] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000100000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator12" + SID "3407" + Ports [1, 1] + Position [425, 1446, 465, 1484] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000010000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator13" + SID "3408" + Ports [1, 1] + Position [425, 1636, 465, 1674] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000001000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator14" + SID "3409" + Ports [1, 1] + Position [425, 1836, 465, 1874] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000100000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator15" + SID "3410" + Ports [1, 1] + Position [425, 2046, 465, 2084] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000010000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator16" + SID "3411" + Ports [1, 1] + Position [425, 2276, 465, 2314] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000001000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator17" + SID "3412" + Ports [1, 1] + Position [425, 2521, 465, 2559] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000100000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator18" + SID "3413" + Ports [1, 1] + Position [425, 2776, 465, 2814] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000010000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator19" + SID "3414" + Ports [1, 1] + Position [425, 3041, 465, 3079] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000001000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator20" + SID "3415" + Ports [1, 1] + Position [425, 3316, 465, 3354] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000100000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator21" + SID "3416" + Ports [1, 1] + Position [425, 3596, 465, 3634] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000010000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator22" + SID "3417" + Ports [1, 1] + Position [425, 3886, 465, 3924] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000001000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator23" + SID "3418" + Ports [1, 1] + Position [425, 4181, 465, 4219] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000100000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator24" + SID "3419" + Ports [1, 1] + Position [425, 4486, 465, 4524] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000010000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator25" + SID "3420" + Ports [1, 1] + Position [425, 4796, 465, 4834] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000001000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator26" + SID "3421" + Ports [1, 1] + Position [430, 5111, 470, 5149] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000100')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator27" + SID "3422" + Ports [1, 1] + Position [430, 5431, 470, 5469] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000010')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator28" + SID "3423" + Ports [1, 1] + Position [430, 5756, 470, 5794] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000001')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator6" + SID "3424" + Ports [1, 1] + Position [415, 426, 455, 464] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0010000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator7" + SID "3425" + Ports [1, 1] + Position [415, 576, 455, 614] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0001000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator8" + SID "3426" + Ports [1, 1] + Position [420, 736, 460, 774] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000100000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator9" + SID "3427" + Ports [1, 1] + Position [425, 906, 465, 944] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000010000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Compare\nTo Zero1" + SID "3428" + Ports [1, 1] + Position [480, 245, 510, 275] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero10" + SID "3429" + Ports [1, 1] + Position [495, 1840, 525, 1870] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero11" + SID "3430" + Ports [1, 1] + Position [495, 2050, 525, 2080] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero12" + SID "3431" + Ports [1, 1] + Position [495, 2280, 525, 2310] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero13" + SID "3432" + Ports [1, 1] + Position [495, 2525, 525, 2555] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero14" + SID "3433" + Ports [1, 1] + Position [495, 2780, 525, 2810] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero15" + SID "3434" + Ports [1, 1] + Position [495, 3045, 525, 3075] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero16" + SID "3435" + Ports [1, 1] + Position [495, 3320, 525, 3350] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero17" + SID "3436" + Ports [1, 1] + Position [495, 3600, 525, 3630] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero18" + SID "3437" + Ports [1, 1] + Position [495, 3890, 525, 3920] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero19" + SID "3438" + Ports [1, 1] + Position [495, 4185, 525, 4215] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero2" + SID "3439" + Ports [1, 1] + Position [485, 430, 515, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero20" + SID "3440" + Ports [1, 1] + Position [495, 4490, 525, 4520] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero21" + SID "3441" + Ports [1, 1] + Position [495, 4800, 525, 4830] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero22" + SID "3442" + Ports [1, 1] + Position [500, 5115, 530, 5145] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero23" + SID "3443" + Ports [1, 1] + Position [500, 5435, 530, 5465] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero24" + SID "3444" + Ports [1, 1] + Position [500, 5760, 530, 5790] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero3" + SID "3445" + Ports [1, 1] + Position [485, 580, 515, 610] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero4" + SID "3446" + Ports [1, 1] + Position [490, 740, 520, 770] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero5" + SID "3447" + Ports [1, 1] + Position [495, 910, 525, 940] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero6" + SID "3448" + Ports [1, 1] + Position [495, 1090, 525, 1120] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero7" + SID "3449" + Ports [1, 1] + Position [495, 1270, 525, 1300] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero8" + SID "3450" + Ports [1, 1] + Position [495, 1450, 525, 1480] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero9" + SID "3451" + Ports [1, 1] + Position [495, 1640, 525, 1670] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Constant + Name "Constant1" + SID "3452" + Position [360, 145, 390, 175] + Value "2" + } + Block { + BlockType Constant + Name "Constant10" + SID "3453" + Position [365, 480, 395, 510] + Value "2" + } + Block { + BlockType Constant + Name "Constant11" + SID "3454" + Position [335, 550, 365, 580] + } + Block { + BlockType Constant + Name "Constant12" + SID "3455" + Position [370, 640, 400, 670] + Value "2" + } + Block { + BlockType Constant + Name "Constant13" + SID "3456" + Position [340, 710, 370, 740] + } + Block { + BlockType Constant + Name "Constant14" + SID "3457" + Position [375, 810, 405, 840] + Value "2" + } + Block { + BlockType Constant + Name "Constant15" + SID "3458" + Position [345, 880, 375, 910] + } + Block { + BlockType Constant + Name "Constant16" + SID "3459" + Position [375, 990, 405, 1020] + Value "2" + } + Block { + BlockType Constant + Name "Constant17" + SID "3460" + Position [345, 1060, 375, 1090] + } + Block { + BlockType Constant + Name "Constant18" + SID "3461" + Position [375, 1170, 405, 1200] + Value "2" + } + Block { + BlockType Constant + Name "Constant19" + SID "3462" + Position [345, 1240, 375, 1270] + } + Block { + BlockType Constant + Name "Constant2" + SID "3463" + Position [345, 400, 375, 430] + } + Block { + BlockType Constant + Name "Constant20" + SID "3464" + Position [375, 1350, 405, 1380] + Value "2" + } + Block { + BlockType Constant + Name "Constant21" + SID "3465" + Position [345, 1420, 375, 1450] + } + Block { + BlockType Constant + Name "Constant22" + SID "3466" + Position [375, 1540, 405, 1570] + Value "2" + } + Block { + BlockType Constant + Name "Constant23" + SID "3467" + Position [345, 1610, 375, 1640] + } + Block { + BlockType Constant + Name "Constant24" + SID "3468" + Position [375, 1740, 405, 1770] + Value "2" + } + Block { + BlockType Constant + Name "Constant25" + SID "3469" + Position [345, 1810, 375, 1840] + } + Block { + BlockType Constant + Name "Constant26" + SID "3470" + Position [375, 1950, 405, 1980] + Value "2" + } + Block { + BlockType Constant + Name "Constant27" + SID "3471" + Position [345, 2020, 375, 2050] + } + Block { + BlockType Constant + Name "Constant28" + SID "3472" + Position [375, 2180, 405, 2210] + Value "2" + } + Block { + BlockType Constant + Name "Constant29" + SID "3473" + Position [345, 2250, 375, 2280] + } + Block { + BlockType Constant + Name "Constant30" + SID "3474" + Position [375, 2425, 405, 2455] + Value "2" + } + Block { + BlockType Constant + Name "Constant31" + SID "3475" + Position [345, 2495, 375, 2525] + } + Block { + BlockType Constant + Name "Constant32" + SID "3476" + Position [375, 2680, 405, 2710] + Value "2" + } + Block { + BlockType Constant + Name "Constant33" + SID "3477" + Position [345, 2750, 375, 2780] + } + Block { + BlockType Constant + Name "Constant34" + SID "3478" + Position [375, 2945, 405, 2975] + Value "2" + } + Block { + BlockType Constant + Name "Constant35" + SID "3479" + Position [345, 3015, 375, 3045] + } + Block { + BlockType Constant + Name "Constant36" + SID "3480" + Position [375, 3220, 405, 3250] + Value "2" + } + Block { + BlockType Constant + Name "Constant37" + SID "3481" + Position [345, 3290, 375, 3320] + } + Block { + BlockType Constant + Name "Constant38" + SID "3482" + Position [375, 3500, 405, 3530] + Value "2" + } + Block { + BlockType Constant + Name "Constant39" + SID "3483" + Position [345, 3570, 375, 3600] + } + Block { + BlockType Constant + Name "Constant40" + SID "3484" + Position [375, 3790, 405, 3820] + Value "2" + } + Block { + BlockType Constant + Name "Constant41" + SID "3485" + Position [345, 3860, 375, 3890] + } + Block { + BlockType Constant + Name "Constant42" + SID "3486" + Position [375, 4085, 405, 4115] + Value "2" + } + Block { + BlockType Constant + Name "Constant43" + SID "3487" + Position [345, 4155, 375, 4185] + } + Block { + BlockType Constant + Name "Constant44" + SID "3488" + Position [375, 4390, 405, 4420] + Value "2" + } + Block { + BlockType Constant + Name "Constant45" + SID "3489" + Position [345, 4460, 375, 4490] + } + Block { + BlockType Constant + Name "Constant46" + SID "3490" + Position [375, 4700, 405, 4730] + Value "2" + } + Block { + BlockType Constant + Name "Constant47" + SID "3491" + Position [345, 4770, 375, 4800] + } + Block { + BlockType Constant + Name "Constant48" + SID "3492" + Position [380, 5015, 410, 5045] + Value "2" + } + Block { + BlockType Constant + Name "Constant49" + SID "3493" + Position [350, 5085, 380, 5115] + } + Block { + BlockType Constant + Name "Constant50" + SID "3494" + Position [380, 5335, 410, 5365] + Value "2" + } + Block { + BlockType Constant + Name "Constant51" + SID "3495" + Position [350, 5405, 380, 5435] + } + Block { + BlockType Constant + Name "Constant52" + SID "3496" + Position [380, 5660, 410, 5690] + Value "2" + } + Block { + BlockType Constant + Name "Constant53" + SID "3497" + Position [350, 5730, 380, 5760] + } + Block { + BlockType Constant + Name "Constant8" + SID "3498" + Position [365, 330, 395, 360] + Value "2" + } + Block { + BlockType Display + Name "Display1" + SID "3499" + Ports [1] + Position [730, 507, 820, 533] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display2" + SID "3500" + Ports [1] + Position [775, 657, 865, 683] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display3" + SID "3501" + Ports [1] + Position [740, 857, 830, 883] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "3502" + Ports [1] + Position [770, 1057, 860, 1083] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display5" + SID "3503" + Ports [1] + Position [735, 332, 825, 358] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display6" + SID "3504" + Ports [1] + Position [770, 1187, 860, 1213] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display7" + SID "3505" + Ports [1] + Position [640, 197, 730, 223] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display8" + SID "3506" + Ports [1] + Position [490, 317, 580, 343] + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction1" + SID "3507" + Ports [2, 1] + Position [420, 177, 450, 208] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction10" + SID "3508" + Ports [2, 1] + Position [435, 1772, 465, 1803] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction11" + SID "3509" + Ports [2, 1] + Position [435, 1982, 465, 2013] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction12" + SID "3510" + Ports [2, 1] + Position [435, 2212, 465, 2243] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction13" + SID "3511" + Ports [2, 1] + Position [435, 2457, 465, 2488] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction14" + SID "3512" + Ports [2, 1] + Position [435, 2712, 465, 2743] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction15" + SID "3513" + Ports [2, 1] + Position [435, 2977, 465, 3008] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction16" + SID "3514" + Ports [2, 1] + Position [435, 3252, 465, 3283] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction17" + SID "3515" + Ports [2, 1] + Position [435, 3532, 465, 3563] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction18" + SID "3516" + Ports [2, 1] + Position [435, 3822, 465, 3853] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction19" + SID "3517" + Ports [2, 1] + Position [435, 4117, 465, 4148] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction2" + SID "3518" + Ports [2, 1] + Position [425, 362, 455, 393] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction20" + SID "3519" + Ports [2, 1] + Position [435, 4422, 465, 4453] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction21" + SID "3520" + Ports [2, 1] + Position [435, 4732, 465, 4763] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction22" + SID "3521" + Ports [2, 1] + Position [440, 5047, 470, 5078] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction23" + SID "3522" + Ports [2, 1] + Position [440, 5367, 470, 5398] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction24" + SID "3523" + Ports [2, 1] + Position [440, 5692, 470, 5723] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction3" + SID "3524" + Ports [2, 1] + Position [425, 512, 455, 543] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction4" + SID "3525" + Ports [2, 1] + Position [430, 672, 460, 703] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction5" + SID "3526" + Ports [2, 1] + Position [435, 842, 465, 873] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction6" + SID "3527" + Ports [2, 1] + Position [435, 1022, 465, 1053] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction7" + SID "3528" + Ports [2, 1] + Position [435, 1202, 465, 1233] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction8" + SID "3529" + Ports [2, 1] + Position [435, 1382, 465, 1413] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction9" + SID "3530" + Ports [2, 1] + Position [435, 1572, 465, 1603] + Operator "pow" + } + Block { + BlockType Product + Name "Product1" + SID "3531" + Ports [2, 1] + Position [555, 202, 585, 233] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product10" + SID "3532" + Ports [2, 1] + Position [570, 1797, 600, 1828] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product11" + SID "3533" + Ports [2, 1] + Position [570, 2007, 600, 2038] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product12" + SID "3534" + Ports [2, 1] + Position [570, 2237, 600, 2268] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product13" + SID "3535" + Ports [2, 1] + Position [570, 2482, 600, 2513] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product14" + SID "3536" + Ports [2, 1] + Position [570, 2737, 600, 2768] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product15" + SID "3537" + Ports [2, 1] + Position [570, 3002, 600, 3033] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product16" + SID "3538" + Ports [2, 1] + Position [570, 3277, 600, 3308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product17" + SID "3539" + Ports [2, 1] + Position [570, 3557, 600, 3588] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product18" + SID "3540" + Ports [2, 1] + Position [570, 3847, 600, 3878] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product19" + SID "3541" + Ports [2, 1] + Position [570, 4142, 600, 4173] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product2" + SID "3542" + Ports [2, 1] + Position [560, 387, 590, 418] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product20" + SID "3543" + Ports [2, 1] + Position [570, 4447, 600, 4478] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product21" + SID "3544" + Ports [2, 1] + Position [570, 4757, 600, 4788] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product22" + SID "3545" + Ports [2, 1] + Position [575, 5072, 605, 5103] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product23" + SID "3546" + Ports [2, 1] + Position [575, 5392, 605, 5423] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product24" + SID "3547" + Ports [2, 1] + Position [575, 5717, 605, 5748] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product3" + SID "3548" + Ports [2, 1] + Position [560, 537, 590, 568] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product4" + SID "3549" + Ports [2, 1] + Position [565, 697, 595, 728] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product5" + SID "3550" + Ports [2, 1] + Position [570, 867, 600, 898] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product6" + SID "3551" + Ports [2, 1] + Position [570, 1047, 600, 1078] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product7" + SID "3552" + Ports [2, 1] + Position [570, 1227, 600, 1258] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product8" + SID "3553" + Ports [2, 1] + Position [570, 1407, 600, 1438] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product9" + SID "3554" + Ports [2, 1] + Position [570, 1597, 600, 1628] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum1" + SID "3555" + Ports [2, 1] + Position [380, 380, 400, 400] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum10" + SID "3556" + Ports [2, 1] + Position [380, 1400, 400, 1420] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum11" + SID "3557" + Ports [2, 1] + Position [380, 1590, 400, 1610] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum12" + SID "3558" + Ports [2, 1] + Position [380, 1790, 400, 1810] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum13" + SID "3559" + Ports [2, 1] + Position [380, 2000, 400, 2020] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum14" + SID "3560" + Ports [2, 1] + Position [380, 2230, 400, 2250] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum15" + SID "3561" + Ports [2, 1] + Position [380, 2475, 400, 2495] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum16" + SID "3562" + Ports [2, 1] + Position [380, 2730, 400, 2750] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum17" + SID "3563" + Ports [2, 1] + Position [380, 2995, 400, 3015] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum18" + SID "3564" + Ports [2, 1] + Position [380, 3270, 400, 3290] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum19" + SID "3565" + Ports [2, 1] + Position [380, 3550, 400, 3570] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum20" + SID "3566" + Ports [2, 1] + Position [380, 3840, 400, 3860] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum21" + SID "3567" + Ports [2, 1] + Position [380, 4135, 400, 4155] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum22" + SID "3568" + Ports [2, 1] + Position [380, 4440, 400, 4460] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum23" + SID "3569" + Ports [2, 1] + Position [380, 4750, 400, 4770] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum24" + SID "3570" + Ports [2, 1] + Position [385, 5065, 405, 5085] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum25" + SID "3571" + Ports [2, 1] + Position [385, 5385, 405, 5405] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum26" + SID "3572" + Ports [2, 1] + Position [385, 5710, 405, 5730] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum27" + SID "3573" + Ports [24, 1] + Position [760, 3171, 820, 3479] + ShowName off + Inputs "|++++++++++++++++++++++++" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum5" + SID "3574" + Ports [2, 1] + Position [370, 530, 390, 550] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum6" + SID "3575" + Ports [2, 1] + Position [375, 690, 395, 710] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum7" + SID "3576" + Ports [2, 1] + Position [380, 860, 400, 880] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum8" + SID "3577" + Ports [2, 1] + Position [380, 1040, 400, 1060] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum9" + SID "3578" + Ports [2, 1] + Position [380, 1220, 400, 1240] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "Out1" + SID "3579" + Position [845, 3318, 875, 3332] + IconDisplay "Port number" + } + Line { + SrcBlock "Product1" + SrcPort 1 + Points [15, 0] + Branch { + Points [110, 0; 0, 3225] + DstBlock "Sum27" + DstPort 24 + } + Branch { + Points [0, -10] + DstBlock "Display7" + DstPort 1 + } + } + Line { + SrcBlock "Sum1" + SrcPort 1 + Points [0, -5] + Branch { + Points [-50, 0] + DstBlock "Sum5" + DstPort 1 + } + Branch { + Points [5, 0] + Branch { + Points [0, -55] + DstBlock "Display8" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction2" + DstPort 2 + } + } + } + Line { + SrcBlock "Constant2" + SrcPort 1 + DstBlock "Sum1" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction1" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product1" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero1" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product1" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator1" + SrcPort 1 + DstBlock "Compare\nTo Zero1" + DstPort 1 + } + Line { + SrcBlock "Constant1" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction1" + DstPort 1 + } + Line { + SrcBlock "Sum27" + SrcPort 1 + DstBlock "Out1" + DstPort 1 + } + Line { + SrcBlock "In2" + SrcPort 1 + Points [15, 0] + Branch { + Points [0, -105] + DstBlock "Bitwise\nOperator1" + DstPort 1 + } + Branch { + Points [0, 80] + Branch { + Points [0, 150] + Branch { + Points [0, 155] + Branch { + Points [0, 175] + Branch { + Points [0, 180; 5, 0] + Branch { + Points [-5, 0; 0, 175] + Branch { + Points [0, 185] + Branch { + Points [0, 190] + Branch { + Points [0, 195] + Branch { + Points [0, 215] + Branch { + Points [0, 230] + Branch { + Points [0, 240] + Branch { + Points [0, 260] + Branch { + Points [0, 265] + Branch { + Points [0, 275] + Branch { + Points [0, 280] + Branch { + Points [0, 285] + Branch { + Points [0, 300] + Branch { + Points [0, 305] + Branch { + Points [0, 310] + Branch { + Points [0, 315] + Branch { + Points [0, 320] + Branch { + Points [0, 325] + DstBlock "Bitwise\nOperator28" + DstPort 1 + } + Branch { + DstBlock "Bitwise\nOperator27" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator26" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator25" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator24" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator23" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator22" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator21" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator20" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator19" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator18" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator17" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator16" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator15" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator14" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator13" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator12" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator11" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator10" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator9" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator8" + DstPort 1 + } + } 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[140, 0] + DstBlock "Sum27" + DstPort 19 + } + Line { + SrcBlock "Product17" + SrcPort 1 + Points [40, 0; 0, -190] + DstBlock "Sum27" + DstPort 18 + } + Line { + SrcBlock "Product16" + SrcPort 1 + Points [40, 0; 0, 80] + DstBlock "Sum27" + DstPort 17 + } + Line { + SrcBlock "Product15" + SrcPort 1 + Points [40, 0; 0, 345] + DstBlock "Sum27" + DstPort 16 + } + Line { + SrcBlock "Product14" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 15 + } + Line { + SrcBlock "Product13" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 14 + } + Line { + SrcBlock "Product12" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 13 + } + Line { + SrcBlock "Product11" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 12 + } + Line { + SrcBlock "Product10" + SrcPort 1 + Points [40, 0; 0, 1500] + DstBlock "Sum27" + DstPort 11 + } + Line { + SrcBlock "Product9" + SrcPort 1 + Points [40, 0; 0, 1690] + DstBlock "Sum27" + DstPort 10 + } + Line { + SrcBlock "Product8" + SrcPort 1 + Points [40, 0; 0, 1870] + DstBlock "Sum27" + DstPort 9 + } + Line { + SrcBlock "Product7" + SrcPort 1 + Points [95, 0] + Branch { + Points [0, -45] + DstBlock "Display6" + DstPort 1 + } + Branch { + Points [45, 0] + DstBlock "Sum27" + DstPort 8 + } + } + Line { + SrcBlock "Product6" + SrcPort 1 + Points [40, 0; 0, 5] + Branch { + DstBlock "Display4" + DstPort 1 + } + Branch { + Points [0, 2205] + DstBlock "Sum27" + DstPort 7 + } + } + Line { + SrcBlock "Product5" + SrcPort 1 + Points [15, 0] + Branch { + Points [0, -15] + DstBlock "Display3" + DstPort 1 + } + Branch { + Points [0, 2380] + DstBlock "Sum27" + DstPort 6 + } + } + Line { + SrcBlock "Product4" + SrcPort 1 + Points [105, 0] + Branch { + Points [0, -45] + DstBlock "Display2" + DstPort 1 + } + Branch { + Points [40, 0] + DstBlock "Sum27" + DstPort 5 + } + } + Line { + SrcBlock "Product3" + SrcPort 1 + Points [105, 0] + Branch { + Points [0, -35] + DstBlock "Display1" + DstPort 1 + } + Branch { + Points [45, 0] + DstBlock "Sum27" + DstPort 4 + } + } + Line { + SrcBlock "Product2" + SrcPort 1 + Points [40, 0] + Branch { + Points [0, -60] + DstBlock "Display5" + DstPort 1 + } + Branch { + Points [0, 2830] + DstBlock "Sum27" + DstPort 3 + } + } + Line { + SrcBlock "Sum26" + SrcPort 1 + Points [5, 0; 0, -5] + DstBlock "Math\nFunction24" + DstPort 2 + } + Line { + SrcBlock "Constant53" + SrcPort 1 + DstBlock "Sum26" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction24" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product24" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero24" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product24" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator28" + SrcPort 1 + DstBlock "Compare\nTo Zero24" + DstPort 1 + } + Line { + SrcBlock "Constant52" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction24" + DstPort 1 + } + Line { + SrcBlock "Sum25" + SrcPort 1 + Points [5, 0; 0, -5; 5, 0] + Branch { + Points [-50, 0] + DstBlock "Sum26" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction23" + DstPort 2 + } + } + Line { + SrcBlock "Constant51" + SrcPort 1 + DstBlock "Sum25" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction23" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product23" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero23" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product23" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator27" + SrcPort 1 + DstBlock "Compare\nTo Zero23" + DstPort 1 + } + Line { + SrcBlock "Constant50" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction23" + DstPort 1 + } + Line { + SrcBlock "Sum24" + SrcPort 1 + Points [5, 0; 0, -5; 5, 0] + Branch { + Points [-50, 0] + DstBlock "Sum25" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction22" + DstPort 2 + } + } + Line { + SrcBlock "Constant49" + SrcPort 1 + DstBlock "Sum24" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction22" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product22" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero22" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product22" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator26" + SrcPort 1 + DstBlock "Compare\nTo Zero22" + DstPort 1 + } + Line { + SrcBlock "Constant48" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction22" + DstPort 1 + } + Line { + SrcBlock "Sum23" + SrcPort 1 + Points [5, 0; 0, -5] + Branch { + Points [-40, 0] + DstBlock "Sum24" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction21" + DstPort 2 + } + } + Line { + SrcBlock "Constant47" + SrcPort 1 + DstBlock "Sum23" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction21" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product21" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero21" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product21" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator25" + SrcPort 1 + DstBlock "Compare\nTo Zero21" + DstPort 1 + } + Line { + SrcBlock "Constant46" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction21" + DstPort 1 + } + Line { + SrcBlock "Sum22" + SrcPort 1 + Points [5, 0; 0, -5] + Branch { + Points [-45, 0] + DstBlock "Sum23" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction20" + DstPort 2 + } + } + Line { + SrcBlock "Constant45" + SrcPort 1 + DstBlock "Sum22" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction20" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product20" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero20" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product20" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator24" + SrcPort 1 + DstBlock "Compare\nTo Zero20" + DstPort 1 + } + Line { + SrcBlock "Constant44" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction20" + DstPort 1 + } + Line { + SrcBlock "Sum21" + SrcPort 1 + Points [5, 0; 0, -5] + Branch { + Points [-45, 0] + DstBlock "Sum22" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction19" + DstPort 2 + } + } + Line { + SrcBlock "Constant43" + SrcPort 1 + DstBlock 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ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "3597" + Position [50, 48, 80, 62] + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "3598" + Position [25, 248, 55, 262] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In3" + SID "3599" + Position [50, 433, 80, 447] + Port "3" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In4" + SID "3600" + Position [50, 528, 80, 542] + Port "4" + IconDisplay "Port number" + } + Block { + BlockType Reference + Name "Bitwise\nOperator" + SID "3601" + Ports [1, 1] + Position [375, 161, 415, 199] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('01111111')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator1" + SID "3602" + Ports [1, 1] + Position [255, 251, 295, 289] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('10000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator2" + SID "3603" + Ports [1, 1] + Position [285, 26, 325, 64] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('10000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator3" + SID "3604" + Ports [1, 1] + Position [255, 336, 295, 374] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('01111111')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Constant + Name "Constant4" + SID "3605" + Position [855, 280, 885, 310] + Value "127" + } + Block { + BlockType Constant + Name "Constant5" + SID "3606" + Position [650, 655, 740, 685] + Value "8388608" + } + Block { + BlockType Constant + Name "Constant7" + SID "3607" + Position [740, 45, 770, 75] + Value "-1" + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion" + SID "3608" + Position [105, 38, 180, 72] + OutDataTypeStr "uint8" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion1" + SID "3609" + Position [105, 238, 180, 272] + OutDataTypeStr "uint8" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion2" + SID "3610" + Position [110, 333, 185, 367] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion3" + SID "3611" + Position [105, 423, 180, 457] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion4" + SID "3612" + Position [105, 518, 180, 552] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion5" + SID "3613" + Position [800, 653, 875, 687] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion7" + SID "3614" + Position [670, 118, 745, 152] + OutDataTypeStr "double" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Display + Name "Display3" + SID "3615" + Ports [1] + Position [460, 162, 550, 188] + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "3616" + Ports [1] + Position [670, 217, 760, 243] + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Exponent" + SID "3617" + Ports [1] + Position [715, 282, 805, 308] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Mantissa" + SID "3618" + Ports [1] + Position [1015, 558, 1295, 592] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction" + SID "3619" + Ports [2, 1] + Position [825, 102, 855, 133] + Operator "pow" + } + Block { + BlockType Product + Name "Product" + SID "3620" + Ports [2, 1] + Position [1225, 277, 1255, 308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Reference + Name "Shift\nArithmetic" + SID "3621" + Ports [1, 1] + Position [565, 215, 645, 255] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-1" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic1" + SID "3622" + Ports [1, 1] + Position [335, 255, 415, 295] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "7" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic2" + SID "3623" + Ports [1, 1] + Position [360, 25, 440, 65] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "7" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic3" + SID "3624" + Ports [1, 1] + Position [370, 335, 450, 375] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-16" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic4" + SID "3625" + Ports [1, 1] + Position [375, 420, 455, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-8" + nBinPtShiftRight "0" + } + Block { + BlockType Display + Name "Sign" + SID "3626" + Ports [1] + Position [480, 32, 570, 58] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType SubSystem + Name "Subsystem" + SID "3627" + Ports [2, 1] + Position [1125, 350, 1165, 410] + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "Subsystem" + Location [2, 82, 1653, 1004] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "3628" + Position [25, 235, 55, 250] + BlockRotation 270 + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "3629" + Position [220, 358, 250, 372] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Reference + Name "Bitwise\nOperator1" + SID "3630" + Ports [1, 1] + Position [410, 241, 450, 279] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0100000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator10" + SID "3631" + Ports [1, 1] + Position [425, 1086, 465, 1124] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000001000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator11" + SID "3632" + Ports [1, 1] + Position [425, 1266, 465, 1304] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000100000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator12" + SID "3633" + Ports [1, 1] + Position [425, 1446, 465, 1484] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000010000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator13" + SID "3634" + Ports [1, 1] + Position [425, 1636, 465, 1674] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000001000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator14" + SID "3635" + Ports [1, 1] + Position [425, 1836, 465, 1874] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000100000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator15" + SID "3636" + Ports [1, 1] + Position [425, 2046, 465, 2084] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000010000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator16" + SID "3637" + Ports [1, 1] + Position [425, 2276, 465, 2314] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000001000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator17" + SID "3638" + Ports [1, 1] + Position [425, 2521, 465, 2559] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000100000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator18" + SID "3639" + Ports [1, 1] + Position [425, 2776, 465, 2814] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000010000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator19" + SID "3640" + Ports [1, 1] + Position [425, 3041, 465, 3079] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000001000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator20" + SID "3641" + Ports [1, 1] + Position [425, 3316, 465, 3354] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000100000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator21" + SID "3642" + Ports [1, 1] + Position [425, 3596, 465, 3634] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000010000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator22" + SID "3643" + Ports [1, 1] + Position [425, 3886, 465, 3924] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000001000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator23" + SID "3644" + Ports [1, 1] + Position [425, 4181, 465, 4219] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000100000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator24" + SID "3645" + Ports [1, 1] + Position [425, 4486, 465, 4524] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000010000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator25" + SID "3646" + Ports [1, 1] + Position [425, 4796, 465, 4834] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000001000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator26" + SID "3647" + Ports [1, 1] + Position [430, 5111, 470, 5149] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000100')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator27" + SID "3648" + Ports [1, 1] + Position [430, 5431, 470, 5469] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000010')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator28" + SID "3649" + Ports [1, 1] + Position [430, 5756, 470, 5794] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000001')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator6" + SID "3650" + Ports [1, 1] + Position [415, 426, 455, 464] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0010000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator7" + SID "3651" + Ports [1, 1] + Position [415, 576, 455, 614] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0001000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator8" + SID "3652" + Ports [1, 1] + Position [420, 736, 460, 774] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000100000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator9" + SID "3653" + Ports [1, 1] + Position [425, 906, 465, 944] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000010000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Compare\nTo Zero1" + SID "3654" + Ports [1, 1] + Position [480, 245, 510, 275] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero10" + SID "3655" + Ports [1, 1] + Position [495, 1840, 525, 1870] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero11" + SID "3656" + Ports [1, 1] + Position [495, 2050, 525, 2080] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero12" + SID "3657" + Ports [1, 1] + Position [495, 2280, 525, 2310] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero13" + SID "3658" + Ports [1, 1] + Position [495, 2525, 525, 2555] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero14" + SID "3659" + Ports [1, 1] + Position [495, 2780, 525, 2810] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero15" + SID "3660" + Ports [1, 1] + Position [495, 3045, 525, 3075] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero16" + SID "3661" + Ports [1, 1] + Position [495, 3320, 525, 3350] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero17" + SID "3662" + Ports [1, 1] + Position [495, 3600, 525, 3630] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero18" + SID "3663" + Ports [1, 1] + Position [495, 3890, 525, 3920] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero19" + SID "3664" + Ports [1, 1] + Position [495, 4185, 525, 4215] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero2" + SID "3665" + Ports [1, 1] + Position [485, 430, 515, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero20" + SID "3666" + Ports [1, 1] + Position [495, 4490, 525, 4520] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero21" + SID "3667" + Ports [1, 1] + Position [495, 4800, 525, 4830] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero22" + SID "3668" + Ports [1, 1] + Position [500, 5115, 530, 5145] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero23" + SID "3669" + Ports [1, 1] + Position [500, 5435, 530, 5465] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero24" + SID "3670" + Ports [1, 1] + Position [500, 5760, 530, 5790] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero3" + SID "3671" + Ports [1, 1] + Position [485, 580, 515, 610] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero4" + SID "3672" + Ports [1, 1] + Position [490, 740, 520, 770] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero5" + SID "3673" + Ports [1, 1] + Position [495, 910, 525, 940] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero6" + SID "3674" + Ports [1, 1] + Position [495, 1090, 525, 1120] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero7" + SID "3675" + Ports [1, 1] + Position [495, 1270, 525, 1300] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero8" + SID "3676" + Ports [1, 1] + Position [495, 1450, 525, 1480] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero9" + SID "3677" + Ports [1, 1] + Position [495, 1640, 525, 1670] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Constant + Name "Constant1" + SID "3678" + Position [360, 145, 390, 175] + Value "2" + } + Block { + BlockType Constant + Name "Constant10" + SID "3679" + Position [365, 480, 395, 510] + Value "2" + } + Block { + BlockType Constant + Name "Constant11" + SID "3680" + Position [335, 550, 365, 580] + } + Block { + BlockType Constant + Name "Constant12" + SID "3681" + Position [370, 640, 400, 670] + Value "2" + } + Block { + BlockType Constant + Name "Constant13" + SID "3682" + Position [340, 710, 370, 740] + } + Block { + BlockType Constant + Name "Constant14" + SID "3683" + Position [375, 810, 405, 840] + Value "2" + } + Block { + BlockType Constant + Name "Constant15" + SID "3684" + Position [345, 880, 375, 910] + } + Block { + BlockType Constant + Name "Constant16" + SID "3685" + Position [375, 990, 405, 1020] + Value "2" + } + Block { + BlockType Constant + Name "Constant17" + SID "3686" + Position [345, 1060, 375, 1090] + } + Block { + BlockType Constant + Name "Constant18" + SID "3687" + Position [375, 1170, 405, 1200] + Value "2" + } + Block { + BlockType Constant + Name "Constant19" + SID "3688" + Position [345, 1240, 375, 1270] + } + Block { + BlockType Constant + Name "Constant2" + SID "3689" + Position [345, 400, 375, 430] + } + Block { + BlockType Constant + Name "Constant20" + SID "3690" + Position [375, 1350, 405, 1380] + Value "2" + } + Block { + BlockType Constant + Name "Constant21" + SID "3691" + Position [345, 1420, 375, 1450] + } + Block { + BlockType Constant + Name "Constant22" + SID "3692" + Position [375, 1540, 405, 1570] + Value "2" + } + Block { + BlockType Constant + Name "Constant23" + SID "3693" + Position [345, 1610, 375, 1640] + } + Block { + BlockType Constant + Name "Constant24" + SID "3694" + Position [375, 1740, 405, 1770] + Value "2" + } + Block { + BlockType Constant + Name "Constant25" + SID "3695" + Position [345, 1810, 375, 1840] + } + Block { + BlockType Constant + Name "Constant26" + SID "3696" + Position [375, 1950, 405, 1980] + Value "2" + } + Block { + BlockType Constant + Name "Constant27" + SID "3697" + Position [345, 2020, 375, 2050] + } + Block { + BlockType Constant + Name "Constant28" + SID "3698" + Position [375, 2180, 405, 2210] + Value "2" + } + Block { + BlockType Constant + Name "Constant29" + SID "3699" + Position [345, 2250, 375, 2280] + } + Block { + BlockType Constant + Name "Constant30" + SID "3700" + Position [375, 2425, 405, 2455] + Value "2" + } + Block { + BlockType Constant + Name "Constant31" + SID "3701" + Position [345, 2495, 375, 2525] + } + Block { + BlockType Constant + Name "Constant32" + SID "3702" + Position [375, 2680, 405, 2710] + Value "2" + } + Block { + BlockType Constant + Name "Constant33" + SID "3703" + Position [345, 2750, 375, 2780] + } + Block { + BlockType Constant + Name "Constant34" + SID "3704" + Position [375, 2945, 405, 2975] + Value "2" + } + Block { + BlockType Constant + Name "Constant35" + SID "3705" + Position [345, 3015, 375, 3045] + } + Block { + BlockType Constant + Name "Constant36" + SID "3706" + Position [375, 3220, 405, 3250] + Value "2" + } + Block { + BlockType Constant + Name "Constant37" + SID "3707" + Position [345, 3290, 375, 3320] + } + Block { + BlockType Constant + Name "Constant38" + SID "3708" + Position [375, 3500, 405, 3530] + Value "2" + } + Block { + BlockType Constant + Name "Constant39" + SID "3709" + Position [345, 3570, 375, 3600] + } + Block { + BlockType Constant + Name "Constant40" + SID "3710" + Position [375, 3790, 405, 3820] + Value "2" + } + Block { + BlockType Constant + Name "Constant41" + SID "3711" + Position [345, 3860, 375, 3890] + } + Block { + BlockType Constant + Name "Constant42" + SID "3712" + Position [375, 4085, 405, 4115] + Value "2" + } + Block { + BlockType Constant + Name "Constant43" + SID "3713" + Position [345, 4155, 375, 4185] + } + Block { + BlockType Constant + Name "Constant44" + SID "3714" + Position [375, 4390, 405, 4420] + Value "2" + } + Block { + BlockType Constant + Name "Constant45" + SID "3715" + Position [345, 4460, 375, 4490] + } + Block { + BlockType Constant + Name "Constant46" + SID "3716" + Position [375, 4700, 405, 4730] + Value "2" + } + Block { + BlockType Constant + Name "Constant47" + SID "3717" + Position [345, 4770, 375, 4800] + } + Block { + BlockType Constant + Name "Constant48" + SID "3718" + Position [380, 5015, 410, 5045] + Value "2" + } + Block { + BlockType Constant + Name "Constant49" + SID "3719" + Position [350, 5085, 380, 5115] + } + Block { + BlockType Constant + Name "Constant50" + SID "3720" + Position [380, 5335, 410, 5365] + Value "2" + } + Block { + BlockType Constant + Name "Constant51" + SID "3721" + Position [350, 5405, 380, 5435] + } + Block { + BlockType Constant + Name "Constant52" + SID "3722" + Position [380, 5660, 410, 5690] + Value "2" + } + Block { + BlockType Constant + Name "Constant53" + SID "3723" + Position [350, 5730, 380, 5760] + } + Block { + BlockType Constant + Name "Constant8" + SID "3724" + Position [365, 330, 395, 360] + Value "2" + } + Block { + BlockType Display + Name "Display1" + SID "3725" + Ports [1] + Position [730, 507, 820, 533] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display2" + SID "3726" + Ports [1] + Position [775, 657, 865, 683] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display3" + SID "3727" + Ports [1] + Position [740, 857, 830, 883] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "3728" + Ports [1] + Position [770, 1057, 860, 1083] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display5" + SID "3729" + Ports [1] + Position [735, 332, 825, 358] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display6" + SID "3730" + Ports [1] + Position [770, 1187, 860, 1213] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display7" + SID "3731" + Ports [1] + Position [640, 197, 730, 223] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display8" + SID "3732" + Ports [1] + Position [490, 317, 580, 343] + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction1" + SID "3733" + Ports [2, 1] + Position [420, 177, 450, 208] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction10" + SID "3734" + Ports [2, 1] + Position [435, 1772, 465, 1803] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction11" + SID "3735" + Ports [2, 1] + Position [435, 1982, 465, 2013] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction12" + SID "3736" + Ports [2, 1] + Position [435, 2212, 465, 2243] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction13" + SID "3737" + Ports [2, 1] + Position [435, 2457, 465, 2488] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction14" + SID "3738" + Ports [2, 1] + Position [435, 2712, 465, 2743] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction15" + SID "3739" + Ports [2, 1] + Position [435, 2977, 465, 3008] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction16" + SID "3740" + Ports [2, 1] + Position [435, 3252, 465, 3283] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction17" + SID "3741" + Ports [2, 1] + Position [435, 3532, 465, 3563] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction18" + SID "3742" + Ports [2, 1] + Position [435, 3822, 465, 3853] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction19" + SID "3743" + Ports [2, 1] + Position [435, 4117, 465, 4148] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction2" + SID "3744" + Ports [2, 1] + Position [425, 362, 455, 393] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction20" + SID "3745" + Ports [2, 1] + Position [435, 4422, 465, 4453] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction21" + SID "3746" + Ports [2, 1] + Position [435, 4732, 465, 4763] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction22" + SID "3747" + Ports [2, 1] + Position [440, 5047, 470, 5078] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction23" + SID "3748" + Ports [2, 1] + Position [440, 5367, 470, 5398] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction24" + SID "3749" + Ports [2, 1] + Position [440, 5692, 470, 5723] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction3" + SID "3750" + Ports [2, 1] + Position [425, 512, 455, 543] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction4" + SID "3751" + Ports [2, 1] + Position [430, 672, 460, 703] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction5" + SID "3752" + Ports [2, 1] + Position [435, 842, 465, 873] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction6" + SID "3753" + Ports [2, 1] + Position [435, 1022, 465, 1053] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction7" + SID "3754" + Ports [2, 1] + Position [435, 1202, 465, 1233] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction8" + SID "3755" + Ports [2, 1] + Position [435, 1382, 465, 1413] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction9" + SID "3756" + Ports [2, 1] + Position [435, 1572, 465, 1603] + Operator "pow" + } + Block { + BlockType Product + Name "Product1" + SID "3757" + Ports [2, 1] + Position [555, 202, 585, 233] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product10" + SID "3758" + Ports [2, 1] + Position [570, 1797, 600, 1828] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product11" + SID "3759" + Ports [2, 1] + Position [570, 2007, 600, 2038] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product12" + SID "3760" + Ports [2, 1] + Position [570, 2237, 600, 2268] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product13" + SID "3761" + Ports [2, 1] + Position [570, 2482, 600, 2513] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product14" + SID "3762" + Ports [2, 1] + Position [570, 2737, 600, 2768] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product15" + SID "3763" + Ports [2, 1] + Position [570, 3002, 600, 3033] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product16" + SID "3764" + Ports [2, 1] + Position [570, 3277, 600, 3308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product17" + SID "3765" + Ports [2, 1] + Position [570, 3557, 600, 3588] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product18" + SID "3766" + Ports [2, 1] + Position [570, 3847, 600, 3878] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product19" + SID "3767" + Ports [2, 1] + Position [570, 4142, 600, 4173] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product2" + SID "3768" + Ports [2, 1] + Position [560, 387, 590, 418] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product20" + SID "3769" + Ports [2, 1] + Position [570, 4447, 600, 4478] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product21" + SID "3770" + Ports [2, 1] + Position [570, 4757, 600, 4788] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product22" + SID "3771" + Ports [2, 1] + Position [575, 5072, 605, 5103] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product23" + SID "3772" + Ports [2, 1] + Position [575, 5392, 605, 5423] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product24" + SID "3773" + Ports [2, 1] + Position [575, 5717, 605, 5748] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product3" + SID "3774" + Ports [2, 1] + Position [560, 537, 590, 568] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product4" + SID "3775" + Ports [2, 1] + Position [565, 697, 595, 728] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product5" + SID "3776" + Ports [2, 1] + Position [570, 867, 600, 898] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product6" + SID "3777" + Ports [2, 1] + Position [570, 1047, 600, 1078] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product7" + SID "3778" + Ports [2, 1] + Position [570, 1227, 600, 1258] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product8" + SID "3779" + Ports [2, 1] + Position [570, 1407, 600, 1438] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product9" + SID "3780" + Ports [2, 1] + Position [570, 1597, 600, 1628] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum1" + SID "3781" + Ports [2, 1] + Position [380, 380, 400, 400] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum10" + SID "3782" + Ports [2, 1] + Position [380, 1400, 400, 1420] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum11" + SID "3783" + Ports [2, 1] + Position [380, 1590, 400, 1610] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum12" + SID "3784" + Ports [2, 1] + Position [380, 1790, 400, 1810] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum13" + SID "3785" + Ports [2, 1] + Position [380, 2000, 400, 2020] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum14" + SID "3786" + Ports [2, 1] + Position [380, 2230, 400, 2250] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum15" + SID "3787" + Ports [2, 1] + Position [380, 2475, 400, 2495] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum16" + SID "3788" + Ports [2, 1] + Position [380, 2730, 400, 2750] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum17" + SID "3789" + Ports [2, 1] + Position [380, 2995, 400, 3015] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum18" + SID "3790" + Ports [2, 1] + Position [380, 3270, 400, 3290] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum19" + SID "3791" + Ports [2, 1] + Position [380, 3550, 400, 3570] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum20" + SID "3792" + Ports [2, 1] + Position [380, 3840, 400, 3860] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum21" + SID "3793" + Ports [2, 1] + Position [380, 4135, 400, 4155] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum22" + SID "3794" + Ports [2, 1] + Position [380, 4440, 400, 4460] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum23" + SID "3795" + Ports [2, 1] + Position [380, 4750, 400, 4770] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum24" + SID "3796" + Ports [2, 1] + Position [385, 5065, 405, 5085] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum25" + SID "3797" + Ports [2, 1] + Position [385, 5385, 405, 5405] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum26" + SID "3798" + Ports [2, 1] + Position [385, 5710, 405, 5730] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum27" + SID "3799" + Ports [24, 1] + Position [760, 3171, 820, 3479] + ShowName off + Inputs "|++++++++++++++++++++++++" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum5" + SID "3800" + Ports [2, 1] + Position [370, 530, 390, 550] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum6" + SID "3801" + Ports [2, 1] + Position [375, 690, 395, 710] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum7" + SID "3802" + Ports [2, 1] + Position [380, 860, 400, 880] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum8" + SID "3803" + Ports [2, 1] + Position [380, 1040, 400, 1060] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum9" + SID "3804" + Ports [2, 1] + Position [380, 1220, 400, 1240] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "Out1" + SID "3805" + Position [845, 3318, 875, 3332] + IconDisplay "Port number" + } + Line { + SrcBlock "Constant8" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction2" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator6" + SrcPort 1 + DstBlock "Compare\nTo Zero2" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero2" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product2" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction2" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product2" + DstPort 1 + } + Line { + SrcBlock "Constant10" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction3" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator7" + SrcPort 1 + DstBlock "Compare\nTo Zero3" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero3" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product3" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction3" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product3" + DstPort 1 + } + Line { + SrcBlock "Constant11" + SrcPort 1 + DstBlock "Sum5" + DstPort 2 + } + Line { + SrcBlock "Sum5" + SrcPort 1 + Points [0, 0; 5, 0] + Branch { + Points [0, 10; -40, 0] + DstBlock "Sum6" + DstPort 1 + } + Branch { + Points [0, -5] + DstBlock "Math\nFunction3" + DstPort 2 + } + } + Line { + SrcBlock "Constant12" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction4" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator8" + SrcPort 1 + DstBlock "Compare\nTo Zero4" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero4" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product4" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction4" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product4" + DstPort 1 + } + Line { + SrcBlock "Constant13" + SrcPort 1 + DstBlock "Sum6" + DstPort 2 + } + Line { + SrcBlock "Sum6" + SrcPort 1 + Points [0, 0; 5, 0] + Branch { + Points [-40, 0] + DstBlock "Sum7" + DstPort 1 + } + Branch { + Points [0, -5] + DstBlock "Math\nFunction4" + DstPort 2 + } + } + Line { + SrcBlock "Constant14" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction5" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator9" + SrcPort 1 + DstBlock "Compare\nTo Zero5" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero5" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product5" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction5" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product5" + DstPort 1 + } + Line { + SrcBlock "Constant15" + SrcPort 1 + DstBlock "Sum7" + DstPort 2 + } + Line { + SrcBlock "Sum7" + SrcPort 1 + Points [0, 0; 5, 0] + Branch { + Points [-45, 0] + DstBlock "Sum8" + DstPort 1 + } + Branch { + Points [0, -5] + DstBlock "Math\nFunction5" + DstPort 2 + } + } + Line { + SrcBlock "Constant16" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction6" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator10" + SrcPort 1 + DstBlock "Compare\nTo Zero6" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero6" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product6" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction6" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product6" + DstPort 1 + } + Line { + SrcBlock "Constant17" + SrcPort 1 + DstBlock "Sum8" + DstPort 2 + } + Line { + SrcBlock "Sum8" + SrcPort 1 + Points [0, 0; 5, 0] + Branch { + Points [-45, 0] + DstBlock "Sum9" + DstPort 1 + } + Branch { + Points [0, -5] + DstBlock "Math\nFunction6" + DstPort 2 + } + } + Line { + SrcBlock "Constant18" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction7" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator11" + SrcPort 1 + DstBlock "Compare\nTo Zero7" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero7" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product7" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction7" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product7" + DstPort 1 + } + Line { + SrcBlock "Constant19" + SrcPort 1 + DstBlock "Sum9" + DstPort 2 + } + Line { + SrcBlock "Sum9" + SrcPort 1 + Points [5, 0; 0, -5; 5, 0] + Branch { + DstBlock "Math\nFunction7" + DstPort 2 + } + Branch { + Points [0, 5; -50, 0] + DstBlock "Sum10" + DstPort 1 + } + } + Line { + SrcBlock "Constant20" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction8" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator12" + SrcPort 1 + DstBlock "Compare\nTo Zero8" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero8" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product8" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction8" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product8" + DstPort 1 + } + Line { + SrcBlock "Constant21" + SrcPort 1 + DstBlock "Sum10" + DstPort 2 + } + Line { + SrcBlock "Sum10" + SrcPort 1 + Points [0, 0; 5, 0] + Branch { + Points [0, -5] + DstBlock "Math\nFunction8" + DstPort 2 + } + Branch { + Points [-45, 0] + DstBlock "Sum11" + DstPort 1 + } + } + Line { + SrcBlock "Constant22" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction9" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator13" + SrcPort 1 + DstBlock "Compare\nTo Zero9" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero9" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product9" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction9" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product9" + DstPort 1 + } + Line { + SrcBlock "Constant23" + SrcPort 1 + DstBlock "Sum11" + DstPort 2 + } + Line { + SrcBlock "Sum11" + SrcPort 1 + Points [0, 0; 5, 0] + Branch { + Points [0, -5] + DstBlock "Math\nFunction9" + DstPort 2 + } + Branch { + Points [-45, 0] + DstBlock "Sum12" + DstPort 1 + } + } + Line { + SrcBlock "Constant24" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction10" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator14" + SrcPort 1 + DstBlock "Compare\nTo Zero10" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero10" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product10" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction10" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product10" + DstPort 1 + } + Line { + SrcBlock "Constant25" + SrcPort 1 + DstBlock "Sum12" + DstPort 2 + } + Line { + SrcBlock "Sum12" + SrcPort 1 + Points [5, 0; 0, -5] + Branch { + DstBlock "Math\nFunction10" + DstPort 2 + } + Branch { + Points [-45, 0] + DstBlock "Sum13" + DstPort 1 + } + } + Line { + SrcBlock "Constant26" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction11" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator15" + SrcPort 1 + DstBlock "Compare\nTo Zero11" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero11" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product11" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction11" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product11" + DstPort 1 + } + Line { + SrcBlock "Constant27" + SrcPort 1 + DstBlock "Sum13" + DstPort 2 + } + Line { + SrcBlock "Sum13" + SrcPort 1 + Points [5, 0; 0, -5] + Branch { + DstBlock "Math\nFunction11" + DstPort 2 + } + Branch { + Points [-45, 0] + DstBlock "Sum14" + DstPort 1 + } + } + Line { + SrcBlock "Constant28" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction12" + DstPort 1 + } + Line { + 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DstBlock "Product13" + DstPort 1 + } + Line { + SrcBlock "Constant31" + SrcPort 1 + DstBlock "Sum15" + DstPort 2 + } + Line { + SrcBlock "Sum15" + SrcPort 1 + Points [5, 0; 0, -5] + Branch { + DstBlock "Math\nFunction13" + DstPort 2 + } + Branch { + Points [-45, 0] + DstBlock "Sum16" + DstPort 1 + } + } + Line { + SrcBlock "Constant32" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction14" + DstPort 1 + } + Line { + SrcBlock "Bitwise\nOperator18" + SrcPort 1 + DstBlock "Compare\nTo Zero14" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero14" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product14" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction14" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product14" + DstPort 1 + } + Line { + SrcBlock "Constant33" + SrcPort 1 + DstBlock "Sum16" + DstPort 2 + } + Line { + SrcBlock "Sum16" + SrcPort 1 + Points [5, 0; 0, -5] + Branch { + DstBlock "Math\nFunction14" + DstPort 2 + } + Branch { + Points [-45, 0] + DstBlock "Sum17" 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SrcPort 1 + Points [135, 0] + DstBlock "Sum27" + DstPort 1 + } + Line { + SrcBlock "In1" + SrcPort 1 + Points [0, -10; 280, 0] + Branch { + Points [0, -20] + DstBlock "Math\nFunction1" + DstPort 2 + } + Branch { + Points [0, 170] + DstBlock "Sum1" + DstPort 1 + } + } + Line { + SrcBlock "In2" + SrcPort 1 + Points [15, 0] + Branch { + Points [0, 80] + Branch { + DstBlock "Bitwise\nOperator6" + DstPort 1 + } + Branch { + Points [0, 150] + Branch { + DstBlock "Bitwise\nOperator7" + DstPort 1 + } + Branch { + Points [0, 155] + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator8" + DstPort 1 + } + Branch { + Points [0, 175] + Branch { + DstBlock "Bitwise\nOperator9" + DstPort 1 + } + Branch { + Points [0, 180; 5, 0] + Branch { + DstBlock "Bitwise\nOperator10" + DstPort 1 + } + Branch { + Points [-5, 0; 0, 175] + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator11" + DstPort 1 + } + Branch { + Points [0, 185] + Branch { + DstBlock "Bitwise\nOperator12" + DstPort 1 + } + Branch { + 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Points [0, 55] + DstBlock "Shift\nArithmetic" + DstPort 1 + } + } + Line { + SrcBlock "Data Type Conversion" + SrcPort 1 + Points [50, 0] + Branch { + Points [0, 125] + DstBlock "Bitwise\nOperator" + DstPort 1 + } + Branch { + Points [0, -10] + DstBlock "Bitwise\nOperator2" + DstPort 1 + } + } + Line { + SrcBlock "In2" + SrcPort 1 + Points [15, 0] + Branch { + Points [0, 95] + DstBlock "Data Type Conversion2" + DstPort 1 + } + Branch { + DstBlock "Data Type Conversion1" + DstPort 1 + } + } + Line { + SrcBlock "Data Type Conversion1" + SrcPort 1 + Points [25, 0; 0, 15] + DstBlock "Bitwise\nOperator1" + DstPort 1 + } + Line { + SrcBlock "Shift\nArithmetic" + SrcPort 1 + Points [0, -5] + Branch { + DstBlock "Display4" + DstPort 1 + } + Branch { + Points [5, 0] + DstBlock "Sum" + DstPort 1 + } + } + Line { + SrcBlock "Bitwise\nOperator1" + SrcPort 1 + Points [10, 0; 0, 5] + DstBlock "Shift\nArithmetic1" + DstPort 1 + } + Line { + SrcBlock "Shift\nArithmetic1" + SrcPort 1 + Points [155, 0; 0, 50] + DstBlock "Sum" + DstPort 2 + } + Line { + SrcBlock "Sum" + SrcPort 1 + Points [0, -5; 5, 0] + Branch { + DstBlock "Exponent" + DstPort 1 + } + Branch { + Points [0, -50] + DstBlock "Sum2" + DstPort 1 + } + } + Line { + SrcBlock "Bitwise\nOperator2" + SrcPort 1 + DstBlock "Shift\nArithmetic2" + DstPort 1 + } + Line { + SrcBlock "Shift\nArithmetic2" + SrcPort 1 + Points [10, 0] + Branch { + DstBlock "Sign" + DstPort 1 + } + Branch { + Points [0, 90] + DstBlock "Data Type Conversion7" + DstPort 1 + } + } + Line { + SrcBlock "Bitwise\nOperator3" + SrcPort 1 + DstBlock "Shift\nArithmetic3" + DstPort 1 + } + Line { + SrcBlock "Data Type Conversion2" + SrcPort 1 + Points [30, 0; 0, 5] + DstBlock "Bitwise\nOperator3" + DstPort 1 + } + Line { + SrcBlock "Shift\nArithmetic3" + SrcPort 1 + Points [5, 0; 0, 10; 379, 0] + DstBlock "Sum1" + DstPort 1 + } + Line { + SrcBlock "Data Type Conversion3" + SrcPort 1 + DstBlock "Shift\nArithmetic4" + DstPort 1 + } + Line { + SrcBlock "Shift\nArithmetic4" + SrcPort 1 + Points [370, 0] + DstBlock "Sum1" + DstPort 2 + } + Line { + SrcBlock "Data Type Conversion4" + SrcPort 1 + Points [320, 0; 0, -64; 334, 0] + DstBlock "Sum1" + DstPort 3 + } + Line { + SrcBlock "Sum1" + SrcPort 1 + Points [30, 0; 0, 155] + Branch { + Points [0, 5] + DstBlock "Mantissa" + DstPort 1 + } + Branch { + Points [0, 65] + DstBlock "Sum3" + DstPort 1 + } + } + Line { + SrcBlock "Constant4" + SrcPort 1 + DstBlock "Sum2" + DstPort 2 + } + Line { + SrcBlock "Sum2" + SrcPort 1 + Points [0, 5; 45, 0; 0, 115] + DstBlock "Subsystem" + DstPort 1 + } + Line { + SrcBlock "Sum3" + SrcPort 1 + Points [5, 0; 0, -240] + DstBlock "Subsystem" + DstPort 2 + } + Line { + SrcBlock "Constant5" + SrcPort 1 + DstBlock "Data Type Conversion5" + DstPort 1 + } + Line { + SrcBlock "Data Type Conversion5" + SrcPort 1 + Points [75, 0] + DstBlock "Sum3" + DstPort 2 + } + Line { + SrcBlock "Subsystem" + SrcPort 1 + Points [25, 0; 0, -30; 5, 0; 0, -50] + DstBlock "Product" + DstPort 2 + } + Line { + SrcBlock "Constant7" + SrcPort 1 + Points [20, 0; 0, 50] + DstBlock "Math\nFunction" + DstPort 1 + } + Line { + SrcBlock "Data Type Conversion7" + SrcPort 1 + Points [60, 0] + DstBlock "Math\nFunction" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction" + SrcPort 1 + Points [175, 0; 0, 165] + DstBlock "Product" + DstPort 1 + } + Line { + SrcBlock "In1" + SrcPort 1 + DstBlock "Data Type Conversion" + DstPort 1 + } + Line { + SrcBlock "Product" + SrcPort 1 + DstBlock "Out1" + DstPort 1 + } + Line { + SrcBlock "In3" + SrcPort 1 + DstBlock "Data Type Conversion3" + DstPort 1 + } + Line { + SrcBlock "In4" + SrcPort 1 + DstBlock "Data Type Conversion4" + DstPort 1 + } + } + } + Block { + BlockType Outport + Name "d_acq_carrier_doppler_Hz" + SID "3811" + Position [440, 113, 470, 127] + IconDisplay "Port number" + OutputWhenDisabled "reset" + InitialOutput "0" + } + Line { + SrcBlock "Data Type \nConversion5" + SrcPort 1 + DstBlock "d_acq_carrier_doppler_Hz" + DstPort 1 + } + Line { + SrcBlock "hex2float" + SrcPort 1 + DstBlock "Data Type \nConversion5" + DstPort 1 + } + Line { + SrcBlock "Data Type \nConversion4" + SrcPort 1 + DstBlock "hex2float" + DstPort 1 + } + Line { + SrcBlock "Data Type \nConversion1" + SrcPort 1 + DstBlock "hex2float" + DstPort 2 + } + Line { + SrcBlock "Data Type \nConversion2" + SrcPort 1 + DstBlock "hex2float" + DstPort 3 + } + Line { + SrcBlock "Data Type \nConversion3" + SrcPort 1 + DstBlock "hex2float" + DstPort 4 + } + Line { + SrcBlock "In4" + SrcPort 1 + DstBlock "Data Type \nConversion4" + DstPort 1 + } + Line { + SrcBlock "In3" + SrcPort 1 + DstBlock "Data Type \nConversion1" + DstPort 1 + } + Line { + SrcBlock "In2" + SrcPort 1 + DstBlock "Data Type \nConversion2" + DstPort 1 + } + Line { + SrcBlock "In1" + SrcPort 1 + DstBlock "Data Type \nConversion3" + DstPort 1 + } + } + } + Block { + BlockType SubSystem + Name "Subsystem7" + SID "3812" + Ports [4, 1] + Position [525, 2000, 630, 2160] + ShowName off + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "Subsystem7" + Location [528, 347, 1038, 603] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "3813" + Position [25, 178, 55, 192] + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "3814" + Position [25, 133, 55, 147] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In3" + SID "3815" + Position [25, 88, 55, 102] + Port "3" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In4" + SID "3816" + Position [25, 43, 55, 57] + Port "4" + IconDisplay "Port number" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion1" + SID "3817" + Position [100, 75, 140, 115] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion2" + SID "3818" + Position [100, 120, 140, 160] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion3" + SID "3819" + Position [100, 165, 140, 205] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion4" + SID "3820" + Position [100, 30, 140, 70] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType DataTypeConversion + Name "Data Type \nConversion5" + SID "3821" + Position [365, 100, 405, 140] + ShowName off + OutDataTypeStr "single" + } + Block { + BlockType SubSystem + Name "hex2float" + SID "3822" + Ports [4, 1] + Position [190, 25, 320, 210] + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "hex2float" + Location [13, 125, 1281, 839] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "3823" + Position [50, 48, 80, 62] + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "3824" + Position [25, 248, 55, 262] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In3" + SID "3825" + Position [50, 433, 80, 447] + Port "3" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In4" + SID "3826" + Position [50, 528, 80, 542] + Port "4" + IconDisplay "Port number" + } + Block { + BlockType Reference + Name "Bitwise\nOperator" + SID "3827" + Ports [1, 1] + Position [375, 161, 415, 199] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('01111111')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator1" + SID "3828" + Ports [1, 1] + Position [255, 251, 295, 289] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('10000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator2" + SID "3829" + Ports [1, 1] + Position [285, 26, 325, 64] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('10000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator3" + SID "3830" + Ports [1, 1] + Position [255, 336, 295, 374] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('01111111')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Constant + Name "Constant4" + SID "3831" + Position [855, 280, 885, 310] + Value "127" + } + Block { + BlockType Constant + Name "Constant5" + SID "3832" + Position [650, 655, 740, 685] + Value "8388608" + } + Block { + BlockType Constant + Name "Constant7" + SID "3833" + Position [740, 45, 770, 75] + Value "-1" + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion" + SID "3834" + Position [105, 38, 180, 72] + OutDataTypeStr "uint8" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion1" + SID "3835" + Position [105, 238, 180, 272] + OutDataTypeStr "uint8" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion2" + SID "3836" + Position [110, 333, 185, 367] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion3" + SID "3837" + Position [105, 423, 180, 457] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion4" + SID "3838" + Position [105, 518, 180, 552] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion5" + SID "3839" + Position [800, 653, 875, 687] + OutDataTypeStr "uint32" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType DataTypeConversion + Name "Data Type Conversion7" + SID "3840" + Position [670, 118, 745, 152] + OutDataTypeStr "double" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Display + Name "Display3" + SID "3841" + Ports [1] + Position [460, 162, 550, 188] + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "3842" + Ports [1] + Position [670, 217, 760, 243] + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Exponent" + SID "3843" + Ports [1] + Position [715, 282, 805, 308] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Mantissa" + SID "3844" + Ports [1] + Position [1015, 558, 1295, 592] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction" + SID "3845" + Ports [2, 1] + Position [825, 102, 855, 133] + Operator "pow" + } + Block { + BlockType Product + Name "Product" + SID "3846" + Ports [2, 1] + Position [1225, 277, 1255, 308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Reference + Name "Shift\nArithmetic" + SID "3847" + Ports [1, 1] + Position [565, 215, 645, 255] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-1" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic1" + SID "3848" + Ports [1, 1] + Position [335, 255, 415, 295] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "7" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic2" + SID "3849" + Ports [1, 1] + Position [360, 25, 440, 65] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "7" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic3" + SID "3850" + Ports [1, 1] + Position [370, 335, 450, 375] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-16" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic4" + SID "3851" + Ports [1, 1] + Position [375, 420, 455, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-8" + nBinPtShiftRight "0" + } + Block { + BlockType Display + Name "Sign" + SID "3852" + Ports [1] + Position [480, 32, 570, 58] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType SubSystem + Name "Subsystem" + SID "3853" + Ports [2, 1] + Position [1125, 350, 1165, 410] + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "Subsystem" + Location [2, 82, 1653, 1004] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "3854" + Position [25, 235, 55, 250] + BlockRotation 270 + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "3855" + Position [220, 358, 250, 372] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Reference + Name "Bitwise\nOperator1" + SID "3856" + Ports [1, 1] + Position [410, 241, 450, 279] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0100000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator10" + SID "3857" + Ports [1, 1] + Position [425, 1086, 465, 1124] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000001000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator11" + SID "3858" + Ports [1, 1] + Position [425, 1266, 465, 1304] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000100000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator12" + SID "3859" + Ports [1, 1] + Position [425, 1446, 465, 1484] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000010000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator13" + SID "3860" + Ports [1, 1] + Position [425, 1636, 465, 1674] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000001000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator14" + SID "3861" + Ports [1, 1] + Position [425, 1836, 465, 1874] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000100000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator15" + SID "3862" + Ports [1, 1] + Position [425, 2046, 465, 2084] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000010000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator16" + SID "3863" + Ports [1, 1] + Position [425, 2276, 465, 2314] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000001000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator17" + SID "3864" + Ports [1, 1] + Position [425, 2521, 465, 2559] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000100000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator18" + SID "3865" + Ports [1, 1] + Position [425, 2776, 465, 2814] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000010000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator19" + SID "3866" + Ports [1, 1] + Position [425, 3041, 465, 3079] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000001000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator20" + SID "3867" + Ports [1, 1] + Position [425, 3316, 465, 3354] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000100000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator21" + SID "3868" + Ports [1, 1] + Position [425, 3596, 465, 3634] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000010000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator22" + SID "3869" + Ports [1, 1] + Position [425, 3886, 465, 3924] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000001000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator23" + SID "3870" + Ports [1, 1] + Position [425, 4181, 465, 4219] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000100000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator24" + SID "3871" + Ports [1, 1] + Position [425, 4486, 465, 4524] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000010000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator25" + SID "3872" + Ports [1, 1] + Position [425, 4796, 465, 4834] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000001000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator26" + SID "3873" + Ports [1, 1] + Position [430, 5111, 470, 5149] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000100')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator27" + SID "3874" + Ports [1, 1] + Position [430, 5431, 470, 5469] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000010')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator28" + SID "3875" + Ports [1, 1] + Position [430, 5756, 470, 5794] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000001')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator6" + SID "3876" + Ports [1, 1] + Position [415, 426, 455, 464] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0010000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator7" + SID "3877" + Ports [1, 1] + Position [415, 576, 455, 614] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0001000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator8" + SID "3878" + Ports [1, 1] + Position [420, 736, 460, 774] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000100000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator9" + SID "3879" + Ports [1, 1] + Position [425, 906, 465, 944] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000010000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Compare\nTo Zero1" + SID "3880" + Ports [1, 1] + Position [480, 245, 510, 275] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero10" + SID "3881" + Ports [1, 1] + Position [495, 1840, 525, 1870] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero11" + SID "3882" + Ports [1, 1] + Position [495, 2050, 525, 2080] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero12" + SID "3883" + Ports [1, 1] + Position [495, 2280, 525, 2310] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero13" + SID "3884" + Ports [1, 1] + Position [495, 2525, 525, 2555] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero14" + SID "3885" + Ports [1, 1] + Position [495, 2780, 525, 2810] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero15" + SID "3886" + Ports [1, 1] + Position [495, 3045, 525, 3075] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero16" + SID "3887" + Ports [1, 1] + Position [495, 3320, 525, 3350] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero17" + SID "3888" + Ports [1, 1] + Position [495, 3600, 525, 3630] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero18" + SID "3889" + Ports [1, 1] + Position [495, 3890, 525, 3920] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero19" + SID "3890" + Ports [1, 1] + Position [495, 4185, 525, 4215] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero2" + SID "3891" + Ports [1, 1] + Position [485, 430, 515, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero20" + SID "3892" + Ports [1, 1] + Position [495, 4490, 525, 4520] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero21" + SID "3893" + Ports [1, 1] + Position [495, 4800, 525, 4830] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero22" + SID "3894" + Ports [1, 1] + Position [500, 5115, 530, 5145] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero23" + SID "3895" + Ports [1, 1] + Position [500, 5435, 530, 5465] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero24" + SID "3896" + Ports [1, 1] + Position [500, 5760, 530, 5790] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero3" + SID "3897" + Ports [1, 1] + Position [485, 580, 515, 610] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero4" + SID "3898" + Ports [1, 1] + Position [490, 740, 520, 770] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero5" + SID "3899" + Ports [1, 1] + Position [495, 910, 525, 940] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero6" + SID "3900" + Ports [1, 1] + Position [495, 1090, 525, 1120] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero7" + SID "3901" + Ports [1, 1] + Position [495, 1270, 525, 1300] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero8" + SID "3902" + Ports [1, 1] + Position [495, 1450, 525, 1480] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero9" + SID "3903" + Ports [1, 1] + Position [495, 1640, 525, 1670] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Constant + Name "Constant1" + SID "3904" + Position [360, 145, 390, 175] + Value "2" + } + Block { + BlockType Constant + Name "Constant10" + SID "3905" + Position [365, 480, 395, 510] + Value "2" + } + Block { + BlockType Constant + Name "Constant11" + SID "3906" + Position [335, 550, 365, 580] + } + Block { + BlockType Constant + Name "Constant12" + SID "3907" + Position [370, 640, 400, 670] + Value "2" + } + Block { + BlockType Constant + Name "Constant13" + SID "3908" + Position [340, 710, 370, 740] + } + Block { + BlockType Constant + Name "Constant14" + SID "3909" + Position [375, 810, 405, 840] + Value "2" + } + Block { + BlockType Constant + Name "Constant15" + SID "3910" + Position [345, 880, 375, 910] + } + Block { + BlockType Constant + Name "Constant16" + SID "3911" + Position [375, 990, 405, 1020] + Value "2" + } + Block { + BlockType Constant + Name "Constant17" + SID "3912" + Position [345, 1060, 375, 1090] + } + Block { + BlockType Constant + Name "Constant18" + SID "3913" + Position [375, 1170, 405, 1200] + Value "2" + } + Block { + BlockType Constant + Name "Constant19" + SID "3914" + Position [345, 1240, 375, 1270] + } + Block { + BlockType Constant + Name "Constant2" + SID "3915" + Position [345, 400, 375, 430] + } + Block { + BlockType Constant + Name "Constant20" + SID "3916" + Position [375, 1350, 405, 1380] + Value "2" + } + Block { + BlockType Constant + Name "Constant21" + SID "3917" + Position [345, 1420, 375, 1450] + } + Block { + BlockType Constant + Name "Constant22" + SID "3918" + Position [375, 1540, 405, 1570] + Value "2" + } + Block { + BlockType Constant + Name "Constant23" + SID "3919" + Position [345, 1610, 375, 1640] + } + Block { + BlockType Constant + Name "Constant24" + SID "3920" + Position [375, 1740, 405, 1770] + Value "2" + } + Block { + BlockType Constant + Name "Constant25" + SID "3921" + Position [345, 1810, 375, 1840] + } + Block { + BlockType Constant + Name "Constant26" + SID "3922" + Position [375, 1950, 405, 1980] + Value "2" + } + Block { + BlockType Constant + Name "Constant27" + SID "3923" + Position [345, 2020, 375, 2050] + } + Block { + BlockType Constant + Name "Constant28" + SID "3924" + Position [375, 2180, 405, 2210] + Value "2" + } + Block { + BlockType Constant + Name "Constant29" + SID "3925" + Position [345, 2250, 375, 2280] + } + Block { + BlockType Constant + Name "Constant30" + SID "3926" + Position [375, 2425, 405, 2455] + Value "2" + } + Block { + BlockType Constant + Name "Constant31" + SID "3927" + Position [345, 2495, 375, 2525] + } + Block { + BlockType Constant + Name "Constant32" + SID "3928" + Position [375, 2680, 405, 2710] + Value "2" + } + Block { + BlockType Constant + Name "Constant33" + SID "3929" + Position [345, 2750, 375, 2780] + } + Block { + BlockType Constant + Name "Constant34" + SID "3930" + Position [375, 2945, 405, 2975] + Value "2" + } + Block { + BlockType Constant + Name "Constant35" + SID "3931" + Position [345, 3015, 375, 3045] + } + Block { + BlockType Constant + Name "Constant36" + SID "3932" + Position [375, 3220, 405, 3250] + Value "2" + } + Block { + BlockType Constant + Name "Constant37" + SID "3933" + Position [345, 3290, 375, 3320] + } + Block { + BlockType Constant + Name "Constant38" + SID "3934" + Position [375, 3500, 405, 3530] + Value "2" + } + Block { + BlockType Constant + Name "Constant39" + SID "3935" + Position [345, 3570, 375, 3600] + } + Block { + BlockType Constant + Name "Constant40" + SID "3936" + Position [375, 3790, 405, 3820] + Value "2" + } + Block { + BlockType Constant + Name "Constant41" + SID "3937" + Position [345, 3860, 375, 3890] + } + Block { + BlockType Constant + Name "Constant42" + SID "3938" + Position [375, 4085, 405, 4115] + Value "2" + } + Block { + BlockType Constant + Name "Constant43" + SID "3939" + Position [345, 4155, 375, 4185] + } + Block { + BlockType Constant + Name "Constant44" + SID "3940" + Position [375, 4390, 405, 4420] + Value "2" + } + Block { + BlockType Constant + Name "Constant45" + SID "3941" + Position [345, 4460, 375, 4490] + } + Block { + BlockType Constant + Name "Constant46" + SID "3942" + Position [375, 4700, 405, 4730] + Value "2" + } + Block { + BlockType Constant + Name "Constant47" + SID "3943" + Position [345, 4770, 375, 4800] + } + Block { + BlockType Constant + Name "Constant48" + SID "3944" + Position [380, 5015, 410, 5045] + Value "2" + } + Block { + BlockType Constant + Name "Constant49" + SID "3945" + Position [350, 5085, 380, 5115] + } + Block { + BlockType Constant + Name "Constant50" + SID "3946" + Position [380, 5335, 410, 5365] + Value "2" + } + Block { + BlockType Constant + Name "Constant51" + SID "3947" + Position [350, 5405, 380, 5435] + } + Block { + BlockType Constant + Name "Constant52" + SID "3948" + Position [380, 5660, 410, 5690] + Value "2" + } + Block { + BlockType Constant + Name "Constant53" + SID "3949" + Position [350, 5730, 380, 5760] + } + Block { + BlockType Constant + Name "Constant8" + SID "3950" + Position [365, 330, 395, 360] + Value "2" + } + Block { + BlockType Display + Name "Display1" + SID "3951" + Ports [1] + Position [730, 507, 820, 533] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display2" + SID "3952" + Ports [1] + Position [775, 657, 865, 683] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display3" + SID "3953" + Ports [1] + Position [740, 857, 830, 883] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "3954" + Ports [1] + Position [770, 1057, 860, 1083] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display5" + SID "3955" + Ports [1] + Position [735, 332, 825, 358] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display6" + SID "3956" + Ports [1] + Position [770, 1187, 860, 1213] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display7" + SID "3957" + Ports [1] + Position [640, 197, 730, 223] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display8" + SID "3958" + Ports [1] + Position [490, 317, 580, 343] + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction1" + SID "3959" + Ports [2, 1] + Position [420, 177, 450, 208] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction10" + SID "3960" + Ports [2, 1] + Position [435, 1772, 465, 1803] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction11" + SID "3961" + Ports [2, 1] + Position [435, 1982, 465, 2013] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction12" + SID "3962" + Ports [2, 1] + Position [435, 2212, 465, 2243] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction13" + SID "3963" + Ports [2, 1] + Position [435, 2457, 465, 2488] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction14" + SID "3964" + Ports [2, 1] + Position [435, 2712, 465, 2743] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction15" + SID "3965" + Ports [2, 1] + Position [435, 2977, 465, 3008] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction16" + SID "3966" + Ports [2, 1] + Position [435, 3252, 465, 3283] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction17" + SID "3967" + Ports [2, 1] + Position [435, 3532, 465, 3563] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction18" + SID "3968" + Ports [2, 1] + Position [435, 3822, 465, 3853] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction19" + SID "3969" + Ports [2, 1] + Position [435, 4117, 465, 4148] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction2" + SID "3970" + Ports [2, 1] + Position [425, 362, 455, 393] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction20" + SID "3971" + Ports [2, 1] + Position [435, 4422, 465, 4453] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction21" + SID "3972" + Ports [2, 1] + Position [435, 4732, 465, 4763] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction22" + SID "3973" + Ports [2, 1] + Position [440, 5047, 470, 5078] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction23" + SID "3974" + Ports [2, 1] + Position [440, 5367, 470, 5398] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction24" + SID "3975" + Ports [2, 1] + Position [440, 5692, 470, 5723] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction3" + SID "3976" + Ports [2, 1] + Position [425, 512, 455, 543] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction4" + SID "3977" + Ports [2, 1] + Position [430, 672, 460, 703] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction5" + SID "3978" + Ports [2, 1] + Position [435, 842, 465, 873] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction6" + SID "3979" + Ports [2, 1] + Position [435, 1022, 465, 1053] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction7" + SID "3980" + Ports [2, 1] + Position [435, 1202, 465, 1233] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction8" + SID "3981" + Ports [2, 1] + Position [435, 1382, 465, 1413] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction9" + SID "3982" + Ports [2, 1] + Position [435, 1572, 465, 1603] + Operator "pow" + } + Block { + BlockType Product + Name "Product1" + SID "3983" + Ports [2, 1] + Position [555, 202, 585, 233] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product10" + SID "3984" + Ports [2, 1] + Position [570, 1797, 600, 1828] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product11" + SID "3985" + Ports [2, 1] + Position [570, 2007, 600, 2038] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product12" + SID "3986" + Ports [2, 1] + Position [570, 2237, 600, 2268] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product13" + SID "3987" + Ports [2, 1] + Position [570, 2482, 600, 2513] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product14" + SID "3988" + Ports [2, 1] + Position [570, 2737, 600, 2768] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product15" + SID "3989" + Ports [2, 1] + Position [570, 3002, 600, 3033] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product16" + SID "3990" + Ports [2, 1] + Position [570, 3277, 600, 3308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product17" + SID "3991" + Ports [2, 1] + Position [570, 3557, 600, 3588] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product18" + SID "3992" + Ports [2, 1] + Position [570, 3847, 600, 3878] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product19" + SID "3993" + Ports [2, 1] + Position [570, 4142, 600, 4173] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product2" + SID "3994" + Ports [2, 1] + Position [560, 387, 590, 418] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product20" + SID "3995" + Ports [2, 1] + Position [570, 4447, 600, 4478] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product21" + SID "3996" + Ports [2, 1] + Position [570, 4757, 600, 4788] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product22" + SID "3997" + Ports [2, 1] + Position [575, 5072, 605, 5103] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product23" + SID "3998" + Ports [2, 1] + Position [575, 5392, 605, 5423] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product24" + SID "3999" + Ports [2, 1] + Position [575, 5717, 605, 5748] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product3" + SID "4000" + Ports [2, 1] + Position [560, 537, 590, 568] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product4" + SID "4001" + Ports [2, 1] + Position [565, 697, 595, 728] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product5" + SID "4002" + Ports [2, 1] + Position [570, 867, 600, 898] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product6" + SID "4003" + Ports [2, 1] + Position [570, 1047, 600, 1078] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product7" + SID "4004" + Ports [2, 1] + Position [570, 1227, 600, 1258] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product8" + SID "4005" + Ports [2, 1] + Position [570, 1407, 600, 1438] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product9" + SID "4006" + Ports [2, 1] + Position [570, 1597, 600, 1628] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum1" + SID "4007" + Ports [2, 1] + Position [380, 380, 400, 400] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum10" + SID "4008" + Ports [2, 1] + Position [380, 1400, 400, 1420] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum11" + SID "4009" + Ports [2, 1] + Position [380, 1590, 400, 1610] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum12" + SID "4010" + Ports [2, 1] + Position [380, 1790, 400, 1810] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum13" + SID "4011" + Ports [2, 1] + Position [380, 2000, 400, 2020] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum14" + SID "4012" + Ports [2, 1] + Position [380, 2230, 400, 2250] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum15" + SID "4013" + Ports [2, 1] + Position [380, 2475, 400, 2495] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum16" + SID "4014" + Ports [2, 1] + Position [380, 2730, 400, 2750] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum17" + SID "4015" + Ports [2, 1] + Position [380, 2995, 400, 3015] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum18" + SID "4016" + Ports [2, 1] + Position [380, 3270, 400, 3290] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum19" + SID "4017" + Ports [2, 1] + Position [380, 3550, 400, 3570] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum20" + SID "4018" + Ports [2, 1] + Position [380, 3840, 400, 3860] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum21" + SID "4019" + Ports [2, 1] + Position [380, 4135, 400, 4155] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum22" + SID "4020" + Ports [2, 1] + Position [380, 4440, 400, 4460] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum23" + SID "4021" + Ports [2, 1] + Position [380, 4750, 400, 4770] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum24" + SID "4022" + Ports [2, 1] + Position [385, 5065, 405, 5085] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum25" + SID "4023" + Ports [2, 1] + Position [385, 5385, 405, 5405] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum26" + SID "4024" + Ports [2, 1] + Position [385, 5710, 405, 5730] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum27" + SID "4025" + Ports [24, 1] + Position [760, 3171, 820, 3479] + ShowName off + Inputs "|++++++++++++++++++++++++" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum5" + SID "4026" + Ports [2, 1] + Position [370, 530, 390, 550] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum6" + SID "4027" + Ports [2, 1] + Position [375, 690, 395, 710] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum7" + SID "4028" + Ports [2, 1] + Position [380, 860, 400, 880] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum8" + SID "4029" + Ports [2, 1] + Position [380, 1040, 400, 1060] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum9" + SID "4030" + Ports [2, 1] + Position [380, 1220, 400, 1240] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "Out1" + SID "4031" + Position [845, 3318, 875, 3332] + IconDisplay "Port number" + } + Line { + SrcBlock "Product1" + SrcPort 1 + Points [15, 0] + Branch { + Points [110, 0; 0, 3225] + DstBlock "Sum27" + DstPort 24 + } + Branch { + Points [0, -10] + DstBlock "Display7" + DstPort 1 + } + } + Line { + SrcBlock "Sum1" + SrcPort 1 + Points [0, -5] + Branch { + Points [-50, 0] + DstBlock "Sum5" + DstPort 1 + } + Branch { + Points [5, 0] + Branch { + Points [0, -55] + DstBlock "Display8" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction2" + DstPort 2 + } + } + } + Line { + SrcBlock "Constant2" + SrcPort 1 + DstBlock "Sum1" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction1" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product1" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero1" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product1" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator1" + SrcPort 1 + DstBlock "Compare\nTo Zero1" + DstPort 1 + } + Line { + SrcBlock "Constant1" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction1" + DstPort 1 + } + Line { + SrcBlock "Sum27" + SrcPort 1 + DstBlock "Out1" + DstPort 1 + } + Line { + SrcBlock "In2" + SrcPort 1 + Points [15, 0] + Branch { + Points [0, -105] + DstBlock "Bitwise\nOperator1" + DstPort 1 + } + Branch { + Points [0, 80] + Branch { + Points [0, 150] + Branch { + Points [0, 155] + Branch { + Points [0, 175] + Branch { + Points [0, 180; 5, 0] + Branch { + Points [-5, 0; 0, 175] + Branch { + Points [0, 185] + Branch { + Points [0, 190] + Branch { + Points [0, 195] + Branch { + Points [0, 215] + Branch { + Points [0, 230] + Branch { + Points [0, 240] + Branch { + Points [0, 260] + Branch { + Points [0, 265] + Branch { + Points [0, 275] + Branch { + Points [0, 280] + Branch { + Points [0, 285] + Branch { + Points [0, 300] + Branch { + Points [0, 305] + Branch { + Points [0, 310] + Branch { + Points [0, 315] + Branch { + Points [0, 320] + Branch { + Points [0, 325] + DstBlock "Bitwise\nOperator28" + DstPort 1 + } + Branch { + DstBlock "Bitwise\nOperator27" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator26" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator25" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator24" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator23" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator22" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator21" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator20" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator19" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator18" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator17" + DstPort 1 + } + } + Branch { + DstBlock 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DstPort 1 + } + Branch { + DstBlock "Display3" + DstPort 1 + } + } + } + } + Block { + BlockType Outport + Name "enable_tracking" + SID "4037" + Position [440, 113, 470, 127] + IconDisplay "Port number" + OutputWhenDisabled "reset" + InitialOutput "0" + } + Line { + SrcBlock "In1" + SrcPort 1 + DstBlock "Data Type \nConversion3" + DstPort 1 + } + Line { + SrcBlock "In2" + SrcPort 1 + DstBlock "Data Type \nConversion2" + DstPort 1 + } + Line { + SrcBlock "In3" + SrcPort 1 + DstBlock "Data Type \nConversion1" + DstPort 1 + } + Line { + SrcBlock "In4" + SrcPort 1 + DstBlock "Data Type \nConversion4" + DstPort 1 + } + Line { + SrcBlock "Data Type \nConversion3" + SrcPort 1 + DstBlock "hex2float" + DstPort 4 + } + Line { + SrcBlock "Data Type \nConversion2" + SrcPort 1 + DstBlock "hex2float" + DstPort 3 + } + Line { + SrcBlock "Data Type \nConversion1" + SrcPort 1 + DstBlock "hex2float" + DstPort 2 + } + Line { + SrcBlock "Data Type \nConversion4" + SrcPort 1 + DstBlock "hex2float" + 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Position [425, 1266, 465, 1304] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000100000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator12" + SID "4085" + Ports [1, 1] + Position [425, 1446, 465, 1484] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000010000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator13" + SID "4086" + Ports [1, 1] + Position [425, 1636, 465, 1674] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000001000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator14" + SID "4087" + Ports [1, 1] + Position [425, 1836, 465, 1874] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000100000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator15" + SID "4088" + Ports [1, 1] + Position [425, 2046, 465, 2084] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000010000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator16" + SID "4089" + Ports [1, 1] + Position [425, 2276, 465, 2314] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000001000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator17" + SID "4090" + Ports [1, 1] + Position [425, 2521, 465, 2559] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000100000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator18" + SID "4091" + Ports [1, 1] + Position [425, 2776, 465, 2814] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000010000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator19" + SID "4092" + Ports [1, 1] + Position [425, 3041, 465, 3079] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000001000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator20" + SID "4093" + Ports [1, 1] + Position [425, 3316, 465, 3354] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000100000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator21" + SID "4094" + Ports [1, 1] + Position [425, 3596, 465, 3634] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000010000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator22" + SID "4095" + Ports [1, 1] + Position [425, 3886, 465, 3924] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000001000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator23" + SID "4096" + Ports [1, 1] + Position [425, 4181, 465, 4219] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000100000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator24" + SID "4097" + Ports [1, 1] + Position [425, 4486, 465, 4524] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000010000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator25" + SID "4098" + Ports [1, 1] + Position [425, 4796, 465, 4834] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000001000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator26" + SID "4099" + Ports [1, 1] + Position [430, 5111, 470, 5149] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000100')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator27" + SID "4100" + Ports [1, 1] + Position [430, 5431, 470, 5469] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000010')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator28" + SID "4101" + Ports [1, 1] + Position [430, 5756, 470, 5794] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000001')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator6" + SID "4102" + Ports [1, 1] + Position [415, 426, 455, 464] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0010000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator7" + SID "4103" + Ports [1, 1] + Position [415, 576, 455, 614] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0001000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator8" + SID "4104" + Ports [1, 1] + Position [420, 736, 460, 774] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000100000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator9" + SID "4105" + Ports [1, 1] + Position [425, 906, 465, 944] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000010000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Compare\nTo Zero1" + SID "4106" + Ports [1, 1] + Position [480, 245, 510, 275] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero10" + SID "4107" + Ports [1, 1] + Position [495, 1840, 525, 1870] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero11" + SID "4108" + Ports [1, 1] + Position [495, 2050, 525, 2080] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero12" + SID "4109" + Ports [1, 1] + Position [495, 2280, 525, 2310] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero13" + SID "4110" + Ports [1, 1] + Position [495, 2525, 525, 2555] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero14" + SID "4111" + Ports [1, 1] + Position [495, 2780, 525, 2810] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero15" + SID "4112" + Ports [1, 1] + Position [495, 3045, 525, 3075] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero16" + SID "4113" + Ports [1, 1] + Position [495, 3320, 525, 3350] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero17" + SID "4114" + Ports [1, 1] + Position [495, 3600, 525, 3630] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero18" + SID "4115" + Ports [1, 1] + Position [495, 3890, 525, 3920] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero19" + SID "4116" + Ports [1, 1] + Position [495, 4185, 525, 4215] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero2" + SID "4117" + Ports [1, 1] + Position [485, 430, 515, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero20" + SID "4118" + Ports [1, 1] + Position [495, 4490, 525, 4520] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero21" + SID "4119" + Ports [1, 1] + Position [495, 4800, 525, 4830] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero22" + SID "4120" + Ports [1, 1] + Position [500, 5115, 530, 5145] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero23" + SID "4121" + Ports [1, 1] + Position [500, 5435, 530, 5465] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero24" + SID "4122" + Ports [1, 1] + Position [500, 5760, 530, 5790] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero3" + SID "4123" + Ports [1, 1] + Position [485, 580, 515, 610] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero4" + SID "4124" + Ports [1, 1] + Position [490, 740, 520, 770] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero5" + SID "4125" + Ports [1, 1] + Position [495, 910, 525, 940] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero6" + SID "4126" + Ports [1, 1] + Position [495, 1090, 525, 1120] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero7" + SID "4127" + Ports [1, 1] + Position [495, 1270, 525, 1300] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero8" + SID "4128" + Ports [1, 1] + Position [495, 1450, 525, 1480] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero9" + SID "4129" + Ports [1, 1] + Position [495, 1640, 525, 1670] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Constant + Name "Constant1" + SID "4130" + Position [360, 145, 390, 175] + Value "2" + } + Block { + BlockType Constant + Name "Constant10" + SID "4131" + Position [365, 480, 395, 510] + Value "2" + } + Block { + BlockType Constant + Name "Constant11" + SID "4132" + Position [335, 550, 365, 580] + } + Block { + BlockType Constant + Name "Constant12" + SID "4133" + Position [370, 640, 400, 670] + Value "2" + } + Block { + BlockType Constant + Name "Constant13" + SID "4134" + Position [340, 710, 370, 740] + } + Block { + BlockType Constant + Name "Constant14" + SID "4135" + Position [375, 810, 405, 840] + Value "2" + } + Block { + BlockType Constant + Name "Constant15" + SID "4136" + Position [345, 880, 375, 910] + } + Block { + BlockType Constant + Name "Constant16" + SID "4137" + Position [375, 990, 405, 1020] + Value "2" + } + Block { + BlockType Constant + Name "Constant17" + SID "4138" + Position [345, 1060, 375, 1090] + } + Block { + BlockType Constant + Name "Constant18" + SID "4139" + Position [375, 1170, 405, 1200] + Value "2" + } + Block { + BlockType Constant + Name "Constant19" + SID "4140" + Position [345, 1240, 375, 1270] + } + Block { + BlockType Constant + Name "Constant2" + SID "4141" + Position [345, 400, 375, 430] + } + Block { + BlockType Constant + Name "Constant20" + SID "4142" + Position [375, 1350, 405, 1380] + Value "2" + } + Block { + BlockType Constant + Name "Constant21" + SID "4143" + Position [345, 1420, 375, 1450] + } + Block { + BlockType Constant + Name "Constant22" + SID "4144" + Position [375, 1540, 405, 1570] + Value "2" + } + Block { + BlockType Constant + Name "Constant23" + SID "4145" + Position [345, 1610, 375, 1640] + } + Block { + BlockType Constant + Name "Constant24" + SID "4146" + Position [375, 1740, 405, 1770] + Value "2" + } + Block { + BlockType Constant + Name "Constant25" + SID "4147" + Position [345, 1810, 375, 1840] + } + Block { + BlockType Constant + Name "Constant26" + SID "4148" + Position [375, 1950, 405, 1980] + Value "2" + } + Block { + BlockType Constant + Name "Constant27" + SID "4149" + Position [345, 2020, 375, 2050] + } + Block { + BlockType Constant + Name "Constant28" + SID "4150" + Position [375, 2180, 405, 2210] + Value "2" + } + Block { + BlockType Constant + Name "Constant29" + SID "4151" + Position [345, 2250, 375, 2280] + } + Block { + BlockType Constant + Name "Constant30" + SID "4152" + Position [375, 2425, 405, 2455] + Value "2" + } + Block { + BlockType Constant + Name "Constant31" + SID "4153" + Position [345, 2495, 375, 2525] + } + Block { + BlockType Constant + Name "Constant32" + SID "4154" + Position [375, 2680, 405, 2710] + Value "2" + } + Block { + BlockType Constant + Name "Constant33" + SID "4155" + Position [345, 2750, 375, 2780] + } + Block { + BlockType Constant + Name "Constant34" + SID "4156" + Position [375, 2945, 405, 2975] + Value "2" + } + Block { + BlockType Constant + Name "Constant35" + SID "4157" + Position [345, 3015, 375, 3045] + } + Block { + BlockType Constant + Name "Constant36" + SID "4158" + Position [375, 3220, 405, 3250] + Value "2" + } + Block { + BlockType Constant + Name "Constant37" + SID "4159" + Position [345, 3290, 375, 3320] + } + Block { + BlockType Constant + Name "Constant38" + SID "4160" + Position [375, 3500, 405, 3530] + Value "2" + } + Block { + BlockType Constant + Name "Constant39" + SID "4161" + Position [345, 3570, 375, 3600] + } + Block { + BlockType Constant + Name "Constant40" + SID "4162" + Position [375, 3790, 405, 3820] + Value "2" + } + Block { + BlockType Constant + Name "Constant41" + SID "4163" + Position [345, 3860, 375, 3890] + } + Block { + BlockType Constant + Name "Constant42" + SID "4164" + Position [375, 4085, 405, 4115] + Value "2" + } + Block { + BlockType Constant + Name "Constant43" + SID "4165" + Position [345, 4155, 375, 4185] + } + Block { + BlockType Constant + Name "Constant44" + SID "4166" + Position [375, 4390, 405, 4420] + Value "2" + } + Block { + BlockType Constant + Name "Constant45" + SID "4167" + Position [345, 4460, 375, 4490] + } + Block { + BlockType Constant + Name "Constant46" + SID "4168" + Position [375, 4700, 405, 4730] + Value "2" + } + Block { + BlockType Constant + Name "Constant47" + SID "4169" + Position [345, 4770, 375, 4800] + } + Block { + BlockType Constant + Name "Constant48" + SID "4170" + Position [380, 5015, 410, 5045] + Value "2" + } + Block { + BlockType Constant + Name "Constant49" + SID "4171" + Position [350, 5085, 380, 5115] + } + Block { + BlockType Constant + Name "Constant50" + SID "4172" + Position [380, 5335, 410, 5365] + Value "2" + } + Block { + BlockType Constant + Name "Constant51" + SID "4173" + Position [350, 5405, 380, 5435] + } + Block { + BlockType Constant + Name "Constant52" + SID "4174" + Position [380, 5660, 410, 5690] + Value "2" + } + Block { + BlockType Constant + Name "Constant53" + SID "4175" + Position [350, 5730, 380, 5760] + } + Block { + BlockType Constant + Name "Constant8" + SID "4176" + Position [365, 330, 395, 360] + Value "2" + } + Block { + BlockType Display + Name "Display1" + SID "4177" + Ports [1] + Position [730, 507, 820, 533] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display2" + SID "4178" + Ports [1] + Position [775, 657, 865, 683] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display3" + SID "4179" + Ports [1] + Position [740, 857, 830, 883] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "4180" + Ports [1] + Position [770, 1057, 860, 1083] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display5" + SID "4181" + Ports [1] + Position [735, 332, 825, 358] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display6" + SID "4182" + Ports [1] + Position [770, 1187, 860, 1213] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display7" + SID "4183" + Ports [1] + Position [640, 197, 730, 223] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display8" + SID "4184" + Ports [1] + Position [490, 317, 580, 343] + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction1" + SID "4185" + Ports [2, 1] + Position [420, 177, 450, 208] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction10" + SID "4186" + Ports [2, 1] + Position [435, 1772, 465, 1803] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction11" + SID "4187" + Ports [2, 1] + Position [435, 1982, 465, 2013] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction12" + SID "4188" + Ports [2, 1] + Position [435, 2212, 465, 2243] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction13" + SID "4189" + Ports [2, 1] + Position [435, 2457, 465, 2488] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction14" + SID "4190" + Ports [2, 1] + Position [435, 2712, 465, 2743] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction15" + SID "4191" + Ports [2, 1] + Position [435, 2977, 465, 3008] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction16" + SID "4192" + Ports [2, 1] + Position [435, 3252, 465, 3283] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction17" + SID "4193" + Ports [2, 1] + Position [435, 3532, 465, 3563] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction18" + SID "4194" + Ports [2, 1] + Position [435, 3822, 465, 3853] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction19" + SID "4195" + Ports [2, 1] + Position [435, 4117, 465, 4148] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction2" + SID "4196" + Ports [2, 1] + Position [425, 362, 455, 393] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction20" + SID "4197" + Ports [2, 1] + Position [435, 4422, 465, 4453] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction21" + SID "4198" + Ports [2, 1] + Position [435, 4732, 465, 4763] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction22" + SID "4199" + Ports [2, 1] + Position [440, 5047, 470, 5078] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction23" + SID "4200" + Ports [2, 1] + Position [440, 5367, 470, 5398] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction24" + SID "4201" + Ports [2, 1] + Position [440, 5692, 470, 5723] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction3" + SID "4202" + Ports [2, 1] + Position [425, 512, 455, 543] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction4" + SID "4203" + Ports [2, 1] + Position [430, 672, 460, 703] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction5" + SID "4204" + Ports [2, 1] + Position [435, 842, 465, 873] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction6" + SID "4205" + Ports [2, 1] + Position [435, 1022, 465, 1053] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction7" + SID "4206" + Ports [2, 1] + Position [435, 1202, 465, 1233] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction8" + SID "4207" + Ports [2, 1] + Position [435, 1382, 465, 1413] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction9" + SID "4208" + Ports [2, 1] + Position [435, 1572, 465, 1603] + Operator "pow" + } + Block { + BlockType Product + Name "Product1" + SID "4209" + Ports [2, 1] + Position [555, 202, 585, 233] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product10" + SID "4210" + Ports [2, 1] + Position [570, 1797, 600, 1828] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product11" + SID "4211" + Ports [2, 1] + Position [570, 2007, 600, 2038] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product12" + SID "4212" + Ports [2, 1] + Position [570, 2237, 600, 2268] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product13" + SID "4213" + Ports [2, 1] + Position [570, 2482, 600, 2513] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product14" + SID "4214" + Ports [2, 1] + Position [570, 2737, 600, 2768] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product15" + SID "4215" + Ports [2, 1] + Position [570, 3002, 600, 3033] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product16" + SID "4216" + Ports [2, 1] + Position [570, 3277, 600, 3308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product17" + SID "4217" + Ports [2, 1] + Position [570, 3557, 600, 3588] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product18" + SID "4218" + Ports [2, 1] + Position [570, 3847, 600, 3878] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product19" + SID "4219" + Ports [2, 1] + Position [570, 4142, 600, 4173] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product2" + SID "4220" + Ports [2, 1] + Position [560, 387, 590, 418] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product20" + SID "4221" + Ports [2, 1] + Position [570, 4447, 600, 4478] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product21" + SID "4222" + Ports [2, 1] + Position [570, 4757, 600, 4788] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product22" + SID "4223" + Ports [2, 1] + Position [575, 5072, 605, 5103] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product23" + SID "4224" + Ports [2, 1] + Position [575, 5392, 605, 5423] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product24" + SID "4225" + Ports [2, 1] + Position [575, 5717, 605, 5748] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product3" + SID "4226" + Ports [2, 1] + Position [560, 537, 590, 568] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product4" + SID "4227" + Ports [2, 1] + Position [565, 697, 595, 728] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product5" + SID "4228" + Ports [2, 1] + Position [570, 867, 600, 898] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product6" + SID "4229" + Ports [2, 1] + Position [570, 1047, 600, 1078] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product7" + SID "4230" + Ports [2, 1] + Position [570, 1227, 600, 1258] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product8" + SID "4231" + Ports [2, 1] + Position [570, 1407, 600, 1438] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product9" + SID "4232" + Ports [2, 1] + Position [570, 1597, 600, 1628] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum1" + SID "4233" + Ports [2, 1] + Position [380, 380, 400, 400] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum10" + SID "4234" + Ports [2, 1] + Position [380, 1400, 400, 1420] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum11" + SID "4235" + Ports [2, 1] + Position [380, 1590, 400, 1610] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum12" + SID "4236" + Ports [2, 1] + Position [380, 1790, 400, 1810] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum13" + SID "4237" + Ports [2, 1] + Position [380, 2000, 400, 2020] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum14" + SID "4238" + Ports [2, 1] + Position [380, 2230, 400, 2250] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum15" + SID "4239" + Ports [2, 1] + Position [380, 2475, 400, 2495] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum16" + SID "4240" + Ports [2, 1] + Position [380, 2730, 400, 2750] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum17" + SID "4241" + Ports [2, 1] + Position [380, 2995, 400, 3015] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum18" + SID "4242" + Ports [2, 1] + Position [380, 3270, 400, 3290] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum19" + SID "4243" + Ports [2, 1] + Position [380, 3550, 400, 3570] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum20" + SID "4244" + Ports [2, 1] + Position [380, 3840, 400, 3860] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum21" + SID "4245" + Ports [2, 1] + Position [380, 4135, 400, 4155] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum22" + SID "4246" + Ports [2, 1] + Position [380, 4440, 400, 4460] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum23" + SID "4247" + Ports [2, 1] + Position [380, 4750, 400, 4770] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum24" + SID "4248" + Ports [2, 1] + Position [385, 5065, 405, 5085] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum25" + SID "4249" + Ports [2, 1] + Position [385, 5385, 405, 5405] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum26" + SID "4250" + Ports [2, 1] + Position [385, 5710, 405, 5730] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum27" + SID "4251" + Ports [24, 1] + Position [760, 3171, 820, 3479] + ShowName off + Inputs "|++++++++++++++++++++++++" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum5" + SID "4252" + Ports [2, 1] + Position [370, 530, 390, 550] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum6" + SID "4253" + Ports [2, 1] + Position [375, 690, 395, 710] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum7" + SID "4254" + Ports [2, 1] + Position [380, 860, 400, 880] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum8" + SID "4255" + Ports [2, 1] + Position [380, 1040, 400, 1060] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum9" + SID "4256" + Ports [2, 1] + Position [380, 1220, 400, 1240] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "Out1" + SID "4257" + Position [845, 3318, 875, 3332] + IconDisplay "Port number" + } + Line { + SrcBlock "Product1" + SrcPort 1 + Points [15, 0] + Branch { + Points [110, 0; 0, 3225] + DstBlock "Sum27" + DstPort 24 + } + Branch { + Points [0, -10] + DstBlock "Display7" + DstPort 1 + } + } + Line { + SrcBlock "Sum1" + SrcPort 1 + Points [0, -5] + Branch { + Points [-50, 0] + DstBlock "Sum5" + DstPort 1 + } + Branch { + Points [5, 0] + Branch { + Points [0, -55] + DstBlock "Display8" + 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model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "7" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic3" + SID "4264:47" + Ports [1, 1] + Position [370, 335, 450, 375] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-16" + nBinPtShiftRight "0" + } + Block { + BlockType Reference + Name "Shift\nArithmetic4" + SID "4264:48" + Ports [1, 1] + Position [375, 420, 455, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Shift\nArithmetic" + SourceType "Shift Arithmetic" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + nBitShiftRight "-8" + nBinPtShiftRight "0" + } + Block { + BlockType Display + Name "Sign" + SID "4264:49" + Ports [1] + Position [480, 32, 570, 58] + BackgroundColor "cyan" + Format "binary (Stored Integer)" + Decimation "1" + Lockdown off + } + Block { + BlockType SubSystem + Name "Subsystem" + SID "4264:50" + Ports [2, 1] + Position [1125, 350, 1165, 410] + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "Subsystem" + Location [2, 82, 1653, 1004] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "In1" + SID "4264:51" + Position [25, 235, 55, 250] + BlockRotation 270 + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "In2" + SID "4264:52" + Position [220, 358, 250, 372] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Reference + Name "Bitwise\nOperator1" + SID "4264:53" + Ports [1, 1] + Position [410, 241, 450, 279] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0100000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator10" + SID "4264:54" + Ports [1, 1] + Position [425, 1086, 465, 1124] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000001000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator11" + SID "4264:55" + Ports [1, 1] + Position [425, 1266, 465, 1304] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000100000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator12" + SID "4264:56" + Ports [1, 1] + Position [425, 1446, 465, 1484] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000010000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator13" + SID "4264:57" + Ports [1, 1] + Position [425, 1636, 465, 1674] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000001000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator14" + SID "4264:58" + Ports [1, 1] + Position [425, 1836, 465, 1874] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000100000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator15" + SID "4264:59" + Ports [1, 1] + Position [425, 2046, 465, 2084] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000010000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator16" + SID "4264:60" + Ports [1, 1] + Position [425, 2276, 465, 2314] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000001000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator17" + SID "4264:61" + Ports [1, 1] + Position [425, 2521, 465, 2559] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000100000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator18" + SID "4264:62" + Ports [1, 1] + Position [425, 2776, 465, 2814] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000010000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator19" + SID "4264:63" + Ports [1, 1] + Position [425, 3041, 465, 3079] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000001000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator20" + SID "4264:64" + Ports [1, 1] + Position [425, 3316, 465, 3354] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000100000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator21" + SID "4264:65" + Ports [1, 1] + Position [425, 3596, 465, 3634] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000010000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator22" + SID "4264:66" + Ports [1, 1] + Position [425, 3886, 465, 3924] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000001000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator23" + SID "4264:67" + Ports [1, 1] + Position [425, 4181, 465, 4219] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000100000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator24" + SID "4264:68" + Ports [1, 1] + Position [425, 4486, 465, 4524] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000010000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator25" + SID "4264:69" + Ports [1, 1] + Position [425, 4796, 465, 4834] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000001000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator26" + SID "4264:70" + Ports [1, 1] + Position [430, 5111, 470, 5149] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000100')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator27" + SID "4264:71" + Ports [1, 1] + Position [430, 5431, 470, 5469] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000010')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator28" + SID "4264:72" + Ports [1, 1] + Position [430, 5756, 470, 5794] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000000000000000000000001')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator6" + SID "4264:73" + Ports [1, 1] + Position [415, 426, 455, 464] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0010000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator7" + SID "4264:74" + Ports [1, 1] + Position [415, 576, 455, 614] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0001000000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator8" + SID "4264:75" + Ports [1, 1] + Position [420, 736, 460, 774] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000100000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Bitwise\nOperator9" + SID "4264:76" + Ports [1, 1] + Position [425, 906, 465, 944] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Bitwise\nOperator" + SourceType "Bitwise Operator" + logicop "AND" + UseBitMask on + NumInputPorts "1" + BitMask "bin2dec('0000010000000000000000000')" + BitMaskRealWorld "Stored Integer" + } + Block { + BlockType Reference + Name "Compare\nTo Zero1" + SID "4264:77" + Ports [1, 1] + Position [480, 245, 510, 275] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero10" + SID "4264:78" + Ports [1, 1] + Position [495, 1840, 525, 1870] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero11" + SID "4264:79" + Ports [1, 1] + Position [495, 2050, 525, 2080] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero12" + SID "4264:80" + Ports [1, 1] + Position [495, 2280, 525, 2310] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero13" + SID "4264:81" + Ports [1, 1] + Position [495, 2525, 525, 2555] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero14" + SID "4264:82" + Ports [1, 1] + Position [495, 2780, 525, 2810] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero15" + SID "4264:83" + Ports [1, 1] + Position [495, 3045, 525, 3075] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero16" + SID "4264:84" + Ports [1, 1] + Position [495, 3320, 525, 3350] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero17" + SID "4264:85" + Ports [1, 1] + Position [495, 3600, 525, 3630] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero18" + SID "4264:86" + Ports [1, 1] + Position [495, 3890, 525, 3920] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero19" + SID "4264:87" + Ports [1, 1] + Position [495, 4185, 525, 4215] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero2" + SID "4264:88" + Ports [1, 1] + Position [485, 430, 515, 460] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero20" + SID "4264:89" + Ports [1, 1] + Position [495, 4490, 525, 4520] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero21" + SID "4264:90" + Ports [1, 1] + Position [495, 4800, 525, 4830] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero22" + SID "4264:91" + Ports [1, 1] + Position [500, 5115, 530, 5145] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero23" + SID "4264:92" + Ports [1, 1] + Position [500, 5435, 530, 5465] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero24" + SID "4264:93" + Ports [1, 1] + Position [500, 5760, 530, 5790] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero3" + SID "4264:94" + Ports [1, 1] + Position [485, 580, 515, 610] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero4" + SID "4264:95" + Ports [1, 1] + Position [490, 740, 520, 770] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero5" + SID "4264:96" + Ports [1, 1] + Position [495, 910, 525, 940] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero6" + SID "4264:97" + Ports [1, 1] + Position [495, 1090, 525, 1120] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero7" + SID "4264:98" + Ports [1, 1] + Position [495, 1270, 525, 1300] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero8" + SID "4264:99" + Ports [1, 1] + Position [495, 1450, 525, 1480] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Reference + Name "Compare\nTo Zero9" + SID "4264:100" + Ports [1, 1] + Position [495, 1640, 525, 1670] + LibraryVersion "1.308" + SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero" + SourceType "Compare To Zero" + ShowPortLabels "FromPortIcon" + SystemSampleTime "-1" + FunctionWithSeparateData off + RTWMemSecFuncInitTerm "Inherit from model" + RTWMemSecFuncExecute "Inherit from model" + RTWMemSecDataConstants "Inherit from model" + RTWMemSecDataInternal "Inherit from model" + RTWMemSecDataParameters "Inherit from model" + GeneratePreprocessorConditionals off + relop ">" + LogicOutDataTypeMode "uint8" + ZeroCross off + } + Block { + BlockType Constant + Name "Constant1" + SID "4264:101" + Position [360, 145, 390, 175] + Value "2" + } + Block { + BlockType Constant + Name "Constant10" + SID "4264:102" + Position [365, 480, 395, 510] + Value "2" + } + Block { + BlockType Constant + Name "Constant11" + SID "4264:103" + Position [335, 550, 365, 580] + } + Block { + BlockType Constant + Name "Constant12" + SID "4264:104" + Position [370, 640, 400, 670] + Value "2" + } + Block { + BlockType Constant + Name "Constant13" + SID "4264:105" + Position [340, 710, 370, 740] + } + Block { + BlockType Constant + Name "Constant14" + SID "4264:106" + Position [375, 810, 405, 840] + Value "2" + } + Block { + BlockType Constant + Name "Constant15" + SID "4264:107" + Position [345, 880, 375, 910] + } + Block { + BlockType Constant + Name "Constant16" + SID "4264:108" + Position [375, 990, 405, 1020] + Value "2" + } + Block { + BlockType Constant + Name "Constant17" + SID "4264:109" + Position [345, 1060, 375, 1090] + } + Block { + BlockType Constant + Name "Constant18" + SID "4264:110" + Position [375, 1170, 405, 1200] + Value "2" + } + Block { + BlockType Constant + Name "Constant19" + SID "4264:111" + Position [345, 1240, 375, 1270] + } + Block { + BlockType Constant + Name "Constant2" + SID "4264:112" + Position [345, 400, 375, 430] + } + Block { + BlockType Constant + Name "Constant20" + SID "4264:113" + Position [375, 1350, 405, 1380] + Value "2" + } + Block { + BlockType Constant + Name "Constant21" + SID "4264:114" + Position [345, 1420, 375, 1450] + } + Block { + BlockType Constant + Name "Constant22" + SID "4264:115" + Position [375, 1540, 405, 1570] + Value "2" + } + Block { + BlockType Constant + Name "Constant23" + SID "4264:116" + Position [345, 1610, 375, 1640] + } + Block { + BlockType Constant + Name "Constant24" + SID "4264:117" + Position [375, 1740, 405, 1770] + Value "2" + } + Block { + BlockType Constant + Name "Constant25" + SID "4264:118" + Position [345, 1810, 375, 1840] + } + Block { + BlockType Constant + Name "Constant26" + SID "4264:119" + Position [375, 1950, 405, 1980] + Value "2" + } + Block { + BlockType Constant + Name "Constant27" + SID "4264:120" + Position [345, 2020, 375, 2050] + } + Block { + BlockType Constant + Name "Constant28" + SID "4264:121" + Position [375, 2180, 405, 2210] + Value "2" + } + Block { + BlockType Constant + Name "Constant29" + SID "4264:122" + Position [345, 2250, 375, 2280] + } + Block { + BlockType Constant + Name "Constant30" + SID "4264:123" + Position [375, 2425, 405, 2455] + Value "2" + } + Block { + BlockType Constant + Name "Constant31" + SID "4264:124" + Position [345, 2495, 375, 2525] + } + Block { + BlockType Constant + Name "Constant32" + SID "4264:125" + Position [375, 2680, 405, 2710] + Value "2" + } + Block { + BlockType Constant + Name "Constant33" + SID "4264:126" + Position [345, 2750, 375, 2780] + } + Block { + BlockType Constant + Name "Constant34" + SID "4264:127" + Position [375, 2945, 405, 2975] + Value "2" + } + Block { + BlockType Constant + Name "Constant35" + SID "4264:128" + Position [345, 3015, 375, 3045] + } + Block { + BlockType Constant + Name "Constant36" + SID "4264:129" + Position [375, 3220, 405, 3250] + Value "2" + } + Block { + BlockType Constant + Name "Constant37" + SID "4264:130" + Position [345, 3290, 375, 3320] + } + Block { + BlockType Constant + Name "Constant38" + SID "4264:131" + Position [375, 3500, 405, 3530] + Value "2" + } + Block { + BlockType Constant + Name "Constant39" + SID "4264:132" + Position [345, 3570, 375, 3600] + } + Block { + BlockType Constant + Name "Constant40" + SID "4264:133" + Position [375, 3790, 405, 3820] + Value "2" + } + Block { + BlockType Constant + Name "Constant41" + SID "4264:134" + Position [345, 3860, 375, 3890] + } + Block { + BlockType Constant + Name "Constant42" + SID "4264:135" + Position [375, 4085, 405, 4115] + Value "2" + } + Block { + BlockType Constant + Name "Constant43" + SID "4264:136" + Position [345, 4155, 375, 4185] + } + Block { + BlockType Constant + Name "Constant44" + SID "4264:137" + Position [375, 4390, 405, 4420] + Value "2" + } + Block { + BlockType Constant + Name "Constant45" + SID "4264:138" + Position [345, 4460, 375, 4490] + } + Block { + BlockType Constant + Name "Constant46" + SID "4264:139" + Position [375, 4700, 405, 4730] + Value "2" + } + Block { + BlockType Constant + Name "Constant47" + SID "4264:140" + Position [345, 4770, 375, 4800] + } + Block { + BlockType Constant + Name "Constant48" + SID "4264:141" + Position [380, 5015, 410, 5045] + Value "2" + } + Block { + BlockType Constant + Name "Constant49" + SID "4264:142" + Position [350, 5085, 380, 5115] + } + Block { + BlockType Constant + Name "Constant50" + SID "4264:143" + Position [380, 5335, 410, 5365] + Value "2" + } + Block { + BlockType Constant + Name "Constant51" + SID "4264:144" + Position [350, 5405, 380, 5435] + } + Block { + BlockType Constant + Name "Constant52" + SID "4264:145" + Position [380, 5660, 410, 5690] + Value "2" + } + Block { + BlockType Constant + Name "Constant53" + SID "4264:146" + Position [350, 5730, 380, 5760] + } + Block { + BlockType Constant + Name "Constant8" + SID "4264:147" + Position [365, 330, 395, 360] + Value "2" + } + Block { + BlockType Display + Name "Display1" + SID "4264:148" + Ports [1] + Position [730, 507, 820, 533] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display2" + SID "4264:149" + Ports [1] + Position [775, 657, 865, 683] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display3" + SID "4264:150" + Ports [1] + Position [740, 857, 830, 883] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display4" + SID "4264:151" + Ports [1] + Position [770, 1057, 860, 1083] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display5" + SID "4264:152" + Ports [1] + Position [735, 332, 825, 358] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display6" + SID "4264:153" + Ports [1] + Position [770, 1187, 860, 1213] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display7" + SID "4264:154" + Ports [1] + Position [640, 197, 730, 223] + Decimation "1" + Lockdown off + } + Block { + BlockType Display + Name "Display8" + SID "4264:155" + Ports [1] + Position [490, 317, 580, 343] + Decimation "1" + Lockdown off + } + Block { + BlockType Math + Name "Math\nFunction1" + SID "4264:156" + Ports [2, 1] + Position [420, 177, 450, 208] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction10" + SID "4264:157" + Ports [2, 1] + Position [435, 1772, 465, 1803] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction11" + SID 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[2, 1] + Position [435, 3822, 465, 3853] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction19" + SID "4264:166" + Ports [2, 1] + Position [435, 4117, 465, 4148] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction2" + SID "4264:167" + Ports [2, 1] + Position [425, 362, 455, 393] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction20" + SID "4264:168" + Ports [2, 1] + Position [435, 4422, 465, 4453] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction21" + SID "4264:169" + Ports [2, 1] + Position [435, 4732, 465, 4763] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction22" + SID "4264:170" + Ports [2, 1] + Position [440, 5047, 470, 5078] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction23" + SID "4264:171" + Ports [2, 1] + Position [440, 5367, 470, 5398] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction24" + SID "4264:172" + Ports [2, 1] + Position [440, 5692, 470, 5723] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction3" + SID "4264:173" + Ports [2, 1] + Position [425, 512, 455, 543] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction4" + SID "4264:174" + Ports [2, 1] + Position [430, 672, 460, 703] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction5" + SID "4264:175" + Ports [2, 1] + Position [435, 842, 465, 873] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction6" + SID "4264:176" + Ports [2, 1] + Position [435, 1022, 465, 1053] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction7" + SID "4264:177" + Ports [2, 1] + Position [435, 1202, 465, 1233] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction8" + SID "4264:178" + Ports [2, 1] + Position [435, 1382, 465, 1413] + Operator "pow" + } + Block { + BlockType Math + Name "Math\nFunction9" + SID "4264:179" + Ports [2, 1] + Position [435, 1572, 465, 1603] + Operator "pow" + } + Block { + BlockType Product + Name "Product1" + SID "4264:180" + Ports [2, 1] + Position [555, 202, 585, 233] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product10" + SID "4264:181" + Ports [2, 1] + Position [570, 1797, 600, 1828] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product11" + SID "4264:182" + Ports [2, 1] + Position [570, 2007, 600, 2038] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product12" + SID "4264:183" + Ports [2, 1] + Position [570, 2237, 600, 2268] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product13" + SID "4264:184" + Ports [2, 1] + Position [570, 2482, 600, 2513] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product14" + SID "4264:185" + Ports [2, 1] + Position [570, 2737, 600, 2768] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product15" + SID "4264:186" + Ports [2, 1] + Position [570, 3002, 600, 3033] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product16" + SID "4264:187" + Ports [2, 1] + Position [570, 3277, 600, 3308] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product17" + SID "4264:188" + Ports [2, 1] + Position [570, 3557, 600, 3588] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product18" + SID "4264:189" + Ports [2, 1] + Position [570, 3847, 600, 3878] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product19" + SID "4264:190" + Ports [2, 1] + Position [570, 4142, 600, 4173] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product2" + SID "4264:191" + Ports [2, 1] + Position [560, 387, 590, 418] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product20" + SID "4264:192" + Ports [2, 1] + Position [570, 4447, 600, 4478] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product21" + SID "4264:193" + Ports [2, 1] + Position [570, 4757, 600, 4788] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product22" + SID "4264:194" + Ports [2, 1] + Position [575, 5072, 605, 5103] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product23" + SID "4264:195" + Ports [2, 1] + Position [575, 5392, 605, 5423] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product24" + SID "4264:196" + Ports [2, 1] + Position [575, 5717, 605, 5748] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product3" + SID "4264:197" + Ports [2, 1] + Position [560, 537, 590, 568] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product4" + SID "4264:198" + Ports [2, 1] + Position [565, 697, 595, 728] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product5" + SID "4264:199" + Ports [2, 1] + Position [570, 867, 600, 898] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product6" + SID "4264:200" + Ports [2, 1] + Position [570, 1047, 600, 1078] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product7" + SID "4264:201" + Ports [2, 1] + Position [570, 1227, 600, 1258] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product8" + SID "4264:202" + Ports [2, 1] + Position [570, 1407, 600, 1438] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product9" + SID "4264:203" + Ports [2, 1] + Position [570, 1597, 600, 1628] + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum1" + SID "4264:204" + Ports [2, 1] + Position [380, 380, 400, 400] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum10" + SID "4264:205" + Ports [2, 1] + Position [380, 1400, 400, 1420] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum11" + SID "4264:206" + Ports [2, 1] + Position [380, 1590, 400, 1610] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum12" + SID "4264:207" + Ports [2, 1] + Position [380, 1790, 400, 1810] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum13" + SID "4264:208" + Ports [2, 1] + Position [380, 2000, 400, 2020] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum14" + SID "4264:209" + Ports [2, 1] + Position [380, 2230, 400, 2250] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum15" + SID "4264:210" + Ports [2, 1] + Position [380, 2475, 400, 2495] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum16" + SID "4264:211" + Ports [2, 1] + Position [380, 2730, 400, 2750] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum17" + SID "4264:212" + Ports [2, 1] + Position [380, 2995, 400, 3015] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum18" + SID "4264:213" + Ports [2, 1] + Position [380, 3270, 400, 3290] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum19" + SID "4264:214" + Ports [2, 1] + Position [380, 3550, 400, 3570] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum20" + SID "4264:215" + Ports [2, 1] + Position [380, 3840, 400, 3860] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum21" + SID "4264:216" + Ports [2, 1] + Position [380, 4135, 400, 4155] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum22" + SID "4264:217" + Ports [2, 1] + Position [380, 4440, 400, 4460] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum23" + SID "4264:218" + Ports [2, 1] + Position [380, 4750, 400, 4770] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum24" + SID "4264:219" + Ports [2, 1] + Position [385, 5065, 405, 5085] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum25" + SID "4264:220" + Ports [2, 1] + Position [385, 5385, 405, 5405] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum26" + SID "4264:221" + Ports [2, 1] + Position [385, 5710, 405, 5730] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum27" + SID "4264:222" + Ports [24, 1] + Position [760, 3171, 820, 3479] + ShowName off + Inputs "|++++++++++++++++++++++++" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum5" + SID "4264:223" + Ports [2, 1] + Position [370, 530, 390, 550] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum6" + SID "4264:224" + Ports [2, 1] + Position [375, 690, 395, 710] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum7" + SID "4264:225" + Ports [2, 1] + Position [380, 860, 400, 880] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum8" + SID "4264:226" + Ports [2, 1] + Position [380, 1040, 400, 1060] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Sum9" + SID "4264:227" + Ports [2, 1] + Position [380, 1220, 400, 1240] + ShowName off + IconShape "round" + Inputs "|+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "Out1" + SID "4264:228" + Position [845, 3318, 875, 3332] + IconDisplay "Port number" + } + Line { + SrcBlock "Product1" + SrcPort 1 + Points [15, 0] + Branch { + Points [110, 0; 0, 3225] + DstBlock "Sum27" + DstPort 24 + } + Branch { + Points [0, -10] + DstBlock "Display7" + DstPort 1 + } + } + Line { + SrcBlock "Sum1" + SrcPort 1 + Points [0, -5] + Branch { + Points [-50, 0] + DstBlock "Sum5" + DstPort 1 + } + Branch { + Points [5, 0] + Branch { + Points [0, -55] + DstBlock "Display8" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction2" + DstPort 2 + } + } + } + Line { + SrcBlock "Constant2" + SrcPort 1 + DstBlock "Sum1" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction1" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product1" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero1" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product1" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator1" + SrcPort 1 + DstBlock "Compare\nTo Zero1" + DstPort 1 + } + Line { + SrcBlock "Constant1" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction1" + DstPort 1 + } + Line { + SrcBlock "Sum27" + SrcPort 1 + DstBlock "Out1" + DstPort 1 + } + Line { + SrcBlock "In2" + SrcPort 1 + Points [15, 0] + Branch { + Points [0, -105] + DstBlock "Bitwise\nOperator1" + DstPort 1 + } + Branch { + Points [0, 80] + Branch { + Points [0, 150] + Branch { + Points [0, 155] + Branch { + Points [0, 175] + Branch { + Points [0, 180; 5, 0] + Branch { + Points [-5, 0; 0, 175] + Branch { + Points [0, 185] + Branch { + Points [0, 190] + Branch { + Points [0, 195] + Branch { + Points [0, 215] + Branch { + Points [0, 230] + Branch { + Points [0, 240] + Branch { + Points [0, 260] + Branch { + Points [0, 265] + Branch { + Points [0, 275] + Branch { + Points [0, 280] + Branch { + Points [0, 285] + Branch { + Points [0, 300] + Branch { + Points [0, 305] + Branch { + Points [0, 310] + Branch { + Points [0, 315] + Branch { + Points [0, 320] + Branch { + Points [0, 325] + DstBlock "Bitwise\nOperator28" + DstPort 1 + } + Branch { + DstBlock "Bitwise\nOperator27" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator26" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator25" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator24" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator23" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator22" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator21" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator20" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator19" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator18" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator17" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator16" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator15" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator14" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator13" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator12" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator11" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator10" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator9" + DstPort 1 + } + } + Branch { + Points [0, 5] + DstBlock "Bitwise\nOperator8" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator7" + DstPort 1 + } + } + Branch { + DstBlock "Bitwise\nOperator6" + DstPort 1 + } + } + } + Line { + SrcBlock "In1" + SrcPort 1 + Points [0, -10; 280, 0] + Branch { + Points [0, 170] + DstBlock "Sum1" + DstPort 1 + } + Branch { + Points [0, -20] + DstBlock "Math\nFunction1" + DstPort 2 + } + } + Line { + SrcBlock "Product24" + SrcPort 1 + Points [135, 0] + DstBlock "Sum27" + DstPort 1 + } + Line { + SrcBlock "Product23" + SrcPort 1 + Points [135, 0] + DstBlock "Sum27" + DstPort 2 + } + Line { + SrcBlock "Product22" + SrcPort 1 + Points [35, 0; 0, -1655] + DstBlock "Sum27" + DstPort 23 + } + Line { + SrcBlock "Product21" + SrcPort 1 + Points [40, 0; 0, -1350] + DstBlock "Sum27" + DstPort 22 + } + Line { + SrcBlock "Product20" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 21 + } + Line { + SrcBlock "Product19" + SrcPort 1 + Points [40, 0; 0, -755] + DstBlock "Sum27" + DstPort 20 + } + Line { + SrcBlock "Product18" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 19 + } + Line { + SrcBlock "Product17" + SrcPort 1 + Points [40, 0; 0, -190] + DstBlock "Sum27" + DstPort 18 + } + Line { + SrcBlock "Product16" + SrcPort 1 + Points [40, 0; 0, 80] + DstBlock "Sum27" + DstPort 17 + } + Line { + SrcBlock "Product15" + SrcPort 1 + Points [40, 0; 0, 345] + DstBlock "Sum27" + DstPort 16 + } + Line { + SrcBlock "Product14" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 15 + } + Line { + SrcBlock "Product13" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 14 + } + Line { + SrcBlock "Product12" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 13 + } + Line { + SrcBlock "Product11" + SrcPort 1 + Points [140, 0] + DstBlock "Sum27" + DstPort 12 + } + Line { + SrcBlock "Product10" + SrcPort 1 + Points [40, 0; 0, 1500] + DstBlock "Sum27" + DstPort 11 + } + Line { + SrcBlock "Product9" + SrcPort 1 + Points [40, 0; 0, 1690] + DstBlock "Sum27" + DstPort 10 + } + Line { + SrcBlock "Product8" + SrcPort 1 + Points [40, 0; 0, 1870] + DstBlock "Sum27" + DstPort 9 + } + Line { + SrcBlock "Product7" + SrcPort 1 + Points [95, 0] + Branch { + Points [0, -45] + DstBlock "Display6" + DstPort 1 + } + Branch { + Points [45, 0] + DstBlock "Sum27" + DstPort 8 + } + } + Line { + SrcBlock "Product6" + SrcPort 1 + Points [40, 0; 0, 5] + Branch { + DstBlock "Display4" + DstPort 1 + } + Branch { + Points [0, 2205] + DstBlock "Sum27" + DstPort 7 + } + } + Line { + SrcBlock "Product5" + SrcPort 1 + Points [15, 0] + Branch { + Points [0, -15] + DstBlock "Display3" + DstPort 1 + } + Branch { + Points [0, 2380] + DstBlock "Sum27" + DstPort 6 + } + } + Line { + SrcBlock "Product4" + SrcPort 1 + Points [105, 0] + Branch { + Points [0, -45] + DstBlock "Display2" + DstPort 1 + } + Branch { + Points [40, 0] + DstBlock "Sum27" + DstPort 5 + } + } + Line { + SrcBlock "Product3" + SrcPort 1 + Points [105, 0] + Branch { + Points [0, -35] + DstBlock "Display1" + DstPort 1 + } + Branch { + Points [45, 0] + DstBlock "Sum27" + DstPort 4 + } + } + Line { + SrcBlock "Product2" + SrcPort 1 + Points [40, 0] + Branch { + Points [0, -60] + DstBlock "Display5" + DstPort 1 + } + Branch { + Points [0, 2830] + DstBlock "Sum27" + DstPort 3 + } + } + Line { + SrcBlock "Sum26" + SrcPort 1 + Points [5, 0; 0, -5] + DstBlock "Math\nFunction24" + DstPort 2 + } + Line { + SrcBlock "Constant53" + SrcPort 1 + DstBlock "Sum26" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction24" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product24" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero24" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product24" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator28" + SrcPort 1 + DstBlock "Compare\nTo Zero24" + DstPort 1 + } + Line { + SrcBlock "Constant52" + SrcPort 1 + Points [5, 0; 0, 25] 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SrcPort 1 + DstBlock "Sum24" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction22" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product22" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero22" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product22" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator26" + SrcPort 1 + DstBlock "Compare\nTo Zero22" + DstPort 1 + } + Line { + SrcBlock "Constant48" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction22" + DstPort 1 + } + Line { + SrcBlock "Sum23" + SrcPort 1 + Points [5, 0; 0, -5] + Branch { + Points [-40, 0] + DstBlock "Sum24" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction21" + DstPort 2 + } + } + Line { + SrcBlock "Constant47" + SrcPort 1 + DstBlock "Sum23" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction21" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product21" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero21" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product21" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator25" + SrcPort 1 + DstBlock "Compare\nTo Zero21" + DstPort 1 + } + Line { + SrcBlock "Constant46" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction21" + DstPort 1 + } + Line { + SrcBlock "Sum22" + SrcPort 1 + Points [5, 0; 0, -5] + Branch { + Points [-45, 0] + DstBlock "Sum23" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction20" + DstPort 2 + } + } + Line { + SrcBlock "Constant45" + SrcPort 1 + DstBlock "Sum22" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction20" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product20" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero20" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product20" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator24" + SrcPort 1 + DstBlock "Compare\nTo Zero20" + DstPort 1 + } + Line { + SrcBlock "Constant44" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction20" + DstPort 1 + } + Line { + SrcBlock "Sum21" + SrcPort 1 + Points [5, 0; 0, -5] + Branch { + Points [-45, 0] + DstBlock "Sum22" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction19" + DstPort 2 + } + } + Line { + SrcBlock "Constant43" + SrcPort 1 + DstBlock "Sum21" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction19" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product19" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero19" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product19" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator23" + SrcPort 1 + DstBlock "Compare\nTo Zero19" + DstPort 1 + } + Line { + SrcBlock "Constant42" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction19" + DstPort 1 + } + Line { + SrcBlock "Sum20" + SrcPort 1 + Points [5, 0; 0, -5; 5, 0] + Branch { + Points [-50, 0] + DstBlock "Sum21" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction18" + DstPort 2 + } + } + Line { + SrcBlock "Constant41" + SrcPort 1 + DstBlock "Sum20" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction18" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product18" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero18" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product18" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator22" + SrcPort 1 + DstBlock "Compare\nTo Zero18" + DstPort 1 + } + Line { + SrcBlock "Constant40" + SrcPort 1 + Points [5, 0; 0, 25] + DstBlock "Math\nFunction18" + DstPort 1 + } + Line { + SrcBlock "Sum19" + SrcPort 1 + Points [5, 0; 0, -5; 5, 0] + Branch { + Points [-50, 0] + DstBlock "Sum20" + DstPort 1 + } + Branch { + DstBlock "Math\nFunction17" + DstPort 2 + } + } + Line { + SrcBlock "Constant39" + SrcPort 1 + DstBlock "Sum19" + DstPort 2 + } + Line { + SrcBlock "Math\nFunction17" + SrcPort 1 + Points [40, 0; 0, 15] + DstBlock "Product17" + DstPort 1 + } + Line { + SrcBlock "Compare\nTo Zero17" + SrcPort 1 + Points [10, 0; 0, -35] + DstBlock "Product17" + DstPort 2 + } + Line { + SrcBlock "Bitwise\nOperator21" + SrcPort 1 + DstBlock "Compare\nTo Zero17" + DstPort 1 + } + Line { + SrcBlock "Constant38" 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+ Name "d_P_I" + SID "4274" + Position [690, 1593, 720, 1607] + Port "10" + IconDisplay "Port number" + } + Block { + BlockType Outport + Name "d_P_Q" + SID "4275" + Position [690, 1753, 720, 1767] + Port "11" + IconDisplay "Port number" + } + Block { + BlockType Outport + Name "d_acq_carrier_doppler_Hz" + SID "4276" + Position [690, 1913, 720, 1927] + Port "12" + IconDisplay "Port number" + } + Block { + BlockType Outport + Name "enable_tracking" + SID "4277" + Position [690, 2073, 720, 2087] + Port "13" + IconDisplay "Port number" + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 52 + Points [150, 0] + DstBlock "Subsystem7" + DstPort 4 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 51 + Points [150, 0] + DstBlock "Subsystem7" + DstPort 3 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 50 + Points [150, 0] + DstBlock "Subsystem7" + DstPort 2 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 49 + Points [150, 0] + DstBlock "Subsystem7" + DstPort 1 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 48 + Points [150, 0] + DstBlock "Subsystem6" + DstPort 4 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 47 + Points [150, 0] + DstBlock "Subsystem6" + DstPort 3 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 46 + Points [150, 0] + DstBlock "Subsystem6" + DstPort 2 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 45 + Points [150, 0] + DstBlock "Subsystem6" + DstPort 1 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 44 + Points [150, 0] + DstBlock "Subsystem5" + DstPort 4 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 43 + Points [150, 0] + DstBlock "Subsystem5" + DstPort 3 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 42 + Points [150, 0] + DstBlock "Subsystem5" + DstPort 2 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 41 + Points [150, 0] + DstBlock "Subsystem5" + DstPort 1 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 40 + Points [150, 0] + DstBlock "Subsystem4" + DstPort 4 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 39 + Points [150, 0] + DstBlock "Subsystem4" + DstPort 3 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 38 + Points [150, 0] + DstBlock "Subsystem4" + DstPort 2 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 37 + Points [150, 0] + DstBlock "Subsystem4" + DstPort 1 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 36 + Points [150, 0] + DstBlock "Subsystem12" + DstPort 4 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 35 + Points [150, 0] + DstBlock "Subsystem12" + DstPort 3 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 34 + Points [150, 0] + DstBlock "Subsystem12" + DstPort 2 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 33 + Points [150, 0] + DstBlock "Subsystem12" + DstPort 1 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 32 + Points [150, 0] + DstBlock "Subsystem11" + DstPort 4 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 31 + Points [150, 0] + DstBlock "Subsystem11" + DstPort 3 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 30 + Points [150, 0] + DstBlock "Subsystem11" + DstPort 2 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 29 + Points [150, 0] + DstBlock "Subsystem11" + DstPort 1 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 28 + DstBlock "Subsystem3" + DstPort 4 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 27 + DstBlock "Subsystem3" + DstPort 3 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 26 + DstBlock "Subsystem3" + DstPort 2 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 25 + DstBlock "Subsystem3" + DstPort 1 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 24 + DstBlock "Subsystem2" + DstPort 4 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 23 + DstBlock "Subsystem2" + DstPort 3 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 22 + DstBlock "Subsystem2" + DstPort 2 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 21 + DstBlock "Subsystem2" + DstPort 1 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 20 + Points [150, 0] + DstBlock "Subsystem1" + DstPort 4 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 19 + Points [150, 0] + DstBlock "Subsystem1" + DstPort 3 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 18 + Points [150, 0] + DstBlock "Subsystem1" + DstPort 2 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 17 + Points [150, 0] + DstBlock "Subsystem1" + DstPort 1 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 16 + Points [150, 0] + DstBlock "Subsystem" + DstPort 4 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 15 + Points [150, 0] + DstBlock "Subsystem" + DstPort 3 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 14 + Points [150, 0] + DstBlock "Subsystem" + DstPort 2 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 13 + Points [0, -10] + DstBlock "Subsystem" + DstPort 1 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 12 + Points [0, -15] + DstBlock "Subsystem10" + DstPort 4 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 11 + Points [150, 0] + DstBlock "Subsystem10" + DstPort 3 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 10 + Points [0, -15] + DstBlock "Subsystem10" + DstPort 2 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 9 + Points [0, -15] + DstBlock "Subsystem10" + DstPort 1 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 8 + Points [0, -15] + DstBlock "Subsystem9" + DstPort 4 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 7 + Points [0, -15] + DstBlock "Subsystem9" + DstPort 3 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 6 + Points [0, -15] + DstBlock "Subsystem9" + DstPort 2 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 5 + Points [0, -15] + DstBlock "Subsystem9" + DstPort 1 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 4 + Points [0, -15] + DstBlock "Subsystem8" + DstPort 4 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 3 + Points [0, -15] + DstBlock "Subsystem8" + DstPort 3 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 2 + Points [0, -15] + DstBlock "Subsystem8" + DstPort 2 + } + Line { + SrcBlock "Multiport\nSelector" + SrcPort 1 + Points [0, -15] + DstBlock "Subsystem8" + DstPort 1 + } + Line { + SrcBlock "Subsystem11" + SrcPort 1 + DstBlock "d_vL_I" + DstPort 1 + } + Line { + SrcBlock "Subsystem12" + SrcPort 1 + DstBlock "d_vL_Q" + DstPort 1 + } + Line { + SrcBlock "Subsystem9" + SrcPort 1 + DstBlock "d_vE_I" + DstPort 1 + } + Line { + SrcBlock "Subsystem10" + SrcPort 1 + DstBlock "d_vE_Q" + DstPort 1 + } + Line { + SrcBlock "Subsystem7" + SrcPort 1 + DstBlock "enable_tracking" + DstPort 1 + } + Line { + SrcBlock "Subsystem6" + SrcPort 1 + DstBlock "d_acq_carrier_doppler_Hz" + DstPort 1 + } + Line { + SrcBlock "Subsystem5" + SrcPort 1 + DstBlock "d_P_Q" + DstPort 1 + } + Line { + SrcBlock "Subsystem8" + SrcPort 1 + DstBlock "control_id" + DstPort 1 + } + Line { + SrcBlock "Subsystem" + SrcPort 1 + DstBlock "d_E_I" + DstPort 1 + } + Line { + SrcBlock "Subsystem1" + SrcPort 1 + DstBlock "d_E_Q" + DstPort 1 + } + Line { + SrcBlock "Subsystem2" + SrcPort 1 + DstBlock "d_L_I" + DstPort 1 + } + Line { + SrcBlock "Subsystem3" + SrcPort 1 + DstBlock "d_L_Q" + DstPort 1 + } + Line { + SrcBlock "Subsystem4" + SrcPort 1 + DstBlock "d_P_I" + DstPort 1 + } + Line { + SrcBlock "RX" + SrcPort 1 + Points [0, 5] + DstBlock "Multiport\nSelector" + DstPort 1 + } + Annotation { + Position [285, 79] + } + } + } + Block { + BlockType SubSystem + Name "gnss_sdr_galileo_e1_tcp_connector_tracking_tx" + SID "2090" + Ports [4] + Position [495, 20, 710, 315] + ShowPortLabels "SignalName" + MinAlgLoopOccurrences off + PropExecContextOutsideSubsystem off + RTWSystemCode "Auto" + FunctionWithSeparateData off + Opaque off + RequestExecContextInheritance off + MaskHideContents off + System { + Name "gnss_sdr_galileo_e1_tcp_connector_tracking_tx" + Location [1137, 408, 1445, 698] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "100" + Block { + BlockType Inport + Name "control_id" + SID "2091" + Position [30, 38, 60, 52] + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "code_nco" + SID "2092" + Position [30, 98, 60, 112] + Port "2" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "carr_nco" + SID "2093" + Position [30, 158, 60, 172] + Port "3" + IconDisplay "Port number" + } + Block { + BlockType Inport + Name "carrier_doppler_Hz" + SID "2094" + Position [30, 218, 60, 232] + Port "4" + IconDisplay "Port number" + } + Block { + BlockType Reference + Name "TX" + SID "2096" + Ports [1] + Position [140, 77, 275, 193] + LibraryVersion "1.84" + DialogController "instrumentcreatedialog" + DialogControllerArgs "DataTag5" + SourceBlock "instrumentlib/TCP//IP Send" + SourceType "TCP/IP Send" + Host "84.88.61.86" + Port "2070" + EnableBlockingMode on + Timeout "5" + ByteOrder "LittleEndian" + } + Block { + BlockType Concatenate + Name "Vector\nConcatenate1" + SID "2097" + Ports [4, 1] + Position [95, 12, 100, 258] + BackgroundColor "black" + ShowName off + NumInputs "4" + Mode "Vector" + } + Line { + SrcBlock "carrier_doppler_Hz" + SrcPort 1 + DstBlock "Vector\nConcatenate1" + DstPort 4 + } + Line { + SrcBlock "Vector\nConcatenate1" + SrcPort 1 + DstBlock "TX" + DstPort 1 + } + Line { + SrcBlock "control_id" + SrcPort 1 + DstBlock "Vector\nConcatenate1" + DstPort 1 + } + Line { + SrcBlock "code_nco" + SrcPort 1 + DstBlock "Vector\nConcatenate1" + DstPort 2 + } + Line { + SrcBlock "carr_nco" + SrcPort 1 + DstBlock "Vector\nConcatenate1" + DstPort 3 + } + } + } + } + } + } +} +MatData { + NumRecords 6 + DataRecord { + Tag DataTag5 + Data " %)30 . : 8 ( 0 % \" $ ! 0 . . 8 ( ! " + " % \" $ ' 0 0 !P '1C<&EP. +% * +% * ---------------------------------------------------------------------- +% */ + +function gnss_sdr_galileo_e1_tcp_connector_tracking_start(num_channels) + + %User parameters + host = '84.88.61.86'; %Remote IP address (GNSS-SDR computer IP) + port = 2070; %Remote port (GNSS-SDR computer port for Ch0) + num_vars_rx = 13; %Number of variables expected from GNSS-SDR + num_vars_tx = 4; %Number of variable to be transmitted to GNSS-SDR + timeout = '10'; %Timeout [s] + + %name of the tracking block, it must match the name of the Simulink + %model + tracking_block_name = 'gnss_sdr_galileo_e1_tcp_connector_tracking'; + + % Layout coordinates for the first gnss_sdr_galileo_e1_tcp_connector_tracking + % block and offset definitions + X0 = 20; + X1 = 170; + Y0 = 20; + Y1 = 140; + X_offset = 200; + Y_offset = 160; + + %Calculate the size of the data received from GNSS-SDR + %(float = 4 bytes each variable) + datasize_RX = num_vars_rx*4; + + %Create a Simulink model + simulink('open'); + new_system('gnss_sdr_galileo_e1_tcp_connector_tracking_aux'); + open_system('gnss_sdr_galileo_e1_tcp_connector_tracking_aux'); + + %Set parameters to avoid warnings in the Command Window + set_param('gnss_sdr_galileo_e1_tcp_connector_tracking_aux',... + 'InheritedTsInSrcMsg', 'none'); + warning('off', 'Simulink:Commands:SetParamLinkChangeWarn'); + + %Assign values to the variables used by Simulink in the base workspace + %DLL + assignin('base', 'B_DLL', 2); + assignin('base', 'zeta_DLL', 0.7); + assignin('base', 'k_DLL', 1); + assignin('base', 'd_pdi_code', 0.004); + + %PLL + assignin('base', 'B_PLL', 30); + assignin('base', 'zeta_PLL', 0.65); + assignin('base', 'k_PLL', 0.25); + assignin('base', 'd_pdi_carr', 0.004); + + %Block generation from the Simulink Library + for i = 0:num_channels-1; + + %Add and prepare an empty block to become the TCP connector block + tcp_connector_block=['gnss_sdr_galileo_e1_tcp_connector_tracking_aux/gnss_sdr_galileo_e1_tcp_connector_tracking_', num2str(i)]; + + add_block('simulink/Ports & Subsystems/Subsystem', tcp_connector_block); + delete_line(tcp_connector_block,'In1/1', 'Out1/1') + + tcp_connector_tracking_i_In1 = ['gnss_sdr_galileo_e1_tcp_connector_tracking_aux/gnss_sdr_galileo_e1_tcp_connector_tracking_',num2str(i),'/In1']; + tcp_connector_tracking_i_Out1 = ['gnss_sdr_galileo_e1_tcp_connector_tracking_aux/gnss_sdr_galileo_e1_tcp_connector_tracking_',num2str(i),'/Out1']; + + delete_block(tcp_connector_tracking_i_In1); + delete_block(tcp_connector_tracking_i_Out1); + + %Add to the TCP connector block the receiver, the tracking and the + %transmitter blocks + tcp_connector_tracking_rx_block = ['gnss_sdr_galileo_e1_tcp_connector_tracking_aux/gnss_sdr_galileo_e1_tcp_connector_tracking_',num2str(i),'/gnss_sdr_galileo_e1_tcp_connector_tracking_rx']; + tcp_connector_tracking_block = ['gnss_sdr_galileo_e1_tcp_connector_tracking_aux/gnss_sdr_galileo_e1_tcp_connector_tracking_',num2str(i),'/',tracking_block_name]; + tcp_connector_tracking_tx_block = ['gnss_sdr_galileo_e1_tcp_connector_tracking_aux/gnss_sdr_galileo_e1_tcp_connector_tracking_',num2str(i),'/gnss_sdr_galileo_e1_tcp_connector_tracking_tx']; + + add_block('simulink/User-Defined Functions/gnss_sdr/gnss_sdr_galileo_e1_tcp_connector_tracking_rx',tcp_connector_tracking_rx_block); + + path_to_tracking_block = ['simulink/User-Defined Functions/gnss_sdr/', tracking_block_name]; + add_block(path_to_tracking_block, tcp_connector_tracking_block); + + add_block('simulink/User-Defined Functions/gnss_sdr/gnss_sdr_galileo_e1_tcp_connector_tracking_tx',tcp_connector_tracking_tx_block); + + %Connect the receiver block to the tracking block + for j=1:num_vars_rx; + rx_out_ports =['gnss_sdr_galileo_e1_tcp_connector_tracking_rx/',num2str(j)]; + tracking_in_ports =[tracking_block_name,'/',num2str(j)]; + + add_line(tcp_connector_block, rx_out_ports, tracking_in_ports) + end + + %Connect the tracking block to the transmitter block + for k=1:num_vars_tx; + tracking_out_ports =[tracking_block_name,'/',num2str(k)]; + tx_in_ports =['gnss_sdr_galileo_e1_tcp_connector_tracking_tx/',num2str(k)]; + + add_line(tcp_connector_block, tracking_out_ports, tx_in_ports) + end + + %Add, place and connect two scopes in the TCP connector block + name_scope_1 = [tcp_connector_block,'/Scope']; + add_block('simulink/Sinks/Scope', name_scope_1, 'Position', [600 425 650 475]); + set_param(name_scope_1, 'NumInputPorts', '5', 'LimitDataPoints', 'off'); + add_line(tcp_connector_block, 'gnss_sdr_galileo_e1_tcp_connector_tracking_rx/10', 'Scope/1', 'autorouting','on') + add_line(tcp_connector_block, 'gnss_sdr_galileo_e1_tcp_connector_tracking_rx/11', 'Scope/2', 'autorouting','on') + tracking_scope_port3 = [tracking_block_name,'/2']; + add_line(tcp_connector_block, tracking_scope_port3, 'Scope/3', 'autorouting','on') + tracking_scope_port4 = [tracking_block_name,'/3']; + add_line(tcp_connector_block, tracking_scope_port4, 'Scope/4', 'autorouting','on') + tracking_scope_port5 = [tracking_block_name,'/4']; + add_line(tcp_connector_block, tracking_scope_port5, 'Scope/5', 'autorouting','on') + + name_scope_2 = [tcp_connector_block,'/EPL']; + add_block('simulink/Sinks/Scope', name_scope_2, 'Position', [475 500 525 550]); + set_param(name_scope_2, 'LimitDataPoints', 'off'); + tracking_scope2_port5 = [tracking_block_name,'/5']; + add_line(tcp_connector_block, tracking_scope2_port5, 'EPL/1', 'autorouting','on') + + %Set the TCP receiver parameters + tcp_receiver = ['gnss_sdr_galileo_e1_tcp_connector_tracking_aux/gnss_sdr_galileo_e1_tcp_connector_tracking_',num2str(i),'/gnss_sdr_galileo_e1_tcp_connector_tracking_rx/RX']; + set_param(tcp_receiver, 'Port', num2str(port+i), 'Host', host, 'DataSize', num2str(datasize_RX), 'Timeout', timeout); + + %Set the TCP transmitter parameters + tcp_transmitter = ['gnss_sdr_galileo_e1_tcp_connector_tracking_aux/gnss_sdr_galileo_e1_tcp_connector_tracking_',num2str(i),'/gnss_sdr_galileo_e1_tcp_connector_tracking_tx/TX']; + set_param(tcp_transmitter, 'Port', num2str(port+i), 'Host', host,'Timeout', timeout); + + %New layout coordinates for each block + X2 = X0 + floor(i/4)*X_offset; + X3 = X1 + floor(i/4)*X_offset; + Y2 = Y0 + (i-4*floor(i/4))*Y_offset; + Y3 = Y1 + (i-4*floor(i/4))*Y_offset; + + %Place the block in the layout + set_param(tcp_connector_block, 'Position', [X2 Y2 X3 Y3]); + end + + %Set parameters to configure the model Solver + set_param('gnss_sdr_galileo_e1_tcp_connector_tracking_aux',... + 'SolverType', 'Fixed-step', 'Solver', 'FixedStepDiscrete',... + 'FixedStep', 'auto', 'StopTime', 'inf'); + + %Save the model with a definitive name + save_system('gnss_sdr_galileo_e1_tcp_connector_tracking_aux', 'gnss_sdr_galileo_e1_tcp_connector_tracking_ready'); + simulink('close'); + + %Run the Simulink model + set_param('gnss_sdr_galileo_e1_tcp_connector_tracking_ready','simulationcommand','start'); + +end