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Merge branch 'next' of https://github.com/carlesfernandez/gnss-sdr into next

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This commit is contained in:
Carles Fernandez 2019-08-19 13:14:26 +02:00
commit bf8ad2d37b
31 changed files with 469 additions and 1563 deletions
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2
src/algorithms/libs/rtklib/rtklib_rtkpos.cc
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@ -2340,7 +2340,7 @@ int valpos(rtk_t *rtk, const double *v, const double *R, const int *vflg,
type = (vflg[i] >> 4) & 0xF; type = (vflg[i] >> 4) & 0xF;
freq = vflg[i] & 0xF; freq = vflg[i] & 0xF;
stype = type == 0 ? 'L' : (type == 1 ? 'L' : 'C'); stype = type == 0 ? 'L' : (type == 1 ? 'L' : 'C');
errmsg(rtk, "large residual (sat=%2d-%2d %s%d v=%6.3f sig=%.3f)\n", errmsg(rtk, "large residual (sat=%2d-%2d %c%d v=%6.3f sig=%.3f)\n",
sat1, sat2, stype, freq + 1, v[i], std::sqrt(R[i + i * nv])); sat1, sat2, stype, freq + 1, v[i], std::sqrt(R[i + i * nv]));
} }
#if 0 /* omitted v.2.4.0 */ #if 0 /* omitted v.2.4.0 */

19
src/algorithms/libs/rtklib/rtklib_stream.cc
View File

@ -58,6 +58,7 @@
#include <cerrno> #include <cerrno>
#include <cstring> #include <cstring>
#include <fcntl.h> #include <fcntl.h>
#include <inttypes.h>
#include <netdb.h> #include <netdb.h>
#include <netinet/tcp.h> #include <netinet/tcp.h>
#include <string> #include <string>
@ -461,7 +462,7 @@ void closefile(file_t *file)
{ {
return; return;
} }
tracet(3, "closefile: fp=%d\n", file->fp); tracet(3, "closefile: fpos=%" PRIdPTR "\n", file->fp);
closefile_(file); closefile_(file);
free(file); free(file);
} }
@ -472,7 +473,7 @@ void swapfile(file_t *file, gtime_t time, char *msg)
{ {
char openpath[MAXSTRPATH]; char openpath[MAXSTRPATH];
tracet(3, "swapfile: fp=%d time=%s\n", file->fp, time_str(time, 0)); tracet(3, "swapfile: fpos=%" PRIdPTR "\n time=%s\n", file->fp, time_str(time, 0));
/* return if old swap file open */ /* return if old swap file open */
if (file->fp_tmp || file->fp_tag_tmp) if (file->fp_tmp || file->fp_tag_tmp)
@ -500,7 +501,7 @@ void swapfile(file_t *file, gtime_t time, char *msg)
/* close old swap file -------------------------------------------------------*/ /* close old swap file -------------------------------------------------------*/
void swapclose(file_t *file) void swapclose(file_t *file)
{ {
tracet(3, "swapclose: fp_tmp=%d\n", file->fp_tmp); tracet(3, "swapclose: fp_tmp=%" PRIdPTR "\n", file->fp_tmp);
if (file->fp_tmp) if (file->fp_tmp)
{ {
fclose(file->fp_tmp); fclose(file->fp_tmp);
@ -534,7 +535,7 @@ int readfile(file_t *file, unsigned char *buff, int nmax, char *msg)
{ {
return 0; return 0;
} }
tracet(4, "readfile: fp=%d nmax=%d\n", file->fp, nmax); tracet(4, "readfile: fp=%zd nmax=%d\n", file->fp, nmax);
if (file->fp == stdin) if (file->fp == stdin)
{ {
@ -617,7 +618,7 @@ int readfile(file_t *file, unsigned char *buff, int nmax, char *msg)
sprintf(msg, "end"); sprintf(msg, "end");
} }
} }
tracet(5, "readfile: fp=%d nr=%d fpos=%d\n", file->fp, nr, file->fpos); tracet(5, "readfile: fpos=%" PRIdPTR "\n nr=%d fpos=%zd\n", file->fp, nr, file->fpos);
return nr; return nr;
} }
@ -640,7 +641,7 @@ int writefile(file_t *file, unsigned char *buff, int n, char *msg)
{ {
return 0; return 0;
} }
tracet(3, "writefile: fp=%d n=%d\n", file->fp, n); tracet(3, "writefile: fpos=%" PRIdPTR "\n n=%d\n", file->fp, n);
wtime = utc2gpst(timeget()); /* write time in gpst */ wtime = utc2gpst(timeget()); /* write time in gpst */
@ -693,7 +694,7 @@ int writefile(file_t *file, unsigned char *buff, int n, char *msg)
fflush(file->fp_tag_tmp); fflush(file->fp_tag_tmp);
} }
} }
tracet(5, "writefile: fp=%d ns=%d tick=%5d fpos=%d\n", file->fp, ns, tick, fpos); tracet(5, "writefile: fpos=%" PRIdPTR "\n ns=%d tick=%5d fpos=%zd\n", file->fp, ns, tick, fpos);
return static_cast<int>(ns); return static_cast<int>(ns);
} }
@ -1497,7 +1498,7 @@ int reqntrip_s(ntrip_t *ntrip, char *msg)
return 0; return 0;
} }
tracet(2, "reqntrip_s: send request state=%d ns=%d\n", ntrip->state, p - buff); tracet(2, "reqntrip_s: send request state=%d ns=%" PRIdPTR "\n", ntrip->state, p - buff);
tracet(5, "reqntrip_s: n=%d buff=\n%s\n", p - buff, buff); tracet(5, "reqntrip_s: n=%d buff=\n%s\n", p - buff, buff);
ntrip->state = 1; ntrip->state = 1;
return 1; return 1;
@ -1535,7 +1536,7 @@ int reqntrip_c(ntrip_t *ntrip, char *msg)
return 0; return 0;
} }
tracet(2, "reqntrip_c: send request state=%d ns=%d\n", ntrip->state, p - buff); tracet(2, "reqntrip_c: send request state=%d ns=%" PRIdPTR "\n", ntrip->state, p - buff);
tracet(5, "reqntrip_c: n=%d buff=\n%s\n", p - buff, buff); tracet(5, "reqntrip_c: n=%d buff=\n%s\n", p - buff, buff);
ntrip->state = 1; ntrip->state = 1;
return 1; return 1;

24
src/algorithms/libs/volk_gnsssdr_module/volk_gnsssdr/include/volk_gnsssdr/volk_gnsssdr_common.h
View File

@ -24,9 +24,9 @@
#ifndef INCLUDED_LIBVOLK_GNSSSDR_COMMON_H #ifndef INCLUDED_LIBVOLK_GNSSSDR_COMMON_H
#define INCLUDED_LIBVOLK_GNSSSDR_COMMON_H #define INCLUDED_LIBVOLK_GNSSSDR_COMMON_H
//////////////////////////////////////////////////////////////////////// //
// Cross-platform attribute macros not included in VOLK // Cross-platform attribute macros not included in VOLK
//////////////////////////////////////////////////////////////////////// //
#if defined __GNUC__ #if defined __GNUC__
#define __VOLK_GNSSSDR_PREFETCH(addr) __builtin_prefetch(addr) #define __VOLK_GNSSSDR_PREFETCH(addr) __builtin_prefetch(addr)
#define __VOLK_GNSSSDR_PREFETCH_LOCALITY(addr, rw, locality) __builtin_prefetch(addr, rw, locality) #define __VOLK_GNSSSDR_PREFETCH_LOCALITY(addr, rw, locality) __builtin_prefetch(addr, rw, locality)
@ -41,9 +41,9 @@
#ifndef INCLUDED_LIBVOLK_COMMON_H #ifndef INCLUDED_LIBVOLK_COMMON_H
#define INCLUDED_LIBVOLK_COMMON_H #define INCLUDED_LIBVOLK_COMMON_H
//////////////////////////////////////////////////////////////////////// //
// Cross-platform attribute macros // Cross-platform attribute macros
//////////////////////////////////////////////////////////////////////// //
#if defined __GNUC__ #if defined __GNUC__
#define __VOLK_ATTR_ALIGNED(x) __attribute__((aligned(x))) #define __VOLK_ATTR_ALIGNED(x) __attribute__((aligned(x)))
#define __VOLK_ATTR_UNUSED __attribute__((unused)) #define __VOLK_ATTR_UNUSED __attribute__((unused))
@ -78,18 +78,18 @@
#define __VOLK_VOLATILE __volatile__ #define __VOLK_VOLATILE __volatile__
#endif #endif
//////////////////////////////////////////////////////////////////////// //
// Ignore annoying warnings in MSVC // Ignore annoying warnings in MSVC
//////////////////////////////////////////////////////////////////////// //
#if defined(_MSC_VER) #if defined(_MSC_VER)
#pragma warning(disable : 4244) // 'conversion' conversion from 'type1' to 'type2', possible loss of data #pragma warning(disable : 4244) // 'conversion' conversion from 'type1' to 'type2', possible loss of data
#pragma warning(disable : 4305) // 'identifier' : truncation from 'type1' to 'type2' #pragma warning(disable : 4305) // 'identifier' : truncation from 'type1' to 'type2'
#endif #endif
//////////////////////////////////////////////////////////////////////// //
// C-linkage declaration macros // C-linkage declaration macros
// FIXME: due to the usage of complex.h, require gcc for c-linkage // FIXME: due to the usage of complex.h, require gcc for c-linkage
//////////////////////////////////////////////////////////////////////// //
#if defined(__cplusplus) && (__GNUC__) #if defined(__cplusplus) && (__GNUC__)
#define __VOLK_DECL_BEGIN \ #define __VOLK_DECL_BEGIN \
extern "C" \ extern "C" \
@ -100,19 +100,19 @@
#define __VOLK_DECL_END #define __VOLK_DECL_END
#endif #endif
//////////////////////////////////////////////////////////////////////// //
// Define VOLK_API for library symbols // Define VOLK_API for library symbols
// http://gcc.gnu.org/wiki/Visibility // http://gcc.gnu.org/wiki/Visibility
//////////////////////////////////////////////////////////////////////// //
#ifdef volk_gnsssdr_EXPORTS #ifdef volk_gnsssdr_EXPORTS
#define VOLK_API __VOLK_ATTR_EXPORT #define VOLK_API __VOLK_ATTR_EXPORT
#else #else
#define VOLK_API __VOLK_ATTR_IMPORT #define VOLK_API __VOLK_ATTR_IMPORT
#endif #endif
//////////////////////////////////////////////////////////////////////// //
// The bit128 union used by some // The bit128 union used by some
//////////////////////////////////////////////////////////////////////// //
#include <inttypes.h> #include <inttypes.h>
#ifdef LV_HAVE_SSE #ifdef LV_HAVE_SSE

804
src/algorithms/libs/volk_gnsssdr_module/volk_gnsssdr/kernels/volk_gnsssdr/volk_gnsssdr_16ic_16i_rotator_dot_prod_16ic_xn.h
View File

@ -334,254 +334,6 @@ static inline void volk_gnsssdr_16ic_16i_rotator_dot_prod_16ic_xn_a_sse3(lv_16sc
#endif /* LV_HAVE_SSE3 */ #endif /* LV_HAVE_SSE3 */
//#ifdef LV_HAVE_SSE3
//#include <pmmintrin.h>
//static inline void volk_gnsssdr_16ic_16i_rotator_dot_prod_16ic_xn_a_sse3_reload(lv_16sc_t* result, const lv_16sc_t* in_common, const lv_32fc_t phase_inc, lv_32fc_t* phase, const int16_t** in_a, int num_a_vectors, unsigned int num_points)
//{
//lv_16sc_t dotProduct = lv_cmake(0,0);
//const unsigned int sse_iters = num_points / 4;
//const unsigned int ROTATOR_RELOAD = 128;
//int n_vec;
//int i;
//unsigned int number;
//unsigned int j;
//unsigned int n;
//const int16_t** _in_a = in_a;
//const lv_16sc_t* _in_common = in_common;
//lv_16sc_t* _out = result;
//__VOLK_ATTR_ALIGNED(16) lv_16sc_t dotProductVector[4];
//__m128i* realcacc = (__m128i*)volk_gnsssdr_malloc(num_a_vectors * sizeof(__m128i), volk_gnsssdr_get_alignment());
//__m128i* imagcacc = (__m128i*)volk_gnsssdr_malloc(num_a_vectors * sizeof(__m128i), volk_gnsssdr_get_alignment());
//for (n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//realcacc[n_vec] = _mm_setzero_si128();
//imagcacc[n_vec] = _mm_setzero_si128();
//}
//__m128i a, b, c, c_sr, mask_imag, mask_real, real, imag, imag1, imag2, b_sl, a_sl;
//mask_imag = _mm_set_epi8(255, 255, 0, 0, 255, 255, 0, 0, 255, 255, 0, 0, 255, 255, 0, 0);
//mask_real = _mm_set_epi8(0, 0, 255, 255, 0, 0, 255, 255, 0, 0, 255, 255, 0, 0, 255, 255);
//// phase rotation registers
//__m128 pa, pb, two_phase_acc_reg, two_phase_inc_reg;
//__m128i pc1, pc2;
//__VOLK_ATTR_ALIGNED(16) lv_32fc_t two_phase_inc[2];
//two_phase_inc[0] = phase_inc * phase_inc;
//two_phase_inc[1] = phase_inc * phase_inc;
//two_phase_inc_reg = _mm_load_ps((float*) two_phase_inc);
//__VOLK_ATTR_ALIGNED(16) lv_32fc_t two_phase_acc[2];
//two_phase_acc[0] = (*phase);
//two_phase_acc[1] = (*phase) * phase_inc;
//two_phase_acc_reg = _mm_load_ps((float*)two_phase_acc);
//__m128 yl, yh, tmp1, tmp2, tmp3;
//lv_16sc_t tmp16;
//lv_32fc_t tmp32;
//for (number = 0; number < sse_iters / ROTATOR_RELOAD; ++number)
//{
//for (j = 0; j < ROTATOR_RELOAD; j++)
//{
//// Phase rotation on operand in_common starts here:
////printf("generic phase %i: %f,%f\n", n*4,lv_creal(*phase),lv_cimag(*phase));
//pa = _mm_set_ps((float)(lv_cimag(_in_common[1])), (float)(lv_creal(_in_common[1])), (float)(lv_cimag(_in_common[0])), (float)(lv_creal(_in_common[0]))); // //load (2 byte imag, 2 byte real) x 2 into 128 bits reg
////complex 32fc multiplication b=a*two_phase_acc_reg
//yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
//yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
//tmp1 = _mm_mul_ps(pa, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
//pa = _mm_shuffle_ps(pa, pa, 0xB1); // Re-arrange x to be ai,ar,bi,br
//tmp2 = _mm_mul_ps(pa, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
//pb = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
//pc1 = _mm_cvtps_epi32(pb); // convert from 32fc to 32ic
////complex 32fc multiplication two_phase_acc_reg=two_phase_acc_reg*two_phase_inc_reg
//yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
//yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
//tmp1 = _mm_mul_ps(two_phase_inc_reg, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
//tmp3 = _mm_shuffle_ps(two_phase_inc_reg, two_phase_inc_reg, 0xB1); // Re-arrange x to be ai,ar,bi,br
//tmp2 = _mm_mul_ps(tmp3, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
//two_phase_acc_reg = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
////next two samples
//_in_common += 2;
//pa = _mm_set_ps((float)(lv_cimag(_in_common[1])), (float)(lv_creal(_in_common[1])), (float)(lv_cimag(_in_common[0])), (float)(lv_creal(_in_common[0]))); // //load (2 byte imag, 2 byte real) x 2 into 128 bits reg
//__VOLK_GNSSSDR_PREFETCH(_in_common + 8);
////complex 32fc multiplication b=a*two_phase_acc_reg
//yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
//yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
//tmp1 = _mm_mul_ps(pa, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
//pa = _mm_shuffle_ps(pa, pa, 0xB1); // Re-arrange x to be ai,ar,bi,br
//tmp2 = _mm_mul_ps(pa, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
//pb = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
//pc2 = _mm_cvtps_epi32(pb); // convert from 32fc to 32ic
////complex 32fc multiplication two_phase_acc_reg=two_phase_acc_reg*two_phase_inc_reg
//yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
//yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
//tmp1 = _mm_mul_ps(two_phase_inc_reg, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
//tmp3 = _mm_shuffle_ps(two_phase_inc_reg, two_phase_inc_reg, 0xB1); // Re-arrange x to be ai,ar,bi,br
//tmp2 = _mm_mul_ps(tmp3, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
//two_phase_acc_reg = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
//// store four rotated in_common samples in the register b
//b = _mm_packs_epi32(pc1, pc2);// convert from 32ic to 16ic
////next two samples
//_in_common += 2;
//for (n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//a = _mm_load_si128((__m128i*)&(_in_a[n_vec][(number * ROTATOR_RELOAD + j) * 4])); //load (2 byte imag, 2 byte real) x 4 into 128 bits reg
//c = _mm_mullo_epi16(a, b); // a3.i*b3.i, a3.r*b3.r, ....
//c_sr = _mm_srli_si128(c, 2); // Shift a right by imm8 bytes while shifting in zeros, and store the results in dst.
//real = _mm_subs_epi16(c, c_sr);
//b_sl = _mm_slli_si128(b, 2); // b3.r, b2.i ....
//a_sl = _mm_slli_si128(a, 2); // a3.r, a2.i ....
//imag1 = _mm_mullo_epi16(a, b_sl); // a3.i*b3.r, ....
//imag2 = _mm_mullo_epi16(b, a_sl); // b3.i*a3.r, ....
//imag = _mm_adds_epi16(imag1, imag2);
//realcacc[n_vec] = _mm_adds_epi16(realcacc[n_vec], real);
//imagcacc[n_vec] = _mm_adds_epi16(imagcacc[n_vec], imag);
//}
//}
//// regenerate phase
//tmp1 = _mm_mul_ps(two_phase_acc_reg, two_phase_acc_reg);
//tmp2 = _mm_hadd_ps(tmp1, tmp1);
//tmp1 = _mm_shuffle_ps(tmp2, tmp2, 0xD8);
//tmp2 = _mm_sqrt_ps(tmp1);
//two_phase_acc_reg = _mm_div_ps(two_phase_acc_reg, tmp2);
//}
//for (j = 0; j < sse_iters % ROTATOR_RELOAD; j++)
//{
//pa = _mm_set_ps((float)(lv_cimag(_in_common[1])), (float)(lv_creal(_in_common[1])), (float)(lv_cimag(_in_common[0])), (float)(lv_creal(_in_common[0]))); // //load (2 byte imag, 2 byte real) x 2 into 128 bits reg
////complex 32fc multiplication b=a*two_phase_acc_reg
//yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
//yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
//tmp1 = _mm_mul_ps(pa, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
//pa = _mm_shuffle_ps(pa, pa, 0xB1); // Re-arrange x to be ai,ar,bi,br
//tmp2 = _mm_mul_ps(pa, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
//pb = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
//pc1 = _mm_cvtps_epi32(pb); // convert from 32fc to 32ic
////complex 32fc multiplication two_phase_acc_reg=two_phase_acc_reg*two_phase_inc_reg
//yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
//yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
//tmp1 = _mm_mul_ps(two_phase_inc_reg, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
//tmp3 = _mm_shuffle_ps(two_phase_inc_reg, two_phase_inc_reg, 0xB1); // Re-arrange x to be ai,ar,bi,br
//tmp2 = _mm_mul_ps(tmp3, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
//two_phase_acc_reg = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
////next two samples
//_in_common += 2;
//pa = _mm_set_ps((float)(lv_cimag(_in_common[1])), (float)(lv_creal(_in_common[1])), (float)(lv_cimag(_in_common[0])), (float)(lv_creal(_in_common[0]))); // //load (2 byte imag, 2 byte real) x 2 into 128 bits reg
//__VOLK_GNSSSDR_PREFETCH(_in_common + 8);
////complex 32fc multiplication b=a*two_phase_acc_reg
//yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
//yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
//tmp1 = _mm_mul_ps(pa, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
//pa = _mm_shuffle_ps(pa, pa, 0xB1); // Re-arrange x to be ai,ar,bi,br
//tmp2 = _mm_mul_ps(pa, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
//pb = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
//pc2 = _mm_cvtps_epi32(pb); // convert from 32fc to 32ic
////complex 32fc multiplication two_phase_acc_reg=two_phase_acc_reg*two_phase_inc_reg
//yl = _mm_moveldup_ps(two_phase_acc_reg); // Load yl with cr,cr,dr,dr
//yh = _mm_movehdup_ps(two_phase_acc_reg); // Load yh with ci,ci,di,di
//tmp1 = _mm_mul_ps(two_phase_inc_reg, yl); // tmp1 = ar*cr,ai*cr,br*dr,bi*dr
//tmp3 = _mm_shuffle_ps(two_phase_inc_reg, two_phase_inc_reg, 0xB1); // Re-arrange x to be ai,ar,bi,br
//tmp2 = _mm_mul_ps(tmp3, yh); // tmp2 = ai*ci,ar*ci,bi*di,br*di
//two_phase_acc_reg = _mm_addsub_ps(tmp1, tmp2); // ar*cr-ai*ci, ai*cr+ar*ci, br*dr-bi*di, bi*dr+br*di
//// store four rotated in_common samples in the register b
//b = _mm_packs_epi32(pc1, pc2);// convert from 32ic to 16ic
////next two samples
//_in_common += 2;
//for (n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//a = _mm_load_si128((__m128i*)&(_in_a[n_vec][((sse_iters / ROTATOR_RELOAD) * ROTATOR_RELOAD + j) * 4])); //load (2 byte imag, 2 byte real) x 4 into 128 bits reg
//c = _mm_mullo_epi16(a, b); // a3.i*b3.i, a3.r*b3.r, ....
//c_sr = _mm_srli_si128(c, 2); // Shift a right by imm8 bytes while shifting in zeros, and store the results in dst.
//real = _mm_subs_epi16(c, c_sr);
//b_sl = _mm_slli_si128(b, 2); // b3.r, b2.i ....
//a_sl = _mm_slli_si128(a, 2); // a3.r, a2.i ....
//imag1 = _mm_mullo_epi16(a, b_sl); // a3.i*b3.r, ....
//imag2 = _mm_mullo_epi16(b, a_sl); // b3.i*a3.r, ....
//imag = _mm_adds_epi16(imag1, imag2);
//realcacc[n_vec] = _mm_adds_epi16(realcacc[n_vec], real);
//imagcacc[n_vec] = _mm_adds_epi16(imagcacc[n_vec], imag);
//}
//}
//for (n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//realcacc[n_vec] = _mm_and_si128(realcacc[n_vec], mask_real);
//imagcacc[n_vec] = _mm_and_si128(imagcacc[n_vec], mask_imag);
//a = _mm_or_si128(realcacc[n_vec], imagcacc[n_vec]);
//_mm_store_si128((__m128i*)dotProductVector, a); // Store the results back into the dot product vector
//dotProduct = lv_cmake(0,0);
//for (i = 0; i < 4; ++i)
//{
//dotProduct = lv_cmake(sat_adds16i(lv_creal(dotProduct), lv_creal(dotProductVector[i])),
//sat_adds16i(lv_cimag(dotProduct), lv_cimag(dotProductVector[i])));
//}
//_out[n_vec] = dotProduct;
//}
//volk_gnsssdr_free(realcacc);
//volk_gnsssdr_free(imagcacc);
//tmp1 = _mm_mul_ps(two_phase_acc_reg, two_phase_acc_reg);
//tmp2 = _mm_hadd_ps(tmp1, tmp1);
//tmp1 = _mm_shuffle_ps(tmp2, tmp2, 0xD8);
//tmp2 = _mm_sqrt_ps(tmp1);
//two_phase_acc_reg = _mm_div_ps(two_phase_acc_reg, tmp2);
//_mm_store_ps((float*)two_phase_acc, two_phase_acc_reg);
////(*phase) = lv_cmake((float*)two_phase_acc[0], (float*)two_phase_acc[1]);
//(*phase) = two_phase_acc[0];
//for(n = sse_iters * 4; n < num_points; n++)
//{
//tmp16 = in_common[n]; //printf("a_sse phase %i: %f,%f\n", n,lv_creal(*phase),lv_cimag(*phase));
//tmp32 = lv_cmake((float)lv_creal(tmp16), (float)lv_cimag(tmp16)) * (*phase);
//tmp16 = lv_cmake((int16_t)rintf(lv_creal(tmp32)), (int16_t)rintf(lv_cimag(tmp32)));
//(*phase) *= phase_inc;
//for (n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//lv_16sc_t tmp = tmp16 * in_a[n_vec][n];
////lv_16sc_t tmp = lv_cmake(sat_adds16i(sat_muls16i(lv_creal(tmp16), lv_creal(in_a[n_vec][n])), - sat_muls16i(lv_cimag(tmp16), lv_cimag(in_a[n_vec][n]))) , sat_adds16i(sat_muls16i(lv_creal(tmp16), lv_cimag(in_a[n_vec][n])), sat_muls16i(lv_cimag(tmp16), lv_creal(in_a[n_vec][n]))));
//_out[n_vec] = lv_cmake(sat_adds16i(lv_creal(_out[n_vec]), lv_creal(tmp)),
//sat_adds16i(lv_cimag(_out[n_vec]), lv_cimag(tmp)));
//}
//}
//}
//#endif [> LV_HAVE_SSE3 <]
#ifdef LV_HAVE_SSE3 #ifdef LV_HAVE_SSE3
#include <pmmintrin.h> #include <pmmintrin.h>
@ -985,13 +737,11 @@ static inline void volk_gnsssdr_16ic_16i_rotator_dot_prod_16ic_xn_u_avx2(lv_16sc
__VOLK_GNSSSDR_PREFETCH(_in_common + 16); __VOLK_GNSSSDR_PREFETCH(_in_common + 16);
// Store and convert 32ic to 16ic: // Store and convert 32ic to 16ic:
b2 = _mm256_packs_epi32(c1, c2); b2 = _mm256_packs_epi32(c1, c2);
b2 = _mm256_permutevar8x32_epi32(b2, perm_idx); b2 = _mm256_permutevar8x32_epi32(b2, perm_idx);
_in_common += 4; _in_common += 4;
for (n_vec = 0; n_vec < num_a_vectors; n_vec++) for (n_vec = 0; n_vec < num_a_vectors; n_vec++)
{ {
@ -1049,558 +799,4 @@ static inline void volk_gnsssdr_16ic_16i_rotator_dot_prod_16ic_xn_u_avx2(lv_16sc
} }
#endif /* LV_HAVE_AVX2 */ #endif /* LV_HAVE_AVX2 */
//#ifdef LV_HAVE_NEONV7
//#include <arm_neon.h>
//static inline void volk_gnsssdr_16ic_16i_rotator_dot_prod_16ic_xn_neon(lv_16sc_t* result, const lv_16sc_t* in_common, const lv_32fc_t phase_inc, lv_32fc_t* phase, const int16_t** in_a, int num_a_vectors, unsigned int num_points)
//{
//const unsigned int neon_iters = num_points / 4;
//const int16_t** _in_a = in_a;
//const lv_16sc_t* _in_common = in_common;
//lv_16sc_t* _out = result;
//int n_vec;
//int i;
//unsigned int number;
//unsigned int n;
//lv_16sc_t tmp16_, tmp;
//lv_32fc_t tmp32_;
//if (neon_iters > 0)
//{
//lv_16sc_t dotProduct = lv_cmake(0,0);
//float arg_phase0 = cargf(*phase);
//float arg_phase_inc = cargf(phase_inc);
//float phase_est;
//lv_32fc_t ___phase4 = phase_inc * phase_inc * phase_inc * phase_inc;
//__VOLK_ATTR_ALIGNED(16) float32_t __phase4_real[4] = { lv_creal(___phase4), lv_creal(___phase4), lv_creal(___phase4), lv_creal(___phase4) };
//__VOLK_ATTR_ALIGNED(16) float32_t __phase4_imag[4] = { lv_cimag(___phase4), lv_cimag(___phase4), lv_cimag(___phase4), lv_cimag(___phase4) };
//float32x4_t _phase4_real = vld1q_f32(__phase4_real);
//float32x4_t _phase4_imag = vld1q_f32(__phase4_imag);
//lv_32fc_t phase2 = (lv_32fc_t)(*phase) * phase_inc;
//lv_32fc_t phase3 = phase2 * phase_inc;
//lv_32fc_t phase4 = phase3 * phase_inc;
//__VOLK_ATTR_ALIGNED(16) float32_t __phase_real[4] = { lv_creal((*phase)), lv_creal(phase2), lv_creal(phase3), lv_creal(phase4) };
//__VOLK_ATTR_ALIGNED(16) float32_t __phase_imag[4] = { lv_cimag((*phase)), lv_cimag(phase2), lv_cimag(phase3), lv_cimag(phase4) };
//float32x4_t _phase_real = vld1q_f32(__phase_real);
//float32x4_t _phase_imag = vld1q_f32(__phase_imag);
//int16x4x2_t a_val, b_val, c_val;
//__VOLK_ATTR_ALIGNED(16) lv_16sc_t dotProductVector[4];
//float32x4_t half = vdupq_n_f32(0.5f);
//int16x4x2_t tmp16;
//int32x4x2_t tmp32i;
//float32x4x2_t tmp32f, tmp32_real, tmp32_imag;
//float32x4_t sign, PlusHalf, Round;
//int16x4x2_t* accumulator = (int16x4x2_t*)volk_gnsssdr_malloc(num_a_vectors * sizeof(int16x4x2_t), volk_gnsssdr_get_alignment());
//for(n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//accumulator[n_vec].val[0] = vdup_n_s16(0);
//accumulator[n_vec].val[1] = vdup_n_s16(0);
//}
//for(number = 0; number < neon_iters; number++)
//{
//[> load 4 complex numbers (int 16 bits each component) <]
//tmp16 = vld2_s16((int16_t*)_in_common);
//__VOLK_GNSSSDR_PREFETCH(_in_common + 8);
//_in_common += 4;
//[> promote them to int 32 bits <]
//tmp32i.val[0] = vmovl_s16(tmp16.val[0]);
//tmp32i.val[1] = vmovl_s16(tmp16.val[1]);
//[> promote them to float 32 bits <]
//tmp32f.val[0] = vcvtq_f32_s32(tmp32i.val[0]);
//tmp32f.val[1] = vcvtq_f32_s32(tmp32i.val[1]);
//[> complex multiplication of four complex samples (float 32 bits each component) <]
//tmp32_real.val[0] = vmulq_f32(tmp32f.val[0], _phase_real);
//tmp32_real.val[1] = vmulq_f32(tmp32f.val[1], _phase_imag);
//tmp32_imag.val[0] = vmulq_f32(tmp32f.val[0], _phase_imag);
//tmp32_imag.val[1] = vmulq_f32(tmp32f.val[1], _phase_real);
//tmp32f.val[0] = vsubq_f32(tmp32_real.val[0], tmp32_real.val[1]);
//tmp32f.val[1] = vaddq_f32(tmp32_imag.val[0], tmp32_imag.val[1]);
//[> downcast results to int32 <]
//[> in __aarch64__ we can do that with vcvtaq_s32_f32(ret1); vcvtaq_s32_f32(ret2); <]
//sign = vcvtq_f32_u32((vshrq_n_u32(vreinterpretq_u32_f32(tmp32f.val[0]), 31)));
//PlusHalf = vaddq_f32(tmp32f.val[0], half);
//Round = vsubq_f32(PlusHalf, sign);
//tmp32i.val[0] = vcvtq_s32_f32(Round);
//sign = vcvtq_f32_u32((vshrq_n_u32(vreinterpretq_u32_f32(tmp32f.val[1]), 31)));
//PlusHalf = vaddq_f32(tmp32f.val[1], half);
//Round = vsubq_f32(PlusHalf, sign);
//tmp32i.val[1] = vcvtq_s32_f32(Round);
//[> downcast results to int16 <]
//tmp16.val[0] = vqmovn_s32(tmp32i.val[0]);
//tmp16.val[1] = vqmovn_s32(tmp32i.val[1]);
//[> compute next four phases <]
//tmp32_real.val[0] = vmulq_f32(_phase_real, _phase4_real);
//tmp32_real.val[1] = vmulq_f32(_phase_imag, _phase4_imag);
//tmp32_imag.val[0] = vmulq_f32(_phase_real, _phase4_imag);
//tmp32_imag.val[1] = vmulq_f32(_phase_imag, _phase4_real);
//_phase_real = vsubq_f32(tmp32_real.val[0], tmp32_real.val[1]);
//_phase_imag = vaddq_f32(tmp32_imag.val[0], tmp32_imag.val[1]);
//for (n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//a_val = vld2_s16((int16_t*)&(_in_a[n_vec][number*4])); //load (2 byte imag, 2 byte real) x 4 into 128 bits reg
////__VOLK_GNSSSDR_PREFETCH(&_in_a[n_vec][number*4] + 8);
//// multiply the real*real and imag*imag to get real result
//// a0r*b0r|a1r*b1r|a2r*b2r|a3r*b3r
//b_val.val[0] = vmul_s16(a_val.val[0], tmp16.val[0]);
//// a0i*b0i|a1i*b1i|a2i*b2i|a3i*b3i
//b_val.val[1] = vmul_s16(a_val.val[1], tmp16.val[1]);
//c_val.val[0] = vqsub_s16(b_val.val[0], b_val.val[1]);
//// Multiply cross terms to get the imaginary result
//// a0r*b0i|a1r*b1i|a2r*b2i|a3r*b3i
//b_val.val[0] = vmul_s16(a_val.val[0], tmp16.val[1]);
//// a0i*b0r|a1i*b1r|a2i*b2r|a3i*b3r
//b_val.val[1] = vmul_s16(a_val.val[1], tmp16.val[0]);
//c_val.val[1] = vqadd_s16(b_val.val[0], b_val.val[1]);
//accumulator[n_vec].val[0] = vqadd_s16(accumulator[n_vec].val[0], c_val.val[0]);
//accumulator[n_vec].val[1] = vqadd_s16(accumulator[n_vec].val[1], c_val.val[1]);
//}
//// Regenerate phase
//if ((number % 256) == 0)
//{
//phase_est = arg_phase0 + (number + 1) * 4 * arg_phase_inc;
//*phase = lv_cmake(cos(phase_est), sin(phase_est));
//phase2 = (lv_32fc_t)(*phase) * phase_inc;
//phase3 = phase2 * phase_inc;
//phase4 = phase3 * phase_inc;
//__VOLK_ATTR_ALIGNED(16) float32_t ____phase_real[4] = { lv_creal((*phase)), lv_creal(phase2), lv_creal(phase3), lv_creal(phase4) };
//__VOLK_ATTR_ALIGNED(16) float32_t ____phase_imag[4] = { lv_cimag((*phase)), lv_cimag(phase2), lv_cimag(phase3), lv_cimag(phase4) };
//_phase_real = vld1q_f32(____phase_real);
//_phase_imag = vld1q_f32(____phase_imag);
//}
//}
//for (n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//vst2_s16((int16_t*)dotProductVector, accumulator[n_vec]); // Store the results back into the dot product vector
//dotProduct = lv_cmake(0,0);
//for (i = 0; i < 4; ++i)
//{
//dotProduct = lv_cmake(sat_adds16i(lv_creal(dotProduct), lv_creal(dotProductVector[i])),
//sat_adds16i(lv_cimag(dotProduct), lv_cimag(dotProductVector[i])));
//}
//_out[n_vec] = dotProduct;
//}
//volk_gnsssdr_free(accumulator);
//vst1q_f32((float32_t*)__phase_real, _phase_real);
//vst1q_f32((float32_t*)__phase_imag, _phase_imag);
//(*phase) = lv_cmake((float32_t)__phase_real[0], (float32_t)__phase_imag[0]);
//}
//for (n = neon_iters * 4; n < num_points; n++)
//{
//tmp16_ = in_common[n]; //printf("neon phase %i: %f,%f\n", n,lv_creal(*phase),lv_cimag(*phase));
//tmp32_ = lv_cmake((float32_t)lv_creal(tmp16_), (float32_t)lv_cimag(tmp16_)) * (*phase);
//tmp16_ = lv_cmake((int16_t)rintf(lv_creal(tmp32_)), (int16_t)rintf(lv_cimag(tmp32_)));
//(*phase) *= phase_inc;
//for (n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//tmp = tmp16_ * in_a[n_vec][n];
//_out[n_vec] = lv_cmake(sat_adds16i(lv_creal(_out[n_vec]), lv_creal(tmp)), sat_adds16i(lv_cimag(_out[n_vec]), lv_cimag(tmp)));
//}
//}
//}
//#endif [> LV_HAVE_NEONV7 <]
//#ifdef LV_HAVE_NEONV7
//#include <arm_neon.h>
//#include <volk_gnsssdr/volk_gnsssdr_neon_intrinsics.h>
//static inline void volk_gnsssdr_16ic_16i_rotator_dot_prod_16ic_xn_neon_vma(lv_16sc_t* result, const lv_16sc_t* in_common, const lv_32fc_t phase_inc, lv_32fc_t* phase, const int16_t** in_a, int num_a_vectors, unsigned int num_points)
//{
//const unsigned int neon_iters = num_points / 4;
//const int16_t** _in_a = in_a;
//const lv_16sc_t* _in_common = in_common;
//lv_16sc_t* _out = result;
//int n_vec;
//int i;
//unsigned int number;
//unsigned int n;
//lv_16sc_t tmp16_, tmp;
//lv_32fc_t tmp32_;
//if (neon_iters > 0)
//{
//lv_16sc_t dotProduct = lv_cmake(0,0);
//float arg_phase0 = cargf(*phase);
//float arg_phase_inc = cargf(phase_inc);
//float phase_est;
////printf("arg phase0: %f", arg_phase0);
//lv_32fc_t ___phase4 = phase_inc * phase_inc * phase_inc * phase_inc;
//__VOLK_ATTR_ALIGNED(16) float32_t __phase4_real[4] = { lv_creal(___phase4), lv_creal(___phase4), lv_creal(___phase4), lv_creal(___phase4) };
//__VOLK_ATTR_ALIGNED(16) float32_t __phase4_imag[4] = { lv_cimag(___phase4), lv_cimag(___phase4), lv_cimag(___phase4), lv_cimag(___phase4) };
//float32x4_t _phase4_real = vld1q_f32(__phase4_real);
//float32x4_t _phase4_imag = vld1q_f32(__phase4_imag);
//lv_32fc_t phase2 = (lv_32fc_t)(*phase) * phase_inc;
//lv_32fc_t phase3 = phase2 * phase_inc;
//lv_32fc_t phase4 = phase3 * phase_inc;
//__VOLK_ATTR_ALIGNED(16) float32_t __phase_real[4] = { lv_creal((*phase)), lv_creal(phase2), lv_creal(phase3), lv_creal(phase4) };
//__VOLK_ATTR_ALIGNED(16) float32_t __phase_imag[4] = { lv_cimag((*phase)), lv_cimag(phase2), lv_cimag(phase3), lv_cimag(phase4) };
//float32x4_t _phase_real = vld1q_f32(__phase_real);
//float32x4_t _phase_imag = vld1q_f32(__phase_imag);
//int16x4x2_t a_val, b_val;
//__VOLK_ATTR_ALIGNED(16) lv_16sc_t dotProductVector[4];
//float32x4_t half = vdupq_n_f32(0.5f);
//int16x4x2_t tmp16;
//int32x4x2_t tmp32i;
//float32x4x2_t tmp32f, tmp32_real, tmp32_imag;
//float32x4_t sign, PlusHalf, Round;
//int16x4x2_t* accumulator = (int16x4x2_t*)volk_gnsssdr_malloc(num_a_vectors * sizeof(int16x4x2_t), volk_gnsssdr_get_alignment());
//for(n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//accumulator[n_vec].val[0] = vdup_n_s16(0);
//accumulator[n_vec].val[1] = vdup_n_s16(0);
//}
//for(number = 0; number < neon_iters; number++)
//{
//[> load 4 complex numbers (int 16 bits each component) <]
//tmp16 = vld2_s16((int16_t*)_in_common);
//__VOLK_GNSSSDR_PREFETCH(_in_common + 8);
//_in_common += 4;
//[> promote them to int 32 bits <]
//tmp32i.val[0] = vmovl_s16(tmp16.val[0]);
//tmp32i.val[1] = vmovl_s16(tmp16.val[1]);
//[> promote them to float 32 bits <]
//tmp32f.val[0] = vcvtq_f32_s32(tmp32i.val[0]);
//tmp32f.val[1] = vcvtq_f32_s32(tmp32i.val[1]);
//[> complex multiplication of four complex samples (float 32 bits each component) <]
//tmp32_real.val[0] = vmulq_f32(tmp32f.val[0], _phase_real);
//tmp32_real.val[1] = vmulq_f32(tmp32f.val[1], _phase_imag);
//tmp32_imag.val[0] = vmulq_f32(tmp32f.val[0], _phase_imag);
//tmp32_imag.val[1] = vmulq_f32(tmp32f.val[1], _phase_real);
//tmp32f.val[0] = vsubq_f32(tmp32_real.val[0], tmp32_real.val[1]);
//tmp32f.val[1] = vaddq_f32(tmp32_imag.val[0], tmp32_imag.val[1]);
//[> downcast results to int32 <]
//[> in __aarch64__ we can do that with vcvtaq_s32_f32(ret1); vcvtaq_s32_f32(ret2); <]
//sign = vcvtq_f32_u32((vshrq_n_u32(vreinterpretq_u32_f32(tmp32f.val[0]), 31)));
//PlusHalf = vaddq_f32(tmp32f.val[0], half);
//Round = vsubq_f32(PlusHalf, sign);
//tmp32i.val[0] = vcvtq_s32_f32(Round);
//sign = vcvtq_f32_u32((vshrq_n_u32(vreinterpretq_u32_f32(tmp32f.val[1]), 31)));
//PlusHalf = vaddq_f32(tmp32f.val[1], half);
//Round = vsubq_f32(PlusHalf, sign);
//tmp32i.val[1] = vcvtq_s32_f32(Round);
//[> downcast results to int16 <]
//tmp16.val[0] = vqmovn_s32(tmp32i.val[0]);
//tmp16.val[1] = vqmovn_s32(tmp32i.val[1]);
//[> compute next four phases <]
//tmp32_real.val[0] = vmulq_f32(_phase_real, _phase4_real);
//tmp32_real.val[1] = vmulq_f32(_phase_imag, _phase4_imag);
//tmp32_imag.val[0] = vmulq_f32(_phase_real, _phase4_imag);
//tmp32_imag.val[1] = vmulq_f32(_phase_imag, _phase4_real);
//_phase_real = vsubq_f32(tmp32_real.val[0], tmp32_real.val[1]);
//_phase_imag = vaddq_f32(tmp32_imag.val[0], tmp32_imag.val[1]);
//// Regenerate phase
//if ((number % 256) == 0)
//{
////printf("computed phase: %f\n", cos(cargf(lv_cmake(_phase_real[0],_phase_imag[0]))));
//phase_est = arg_phase0 + (number + 1) * 4 * arg_phase_inc;
////printf("Estimated phase: %f\n\n", cos(phase_est));
//*phase = lv_cmake(cos(phase_est), sin(phase_est));
//phase2 = (lv_32fc_t)(*phase) * phase_inc;
//phase3 = phase2 * phase_inc;
//phase4 = phase3 * phase_inc;
//__VOLK_ATTR_ALIGNED(16) float32_t ____phase_real[4] = { lv_creal((*phase)), lv_creal(phase2), lv_creal(phase3), lv_creal(phase4) };
//__VOLK_ATTR_ALIGNED(16) float32_t ____phase_imag[4] = { lv_cimag((*phase)), lv_cimag(phase2), lv_cimag(phase3), lv_cimag(phase4) };
//_phase_real = vld1q_f32(____phase_real);
//_phase_imag = vld1q_f32(____phase_imag);
//// Round = vmulq_f32(_phase_real, _phase_real);
//// Round = vmlaq_f32(Round, _phase_imag, _phase_imag);
//// Round = vsqrtq_f32(Round);//printf("sqrt: %f \n", Round[0]);
////Round = vrsqrteq_f32(Round);printf("1/sqtr: %f \n",Round[0]);
////Round = vrecpeq_f32((Round);
//// _phase_real = vdivq_f32(_phase_real, Round);
//// _phase_imag = vdivq_f32(_phase_imag, Round);
////_phase_real = vmulq_f32(_phase_real, Round);
////_phase_imag = vmulq_f32(_phase_imag, Round);
////printf("After %i: %f,%f, %f\n\n", number, _phase_real[0], _phase_imag[0], sqrt(_phase_real[0]*_phase_real[0]+_phase_imag[0]*_phase_imag[0]));
//}
//for (n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//a_val = vld2_s16((int16_t*)&(_in_a[n_vec][number*4]));
//b_val.val[0] = vmul_s16(a_val.val[0], tmp16.val[0]);
//b_val.val[1] = vmul_s16(a_val.val[1], tmp16.val[0]);
//// use multiply accumulate/subtract to get result
//b_val.val[0] = vmls_s16(b_val.val[0], a_val.val[1], tmp16.val[1]);
//b_val.val[1] = vmla_s16(b_val.val[1], a_val.val[0], tmp16.val[1]);
//accumulator[n_vec].val[0] = vqadd_s16(accumulator[n_vec].val[0], b_val.val[0]);
//accumulator[n_vec].val[1] = vqadd_s16(accumulator[n_vec].val[1], b_val.val[1]);
//}
//}
//for (n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//vst2_s16((int16_t*)dotProductVector, accumulator[n_vec]); // Store the results back into the dot product vector
//dotProduct = lv_cmake(0,0);
//for (i = 0; i < 4; ++i)
//{
//dotProduct = lv_cmake(sat_adds16i(lv_creal(dotProduct), lv_creal(dotProductVector[i])),
//sat_adds16i(lv_cimag(dotProduct), lv_cimag(dotProductVector[i])));
//}
//_out[n_vec] = dotProduct;
//}
//volk_gnsssdr_free(accumulator);
//vst1q_f32((float32_t*)__phase_real, _phase_real);
//vst1q_f32((float32_t*)__phase_imag, _phase_imag);
//(*phase) = lv_cmake((float32_t)__phase_real[0], (float32_t)__phase_imag[0]);
//}
//for (n = neon_iters * 4; n < num_points; n++)
//{
//tmp16_ = in_common[n]; //printf("neon phase %i: %f,%f\n", n,lv_creal(*phase),lv_cimag(*phase));
//tmp32_ = lv_cmake((float32_t)lv_creal(tmp16_), (float32_t)lv_cimag(tmp16_)) * (*phase);
//tmp16_ = lv_cmake((int16_t)rintf(lv_creal(tmp32_)), (int16_t)rintf(lv_cimag(tmp32_)));
//(*phase) *= phase_inc;
//for (n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//tmp = tmp16_ * in_a[n_vec][n];
//_out[n_vec] = lv_cmake(sat_adds16i(lv_creal(_out[n_vec]), lv_creal(tmp)), sat_adds16i(lv_cimag(_out[n_vec]), lv_cimag(tmp)));
//}
//}
//}
//#endif [> LV_HAVE_NEONV7 <]
//#ifdef LV_HAVE_NEONV7
//#include <arm_neon.h>
//#include <volk_gnsssdr/volk_gnsssdr_neon_intrinsics.h>
//static inline void volk_gnsssdr_16ic_16i_rotator_dot_prod_16ic_xn_neon_optvma(lv_16sc_t* result, const lv_16sc_t* in_common, const lv_32fc_t phase_inc, lv_32fc_t* phase, const int16_t** in_a, int num_a_vectors, unsigned int num_points)
//{
//const unsigned int neon_iters = num_points / 4;
//const int16_t** _in_a = in_a;
//const lv_16sc_t* _in_common = in_common;
//lv_16sc_t* _out = result;
//int n_vec;
//int i;
//unsigned int number;
//unsigned int n;
//lv_16sc_t tmp16_, tmp;
//lv_32fc_t tmp32_;
//if (neon_iters > 0)
//{
//lv_16sc_t dotProduct = lv_cmake(0,0);
//float arg_phase0 = cargf(*phase);
//float arg_phase_inc = cargf(phase_inc);
//float phase_est;
//lv_32fc_t ___phase4 = phase_inc * phase_inc * phase_inc * phase_inc;
//__VOLK_ATTR_ALIGNED(16) float32_t __phase4_real[4] = { lv_creal(___phase4), lv_creal(___phase4), lv_creal(___phase4), lv_creal(___phase4) };
//__VOLK_ATTR_ALIGNED(16) float32_t __phase4_imag[4] = { lv_cimag(___phase4), lv_cimag(___phase4), lv_cimag(___phase4), lv_cimag(___phase4) };
//float32x4_t _phase4_real = vld1q_f32(__phase4_real);
//float32x4_t _phase4_imag = vld1q_f32(__phase4_imag);
//lv_32fc_t phase2 = (lv_32fc_t)(*phase) * phase_inc;
//lv_32fc_t phase3 = phase2 * phase_inc;
//lv_32fc_t phase4 = phase3 * phase_inc;
//__VOLK_ATTR_ALIGNED(16) float32_t __phase_real[4] = { lv_creal((*phase)), lv_creal(phase2), lv_creal(phase3), lv_creal(phase4) };
//__VOLK_ATTR_ALIGNED(16) float32_t __phase_imag[4] = { lv_cimag((*phase)), lv_cimag(phase2), lv_cimag(phase3), lv_cimag(phase4) };
//float32x4_t _phase_real = vld1q_f32(__phase_real);
//float32x4_t _phase_imag = vld1q_f32(__phase_imag);
//int16x4x2_t a_val, b_val;
//__VOLK_ATTR_ALIGNED(16) lv_16sc_t dotProductVector[4];
//float32x4_t half = vdupq_n_f32(0.5f);
//int32x4x2_t tmp32i;
//float32x4x2_t tmp32f, tmp32_real, tmp32_imag;
//float32x4_t sign, PlusHalf, Round;
//int16x4x2_t* accumulator1 = (int16x4x2_t*)volk_gnsssdr_malloc(num_a_vectors * sizeof(int16x4x2_t), volk_gnsssdr_get_alignment());
//int16x4x2_t* accumulator2 = (int16x4x2_t*)volk_gnsssdr_malloc(num_a_vectors * sizeof(int16x4x2_t), volk_gnsssdr_get_alignment());
//for(n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//accumulator1[n_vec].val[0] = vdup_n_s16(0);
//accumulator1[n_vec].val[1] = vdup_n_s16(0);
//accumulator2[n_vec].val[0] = vdup_n_s16(0);
//accumulator2[n_vec].val[1] = vdup_n_s16(0);
//}
//for(number = 0; number < neon_iters; number++)
//{
//[> load 4 complex numbers (int 16 bits each component) <]
//b_val = vld2_s16((int16_t*)_in_common);
//__VOLK_GNSSSDR_PREFETCH(_in_common + 8);
//_in_common += 4;
//[> promote them to int 32 bits <]
//tmp32i.val[0] = vmovl_s16(b_val.val[0]);
//tmp32i.val[1] = vmovl_s16(b_val.val[1]);
//[> promote them to float 32 bits <]
//tmp32f.val[0] = vcvtq_f32_s32(tmp32i.val[0]);
//tmp32f.val[1] = vcvtq_f32_s32(tmp32i.val[1]);
//[> complex multiplication of four complex samples (float 32 bits each component) <]
//tmp32_real.val[0] = vmulq_f32(tmp32f.val[0], _phase_real);
//tmp32_real.val[1] = vmulq_f32(tmp32f.val[1], _phase_imag);
//tmp32_imag.val[0] = vmulq_f32(tmp32f.val[0], _phase_imag);
//tmp32_imag.val[1] = vmulq_f32(tmp32f.val[1], _phase_real);
//tmp32f.val[0] = vsubq_f32(tmp32_real.val[0], tmp32_real.val[1]);
//tmp32f.val[1] = vaddq_f32(tmp32_imag.val[0], tmp32_imag.val[1]);
//[> downcast results to int32 <]
//[> in __aarch64__ we can do that with vcvtaq_s32_f32(ret1); vcvtaq_s32_f32(ret2); <]
//sign = vcvtq_f32_u32((vshrq_n_u32(vreinterpretq_u32_f32(tmp32f.val[0]), 31)));
//PlusHalf = vaddq_f32(tmp32f.val[0], half);
//Round = vsubq_f32(PlusHalf, sign);
//tmp32i.val[0] = vcvtq_s32_f32(Round);
//sign = vcvtq_f32_u32((vshrq_n_u32(vreinterpretq_u32_f32(tmp32f.val[1]), 31)));
//PlusHalf = vaddq_f32(tmp32f.val[1], half);
//Round = vsubq_f32(PlusHalf, sign);
//tmp32i.val[1] = vcvtq_s32_f32(Round);
//[> downcast results to int16 <]
//b_val.val[0] = vqmovn_s32(tmp32i.val[0]);
//b_val.val[1] = vqmovn_s32(tmp32i.val[1]);
//[> compute next four phases <]
//tmp32_real.val[0] = vmulq_f32(_phase_real, _phase4_real);
//tmp32_real.val[1] = vmulq_f32(_phase_imag, _phase4_imag);
//tmp32_imag.val[0] = vmulq_f32(_phase_real, _phase4_imag);
//tmp32_imag.val[1] = vmulq_f32(_phase_imag, _phase4_real);
//_phase_real = vsubq_f32(tmp32_real.val[0], tmp32_real.val[1]);
//_phase_imag = vaddq_f32(tmp32_imag.val[0], tmp32_imag.val[1]);
//// Regenerate phase
//if ((number % 256) == 0)
//{
////printf("computed phase: %f\n", cos(cargf(lv_cmake(_phase_real[0],_phase_imag[0]))));
//phase_est = arg_phase0 + (number + 1) * 4 * arg_phase_inc;
////printf("Estimated phase: %f\n\n", cos(phase_est));
//*phase = lv_cmake(cos(phase_est), sin(phase_est));
//phase2 = (lv_32fc_t)(*phase) * phase_inc;
//phase3 = phase2 * phase_inc;
//phase4 = phase3 * phase_inc;
//__VOLK_ATTR_ALIGNED(16) float32_t ____phase_real[4] = { lv_creal((*phase)), lv_creal(phase2), lv_creal(phase3), lv_creal(phase4) };
//__VOLK_ATTR_ALIGNED(16) float32_t ____phase_imag[4] = { lv_cimag((*phase)), lv_cimag(phase2), lv_cimag(phase3), lv_cimag(phase4) };
//_phase_real = vld1q_f32(____phase_real);
//_phase_imag = vld1q_f32(____phase_imag);
//}
//for (n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//a_val = vld2_s16((int16_t*)&(_in_a[n_vec][number*4]));
//// use 2 accumulators to remove inter-instruction data dependencies
//accumulator1[n_vec].val[0] = vmla_s16(accumulator1[n_vec].val[0], a_val.val[0], b_val.val[0]);
//accumulator1[n_vec].val[1] = vmla_s16(accumulator1[n_vec].val[1], a_val.val[0], b_val.val[1]);
//accumulator2[n_vec].val[0] = vmls_s16(accumulator2[n_vec].val[0], a_val.val[1], b_val.val[1]);
//accumulator2[n_vec].val[1] = vmla_s16(accumulator2[n_vec].val[1], a_val.val[1], b_val.val[0]);
//}
//}
//for (n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//accumulator1[n_vec].val[0] = vqadd_s16(accumulator1[n_vec].val[0], accumulator2[n_vec].val[0]);
//accumulator1[n_vec].val[1] = vqadd_s16(accumulator1[n_vec].val[1], accumulator2[n_vec].val[1]);
//}
//for (n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//vst2_s16((int16_t*)dotProductVector, accumulator1[n_vec]); // Store the results back into the dot product vector
//dotProduct = lv_cmake(0,0);
//for (i = 0; i < 4; ++i)
//{
//dotProduct = lv_cmake(sat_adds16i(lv_creal(dotProduct), lv_creal(dotProductVector[i])),
//sat_adds16i(lv_cimag(dotProduct), lv_cimag(dotProductVector[i])));
//}
//_out[n_vec] = dotProduct;
//}
//volk_gnsssdr_free(accumulator1);
//volk_gnsssdr_free(accumulator2);
//vst1q_f32((float32_t*)__phase_real, _phase_real);
//vst1q_f32((float32_t*)__phase_imag, _phase_imag);
//(*phase) = lv_cmake((float32_t)__phase_real[0], (float32_t)__phase_imag[0]);
//}
//for (n = neon_iters * 4; n < num_points; n++)
//{
//tmp16_ = in_common[n]; //printf("neon phase %i: %f,%f\n", n,lv_creal(*phase),lv_cimag(*phase));
//tmp32_ = lv_cmake((float32_t)lv_creal(tmp16_), (float32_t)lv_cimag(tmp16_)) * (*phase);
//tmp16_ = lv_cmake((int16_t)rintf(lv_creal(tmp32_)), (int16_t)rintf(lv_cimag(tmp32_)));
//(*phase) *= phase_inc;
//for (n_vec = 0; n_vec < num_a_vectors; n_vec++)
//{
//tmp = tmp16_ * in_a[n_vec][n];
//_out[n_vec] = lv_cmake(sat_adds16i(lv_creal(_out[n_vec]), lv_creal(tmp)), sat_adds16i(lv_cimag(_out[n_vec]), lv_cimag(tmp)));
//}
//}
//}
//#endif [> LV_HAVE_NEONV7 <]
#endif /* INCLUDED_volk_gnsssdr_16ic_16i_dot_prod_16ic_xn_H */ #endif /* INCLUDED_volk_gnsssdr_16ic_16i_dot_prod_16ic_xn_H */

152
src/algorithms/libs/volk_gnsssdr_module/volk_gnsssdr/kernels/volk_gnsssdr/volk_gnsssdr_16ic_16i_rotator_dotprodxnpuppet_16ic.h
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@ -131,36 +131,6 @@ static inline void volk_gnsssdr_16ic_16i_rotator_dotprodxnpuppet_16ic_a_sse3(lv_
#endif // SSE3 #endif // SSE3
//#ifdef LV_HAVE_SSE3
//static inline void volk_gnsssdr_16ic_16i_rotator_dotprodxnpuppet_16ic_a_sse3_reload(lv_16sc_t* result, const lv_16sc_t* local_code, const lv_16sc_t* in, unsigned int num_points)
//{
//// phases must be normalized. Phase rotator expects a complex exponential input!
//float rem_carrier_phase_in_rad = 0.345;
//float phase_step_rad = 0.1;
//lv_32fc_t phase[1];
//phase[0] = lv_cmake(cos(rem_carrier_phase_in_rad), sin(rem_carrier_phase_in_rad));
//lv_32fc_t phase_inc[1];
//phase_inc[0] = lv_cmake(cos(phase_step_rad), sin(phase_step_rad));
//int n;
//int num_a_vectors = 3;
//int16_t** in_a = (int16_t**)volk_gnsssdr_malloc(sizeof(int16_t*) * num_a_vectors, volk_gnsssdr_get_alignment());
//for(n = 0; n < num_a_vectors; n++)
//{
//in_a[n] = (int16_t*)volk_gnsssdr_malloc(sizeof(int16_t) * num_points, volk_gnsssdr_get_alignment());
//memcpy((int16_t*)in_a[n], (int16_t*)in, sizeof(int16_t) * num_points);
//}
//volk_gnsssdr_16ic_16i_rotator_dot_prod_16ic_xn_a_sse3_reload(result, local_code, phase_inc[0], phase, (const int16_t**) in_a, num_a_vectors, num_points);
//for(n = 0; n < num_a_vectors; n++)
//{
//volk_gnsssdr_free(in_a[n]);
//}
//volk_gnsssdr_free(in_a);
//}
//#endif // SSE3
#ifdef LV_HAVE_SSE3 #ifdef LV_HAVE_SSE3
static inline void volk_gnsssdr_16ic_16i_rotator_dotprodxnpuppet_16ic_u_sse3(lv_16sc_t* result, const lv_16sc_t* local_code, const lv_16sc_t* in, unsigned int num_points) static inline void volk_gnsssdr_16ic_16i_rotator_dotprodxnpuppet_16ic_u_sse3(lv_16sc_t* result, const lv_16sc_t* local_code, const lv_16sc_t* in, unsigned int num_points)
@ -224,36 +194,6 @@ static inline void volk_gnsssdr_16ic_16i_rotator_dotprodxnpuppet_16ic_a_avx2(lv_
#endif // AVX2 #endif // AVX2
//#ifdef LV_HAVE_AVX2
//static inline void volk_gnsssdr_16ic_16i_rotator_dotprodxnpuppet_16ic_a_avx2_reload(lv_16sc_t* result, const lv_16sc_t* local_code, const lv_16sc_t* in, unsigned int num_points)
//{
//// phases must be normalized. Phase rotator expects a complex exponential input!
//float rem_carrier_phase_in_rad = 0.345;
//float phase_step_rad = 0.1;
//lv_32fc_t phase[1];
//phase[0] = lv_cmake(cos(rem_carrier_phase_in_rad), sin(rem_carrier_phase_in_rad));
//lv_32fc_t phase_inc[1];
//phase_inc[0] = lv_cmake(cos(phase_step_rad), sin(phase_step_rad));
//int n;
//int num_a_vectors = 3;
//int16_t** in_a = (int16_t**)volk_gnsssdr_malloc(sizeof(int16_t*) * num_a_vectors, volk_gnsssdr_get_alignment());
//for(n = 0; n < num_a_vectors; n++)
//{
//in_a[n] = (int16_t*)volk_gnsssdr_malloc(sizeof(int16_t) * num_points, volk_gnsssdr_get_alignment());
//memcpy((int16_t*)in_a[n], (int16_t*)in, sizeof(int16_t) * num_points);
//}
//volk_gnsssdr_16ic_16i_rotator_dot_prod_16ic_xn_a_avx2_reload(result, local_code, phase_inc[0], phase, (const int16_t**) in_a, num_a_vectors, num_points);
//for(n = 0; n < num_a_vectors; n++)
//{
//volk_gnsssdr_free(in_a[n]);
//}
//volk_gnsssdr_free(in_a);
//}
//#endif // AVX2
#ifdef LV_HAVE_AVX2 #ifdef LV_HAVE_AVX2
static inline void volk_gnsssdr_16ic_16i_rotator_dotprodxnpuppet_16ic_u_avx2(lv_16sc_t* result, const lv_16sc_t* local_code, const lv_16sc_t* in, unsigned int num_points) static inline void volk_gnsssdr_16ic_16i_rotator_dotprodxnpuppet_16ic_u_avx2(lv_16sc_t* result, const lv_16sc_t* local_code, const lv_16sc_t* in, unsigned int num_points)
@ -286,96 +226,4 @@ static inline void volk_gnsssdr_16ic_16i_rotator_dotprodxnpuppet_16ic_u_avx2(lv_
#endif // AVX2 #endif // AVX2
//#ifdef LV_HAVE_AVX2
//static inline void volk_gnsssdr_16ic_16i_rotator_dotprodxnpuppet_16ic_u_avx2_reload(lv_16sc_t* result, const lv_16sc_t* local_code, const lv_16sc_t* in, unsigned int num_points)
//{
//// phases must be normalized. Phase rotator expects a complex exponential input!
//float rem_carrier_phase_in_rad = 0.345;
//float phase_step_rad = 0.1;
//lv_32fc_t phase[1];
//phase[0] = lv_cmake(cos(rem_carrier_phase_in_rad), sin(rem_carrier_phase_in_rad));
//lv_32fc_t phase_inc[1];
//phase_inc[0] = lv_cmake(cos(phase_step_rad), sin(phase_step_rad));
//int n;
//int num_a_vectors = 3;
//int16_t** in_a = (int16_t**)volk_gnsssdr_malloc(sizeof(int16_t*) * num_a_vectors, volk_gnsssdr_get_alignment());
//for(n = 0; n < num_a_vectors; n++)
//{
//in_a[n] = (int16_t*)volk_gnsssdr_malloc(sizeof(int16_t) * num_points, volk_gnsssdr_get_alignment());
//memcpy((int16_t*)in_a[n], (int16_t*)in, sizeof(int16_t) * num_points);
//}
//volk_gnsssdr_16ic_16i_rotator_dot_prod_16ic_xn_a_avx2_reload(result, local_code, phase_inc[0], phase, (const int16_t**) in_a, num_a_vectors, num_points);
//for(n = 0; n < num_a_vectors; n++)
//{
//volk_gnsssdr_free(in_a[n]);
//}
//volk_gnsssdr_free(in_a);
//}
//#endif // AVX2
//#ifdef LV_HAVE_NEONV7
//static inline void volk_gnsssdr_16ic_16i_rotator_dotprodxnpuppet_16ic_neon(lv_16sc_t* result, const lv_16sc_t* local_code, const lv_16sc_t* in, unsigned int num_points)
//{
//// phases must be normalized. Phase rotator expects a complex exponential input!
//float rem_carrier_phase_in_rad = 0.345;
//float phase_step_rad = 0.1;
//lv_32fc_t phase[1];
//phase[0] = lv_cmake(cos(rem_carrier_phase_in_rad), sin(rem_carrier_phase_in_rad));
//lv_32fc_t phase_inc[1];
//phase_inc[0] = lv_cmake(cos(phase_step_rad), sin(phase_step_rad));
//int n;
//int num_a_vectors = 3;
//int16_t** in_a = (int16_t**)volk_gnsssdr_malloc(sizeof(int16_t*) * num_a_vectors, volk_gnsssdr_get_alignment());
//for(n = 0; n < num_a_vectors; n++)
//{
//in_a[n] = (int16_t*)volk_gnsssdr_malloc(sizeof(int16_t) * num_points, volk_gnsssdr_get_alignment());
//memcpy((int16_t*)in_a[n], (int16_t*)in, sizeof(int16_t) * num_points);
//}
//volk_gnsssdr_16ic_16i_rotator_dot_prod_16ic_xn_neon(result, local_code, phase_inc[0], phase, (const int16_t**) in_a, num_a_vectors, num_points);
//for(n = 0; n < num_a_vectors; n++)
//{
//volk_gnsssdr_free(in_a[n]);
//}
//volk_gnsssdr_free(in_a);
//}
//#endif // NEON
//#ifdef LV_HAVE_NEONV7
//static inline void volk_gnsssdr_16ic_16i_rotator_dotprodxnpuppet_16ic_neon_vma(lv_16sc_t* result, const lv_16sc_t* local_code, const lv_16sc_t* in, unsigned int num_points)
//{
//// phases must be normalized. Phase rotator expects a complex exponential input!
//float rem_carrier_phase_in_rad = 0.345;
//float phase_step_rad = 0.1;
//lv_32fc_t phase[1];
//phase[0] = lv_cmake(cos(rem_carrier_phase_in_rad), sin(rem_carrier_phase_in_rad));
//lv_32fc_t phase_inc[1];
//phase_inc[0] = lv_cmake(cos(phase_step_rad), sin(phase_step_rad));
//int n;
//int num_a_vectors = 3;
//int16_t** in_a = (int16_t**)volk_gnsssdr_malloc(sizeof(int16_t*) * num_a_vectors, volk_gnsssdr_get_alignment());
//for(n = 0; n < num_a_vectors; n++)
//{
//in_a[n] = (int16_t*)volk_gnsssdr_malloc(sizeof(int16_t) * num_points, volk_gnsssdr_get_alignment());
//memcpy((int16_t*)in_a[n], (int16_t*)in, sizeof(int16_t) * num_points);
//}
//volk_gnsssdr_16ic_16i_rotator_dot_prod_16ic_xn_neon_vma(result, local_code, phase_inc[0], phase, (const int16_t**) in_a, num_a_vectors, num_points);
//for(n = 0; n < num_a_vectors; n++)
//{
//volk_gnsssdr_free(in_a[n]);
//}
//volk_gnsssdr_free(in_a);
//}
//#endif // NEON
#endif // INCLUDED_volk_gnsssdr_16ic_16i_rotator_dotprodxnpuppet_16ic_H #endif // INCLUDED_volk_gnsssdr_16ic_16i_rotator_dotprodxnpuppet_16ic_H

30
src/algorithms/libs/volk_gnsssdr_module/volk_gnsssdr/kernels/volk_gnsssdr/volk_gnsssdr_16ic_conjugate_16ic.h
View File

@ -200,34 +200,4 @@ static inline void volk_gnsssdr_16ic_conjugate_16ic_u_avx2(lv_16sc_t* cVector, c
} }
#endif /* LV_HAVE_AVX2 */ #endif /* LV_HAVE_AVX2 */
//
//
//#ifdef LV_HAVE_NEONV7
//#include <arm_neon.h>
//
//static inline void volk_gnsssdr_16ic_conjugate_16ic_neon(lv_16sc_t* cVector, const lv_16sc_t* aVector, unsigned int num_points)
//{
// const unsigned int sse_iters = num_points / 4;
// unsigned int i;
// lv_16sc_t* c = cVector;
// const lv_16sc_t* a = aVector;
// int16x4x2_t a_val;
//
// for (i = 0; i < sse_iters; ++i)
// {
// a_val = vld2_s16((const int16_t*)a);
// __VOLK_GNSSSDR_PREFETCH(a + 4);
// a_val.val[1] = vneg_s16(a_val.val[1]);
// vst2_s16((int16_t*)c, a_val);
// a += 4;
// c += 4;
// }
//
// for (i = sse_iters * 4; i < num_points; ++i)
// {
// *c++ = lv_conj(*a++);
// }
//}
//#endif /* LV_HAVE_NEONV7 */
#endif /* INCLUDED_volk_gnsssdr_16ic_conjugate_16ic_H */ #endif /* INCLUDED_volk_gnsssdr_16ic_conjugate_16ic_H */

29
src/algorithms/libs/volk_gnsssdr_module/volk_gnsssdr/kernels/volk_gnsssdr/volk_gnsssdr_32f_high_dynamics_resamplerxnpuppet_32f.h
View File

@ -256,33 +256,6 @@ static inline void volk_gnsssdr_32f_high_dynamics_resamplerxnpuppet_32f_u_avx(fl
volk_gnsssdr_free(result_aux); volk_gnsssdr_free(result_aux);
} }
#endif #endif
//
//#ifdef LV_HAVE_NEONV7
//static inline void volk_gnsssdr_32f_resamplerxnpuppet_32f_neon(float* result, const float* local_code, unsigned int num_points)
//{
// int code_length_chips = 2046;
// float code_phase_step_chips = ((float)(code_length_chips) + 0.1) / ((float)num_points);
// int num_out_vectors = 3;
// float rem_code_phase_chips = -0.234;
// int n;
// float shifts_chips[3] = {-0.1, 0.0, 0.1};
//
// float** result_aux = (float**)volk_gnsssdr_malloc(sizeof(float*) * num_out_vectors, volk_gnsssdr_get_alignment());
// for (n = 0; n < num_out_vectors; n++)
// {
// result_aux[n] = (float*)volk_gnsssdr_malloc(sizeof(float) * num_points, volk_gnsssdr_get_alignment());
// }
//
// volk_gnsssdr_32f_xn_resampler_32f_xn_neon(result_aux, local_code, rem_code_phase_chips, code_phase_step_chips, shifts_chips, code_length_chips, num_out_vectors, num_points);
//
// memcpy((float*)result, (float*)result_aux[0], sizeof(float) * num_points);
//
// for (n = 0; n < num_out_vectors; n++)
// {
// volk_gnsssdr_free(result_aux[n]);
// }
// volk_gnsssdr_free(result_aux);
//}
//#endif
#endif // INCLUDED_volk_gnsssdr_32f_high_dynamics_resamplerpuppet_32f_H #endif // INCLUDED_volk_gnsssdr_32f_high_dynamics_resamplerpuppet_32f_H

11
src/algorithms/libs/volk_gnsssdr_module/volk_gnsssdr/kernels/volk_gnsssdr/volk_gnsssdr_32f_sincos_32fc.h
View File

@ -52,6 +52,8 @@
* \b Outputs * \b Outputs
* \li out: Vector of the form lv_32fc_t out[n] = lv_cmake(cos(in[n]), sin(in[n])) * \li out: Vector of the form lv_32fc_t out[n] = lv_cmake(cos(in[n]), sin(in[n]))
* *
* Adapted from http://gruntthepeon.free.fr/ssemath/sse_mathfun.h, original code from Julien Pommier
* Based on algorithms from the cephes library http://www.netlib.org/cephes/
*/ */
#ifndef INCLUDED_volk_gnsssdr_32f_sincos_32fc_H #ifndef INCLUDED_volk_gnsssdr_32f_sincos_32fc_H
@ -251,8 +253,7 @@ static inline void volk_gnsssdr_32f_sincos_32fc_a_sse4_1(lv_32fc_t* out, const f
#ifdef LV_HAVE_SSE2 #ifdef LV_HAVE_SSE2
#include <emmintrin.h> #include <emmintrin.h>
/* Adapted from http://gruntthepeon.free.fr/ssemath/sse_mathfun.h, original code from Julien Pommier */
/* Based on algorithms from the cephes library http://www.netlib.org/cephes/ */
static inline void volk_gnsssdr_32f_sincos_32fc_a_sse2(lv_32fc_t* out, const float* in, unsigned int num_points) static inline void volk_gnsssdr_32f_sincos_32fc_a_sse2(lv_32fc_t* out, const float* in, unsigned int num_points)
{ {
lv_32fc_t* bPtr = out; lv_32fc_t* bPtr = out;
@ -421,8 +422,7 @@ static inline void volk_gnsssdr_32f_sincos_32fc_a_sse2(lv_32fc_t* out, const flo
#ifdef LV_HAVE_SSE2 #ifdef LV_HAVE_SSE2
#include <emmintrin.h> #include <emmintrin.h>
/* Adapted from http://gruntthepeon.free.fr/ssemath/sse_mathfun.h, original code from Julien Pommier */
/* Based on algorithms from the cephes library http://www.netlib.org/cephes/ */
static inline void volk_gnsssdr_32f_sincos_32fc_u_sse2(lv_32fc_t* out, const float* in, unsigned int num_points) static inline void volk_gnsssdr_32f_sincos_32fc_u_sse2(lv_32fc_t* out, const float* in, unsigned int num_points)
{ {
lv_32fc_t* bPtr = out; lv_32fc_t* bPtr = out;
@ -644,8 +644,7 @@ static inline void volk_gnsssdr_32f_sincos_32fc_generic_fxpt(lv_32fc_t* out, con
#ifdef LV_HAVE_NEONV7 #ifdef LV_HAVE_NEONV7
#include <arm_neon.h> #include <arm_neon.h>
/* Adapted from http://gruntthepeon.free.fr/ssemath/neon_mathfun.h, original code from Julien Pommier */
/* Based on algorithms from the cephes library http://www.netlib.org/cephes/ */
static inline void volk_gnsssdr_32f_sincos_32fc_neon(lv_32fc_t* out, const float* in, unsigned int num_points) static inline void volk_gnsssdr_32f_sincos_32fc_neon(lv_32fc_t* out, const float* in, unsigned int num_points)
{ {
lv_32fc_t* bPtr = out; lv_32fc_t* bPtr = out;

80
src/algorithms/libs/volk_gnsssdr_module/volk_gnsssdr/kernels/volk_gnsssdr/volk_gnsssdr_8ic_magnitude_squared_8i.h
View File

@ -114,46 +114,6 @@ static inline void volk_gnsssdr_8ic_magnitude_squared_8i_u_sse3(char* magnitudeV
} }
#endif /* LV_HAVE_SSSE3 */ #endif /* LV_HAVE_SSSE3 */
//#ifdef LV_HAVE_SSE
//#include <xmmintrin.h>
//
//static inline void volk_gnsssdr_8ic_magnitude_squared_8i_u_sse(float* magnitudeVector, const lv_32fc_t* complexVector, unsigned int num_points){
// unsigned int number = 0;
// const unsigned int quarterPoints = num_points / 4;
//
// const float* complexVectorPtr = (float*)complexVector;
// float* magnitudeVectorPtr = magnitudeVector;
//
// __m128 cplxValue1, cplxValue2, iValue, qValue, result;
// for(;number < quarterPoints; number++){
// cplxValue1 = _mm_loadu_ps(complexVectorPtr);
// complexVectorPtr += 4;
//
// cplxValue2 = _mm_loadu_ps(complexVectorPtr);
// complexVectorPtr += 4;
//
// // Arrange in i1i2i3i4 format
// iValue = _mm_shuffle_ps(cplxValue1, cplxValue2, _MM_SHUFFLE(2,0,2,0));
// // Arrange in q1q2q3q4 format
// qValue = _mm_shuffle_ps(cplxValue1, cplxValue2, _MM_SHUFFLE(3,1,3,1));
//
// iValue = _mm_mul_ps(iValue, iValue); // Square the I values
// qValue = _mm_mul_ps(qValue, qValue); // Square the Q Values
//
// result = _mm_add_ps(iValue, qValue); // Add the I2 and Q2 values
//
// _mm_storeu_ps(magnitudeVectorPtr, result);
// magnitudeVectorPtr += 4;
// }
//
// number = quarterPoints * 4;
// for(; number < num_points; number++){
// float val1Real = *complexVectorPtr++;
// float val1Imag = *complexVectorPtr++;
// *magnitudeVectorPtr++ = (val1Real * val1Real) + (val1Imag * val1Imag);
// }
//}
//#endif /* LV_HAVE_SSE */
#ifdef LV_HAVE_GENERIC #ifdef LV_HAVE_GENERIC
@ -228,46 +188,6 @@ static inline void volk_gnsssdr_8ic_magnitude_squared_8i_a_sse3(char* magnitudeV
} }
#endif /* LV_HAVE_SSSE3 */ #endif /* LV_HAVE_SSSE3 */
//#ifdef LV_HAVE_SSE
//#include <xmmintrin.h>
//
//static inline void volk_gnsssdr_8ic_magnitude_squared_8i_a_sse(float* magnitudeVector, const lv_32fc_t* complexVector, unsigned int num_points){
// unsigned int number = 0;
// const unsigned int quarterPoints = num_points / 4;
//
// const float* complexVectorPtr = (float*)complexVector;
// float* magnitudeVectorPtr = magnitudeVector;
//
// __m128 cplxValue1, cplxValue2, iValue, qValue, result;
// for(;number < quarterPoints; number++){
// cplxValue1 = _mm_load_ps(complexVectorPtr);
// complexVectorPtr += 4;
//
// cplxValue2 = _mm_load_ps(complexVectorPtr);
// complexVectorPtr += 4;
//
// // Arrange in i1i2i3i4 format
// iValue = _mm_shuffle_ps(cplxValue1, cplxValue2, _MM_SHUFFLE(2,0,2,0));
// // Arrange in q1q2q3q4 format
// qValue = _mm_shuffle_ps(cplxValue1, cplxValue2, _MM_SHUFFLE(3,1,3,1));
//
// iValue = _mm_mul_ps(iValue, iValue); // Square the I values
// qValue = _mm_mul_ps(qValue, qValue); // Square the Q Values
//
// result = _mm_add_ps(iValue, qValue); // Add the I2 and Q2 values
//
// _mm_store_ps(magnitudeVectorPtr, result);
// magnitudeVectorPtr += 4;
// }
//
// number = quarterPoints * 4;
// for(; number < num_points; number++){
// float val1Real = *complexVectorPtr++;
// float val1Imag = *complexVectorPtr++;
// *magnitudeVectorPtr++ = (val1Real * val1Real) + (val1Imag * val1Imag);
// }
//}
//#endif /* LV_HAVE_SSE */
#ifdef LV_HAVE_ORC #ifdef LV_HAVE_ORC

17
src/algorithms/libs/volk_gnsssdr_module/volk_gnsssdr/kernels/volk_gnsssdr/volk_gnsssdr_s32f_sincos_32fc.h
View File

@ -56,6 +56,8 @@
* \li out: Vector of the form lv_32fc_t out[n] = lv_cmake(cos(in[n]), sin(in[n])) * \li out: Vector of the form lv_32fc_t out[n] = lv_cmake(cos(in[n]), sin(in[n]))
* \li phase: Pointer to a float containing the final phase, in radians. * \li phase: Pointer to a float containing the final phase, in radians.
* *
* Adapted from http://gruntthepeon.free.fr/ssemath/sse_mathfun.h, original code from Julien Pommier
* Based on algorithms from the cephes library http://www.netlib.org/cephes/
*/ */
@ -69,8 +71,7 @@
#ifdef LV_HAVE_SSE2 #ifdef LV_HAVE_SSE2
#include <emmintrin.h> #include <emmintrin.h>
/* Adapted from http://gruntthepeon.free.fr/ssemath/sse_mathfun.h, original code from Julien Pommier */
/* Based on algorithms from the cephes library http://www.netlib.org/cephes/ */
static inline void volk_gnsssdr_s32f_sincos_32fc_a_sse2(lv_32fc_t *out, const float phase_inc, float *phase, unsigned int num_points) static inline void volk_gnsssdr_s32f_sincos_32fc_a_sse2(lv_32fc_t *out, const float phase_inc, float *phase, unsigned int num_points)
{ {
lv_32fc_t *bPtr = out; lv_32fc_t *bPtr = out;
@ -225,8 +226,7 @@ static inline void volk_gnsssdr_s32f_sincos_32fc_a_sse2(lv_32fc_t *out, const fl
#ifdef LV_HAVE_SSE2 #ifdef LV_HAVE_SSE2
#include <emmintrin.h> #include <emmintrin.h>
/* Adapted from http://gruntthepeon.free.fr/ssemath/sse_mathfun.h, original code from Julien Pommier */
/* Based on algorithms from the cephes library http://www.netlib.org/cephes/ */
static inline void volk_gnsssdr_s32f_sincos_32fc_u_sse2(lv_32fc_t *out, const float phase_inc, float *phase, unsigned int num_points) static inline void volk_gnsssdr_s32f_sincos_32fc_u_sse2(lv_32fc_t *out, const float phase_inc, float *phase, unsigned int num_points)
{ {
lv_32fc_t *bPtr = out; lv_32fc_t *bPtr = out;
@ -459,8 +459,7 @@ static inline void volk_gnsssdr_s32f_sincos_32fc_generic_fxpt(lv_32fc_t *out, co
#ifdef LV_HAVE_AVX2 #ifdef LV_HAVE_AVX2
#include <immintrin.h> #include <immintrin.h>
/* Based on algorithms from the cephes library http://www.netlib.org/cephes/
* Adapted to AVX2 by Carles Fernandez, based on original SSE2 code by Julien Pommier*/
static inline void volk_gnsssdr_s32f_sincos_32fc_a_avx2(lv_32fc_t *out, const float phase_inc, float *phase, unsigned int num_points) static inline void volk_gnsssdr_s32f_sincos_32fc_a_avx2(lv_32fc_t *out, const float phase_inc, float *phase, unsigned int num_points)
{ {
lv_32fc_t *bPtr = out; lv_32fc_t *bPtr = out;
@ -647,8 +646,7 @@ static inline void volk_gnsssdr_s32f_sincos_32fc_a_avx2(lv_32fc_t *out, const fl
#ifdef LV_HAVE_AVX2 #ifdef LV_HAVE_AVX2
#include <immintrin.h> #include <immintrin.h>
/* Based on algorithms from the cephes library http://www.netlib.org/cephes/
* Adapted to AVX2 by Carles Fernandez, based on original SSE2 code by Julien Pommier*/
static inline void volk_gnsssdr_s32f_sincos_32fc_u_avx2(lv_32fc_t *out, const float phase_inc, float *phase, unsigned int num_points) static inline void volk_gnsssdr_s32f_sincos_32fc_u_avx2(lv_32fc_t *out, const float phase_inc, float *phase, unsigned int num_points)
{ {
lv_32fc_t *bPtr = out; lv_32fc_t *bPtr = out;
@ -835,8 +833,7 @@ static inline void volk_gnsssdr_s32f_sincos_32fc_u_avx2(lv_32fc_t *out, const fl
#ifdef LV_HAVE_NEONV7 #ifdef LV_HAVE_NEONV7
#include <arm_neon.h> #include <arm_neon.h>
/* Adapted from http://gruntthepeon.free.fr/ssemath/neon_mathfun.h, original code from Julien Pommier */
/* Based on algorithms from the cephes library http://www.netlib.org/cephes/ */
static inline void volk_gnsssdr_s32f_sincos_32fc_neon(lv_32fc_t *out, const float phase_inc, float *phase, unsigned int num_points) static inline void volk_gnsssdr_s32f_sincos_32fc_neon(lv_32fc_t *out, const float phase_inc, float *phase, unsigned int num_points)
{ {
lv_32fc_t *bPtr = out; lv_32fc_t *bPtr = out;

5
src/core/libs/supl/asn-rrlp/INTEGER.c
View File

@ -7,6 +7,7 @@
#include <INTEGER.h> #include <INTEGER.h>
#include <asn_codecs_prim.h> /* Encoder and decoder of a primitive type */ #include <asn_codecs_prim.h> /* Encoder and decoder of a primitive type */
#include <errno.h> #include <errno.h>
#include <inttypes.h>
/* /*
* INTEGER basic type description. * INTEGER basic type description.
@ -146,7 +147,7 @@ INTEGER__dump(asn_TYPE_descriptor_t *td, const INTEGER_t *st, asn_app_consume_by
scr = (char *)alloca(scrsize); scr = (char *)alloca(scrsize);
if(plainOrXER == 0) if(plainOrXER == 0)
ret = snprintf(scr, scrsize, ret = snprintf(scr, scrsize,
"%lld (%s)", accum, el->enum_name); "%+"PRId64"(%s)", accum, el->enum_name);
else else
ret = snprintf(scr, scrsize, ret = snprintf(scr, scrsize,
"<%s/>", el->enum_name); "<%s/>", el->enum_name);
@ -160,7 +161,7 @@ INTEGER__dump(asn_TYPE_descriptor_t *td, const INTEGER_t *st, asn_app_consume_by
scr = scratch; scr = scratch;
ret = snprintf(scr, scrsize, ret = snprintf(scr, scrsize,
(specs && specs->field_unsigned) (specs && specs->field_unsigned)
?"%llu":"%lld", accum); ?"%"PRIu64:"%+"PRId64, accum);
} }
assert(ret > 0 && (size_t)ret < scrsize); assert(ret > 0 && (size_t)ret < scrsize);
return (cb(scr, ret, app_key) < 0) ? -1 : ret; return (cb(scr, ret, app_key) < 0) ? -1 : ret;

5
src/core/libs/supl/asn-supl/INTEGER.c
View File

@ -7,6 +7,7 @@
#include <INTEGER.h> #include <INTEGER.h>
#include <asn_codecs_prim.h> /* Encoder and decoder of a primitive type */ #include <asn_codecs_prim.h> /* Encoder and decoder of a primitive type */
#include <errno.h> #include <errno.h>
#include <inttypes.h>
/* /*
* INTEGER basic type description. * INTEGER basic type description.
@ -146,7 +147,7 @@ INTEGER__dump(asn_TYPE_descriptor_t *td, const INTEGER_t *st, asn_app_consume_by
scr = (char *)alloca(scrsize); scr = (char *)alloca(scrsize);
if(plainOrXER == 0) if(plainOrXER == 0)
ret = snprintf(scr, scrsize, ret = snprintf(scr, scrsize,
"%lld (%s)", accum, el->enum_name); "%+"PRId64"(%s)", accum, el->enum_name);
else else
ret = snprintf(scr, scrsize, ret = snprintf(scr, scrsize,
"<%s/>", el->enum_name); "<%s/>", el->enum_name);
@ -160,7 +161,7 @@ INTEGER__dump(asn_TYPE_descriptor_t *td, const INTEGER_t *st, asn_app_consume_by
scr = scratch; scr = scratch;
ret = snprintf(scr, scrsize, ret = snprintf(scr, scrsize,
(specs && specs->field_unsigned) (specs && specs->field_unsigned)
?"%llu":"%lld", accum); ?"%"PRIu64:"%+"PRId64, accum);
} }
assert(ret > 0 && (size_t)ret < scrsize); assert(ret > 0 && (size_t)ret < scrsize);
return (cb(scr, ret, app_key) < 0) ? -1 : ret; return (cb(scr, ret, app_key) < 0) ? -1 : ret;