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Add some MIPS features

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This commit is contained in:
Carles Fernandez 2022-07-16 10:01:59 +02:00
parent 931cc05c65
commit bbe2a193f6
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GPG Key ID: 4C583C52B0C3877D
4 changed files with 74 additions and 9 deletions
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14
src/algorithms/libs/volk_gnsssdr_module/volk_gnsssdr/cpu_features/include/cpuinfo_mips.h
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@ -16,6 +16,15 @@ typedef struct
int eva : 1; // Enhanced Virtual Addressing
// https://www.mips.com/products/architectures/mips64/
int r6 : 1; // True if is release 6 of the processor.
int mips16 : 1; // Compressed instructions
int mdmx : 1; // MIPS Digital Media Extension
int mips3d : 1; // 3D graphics acceleration
// MIPS(r) Architecture for Programmers, Volume IV-c
int smart : 1; // Smart-card cryptography
// MIPS(r) Architecture for Programmers, Volume IV-d
int dsp : 1; // Digital Signal Processing
// MIPS(r) Architecture for Programmers, Volume IV-e
// https://www.mips.com/products/architectures/ase/dsp/
// Make sure to update MipsFeaturesEnum below if you add a field here.
} MipsFeatures;
@ -35,6 +44,11 @@ typedef enum
MIPS_MSA,
MIPS_EVA,
MIPS_R6,
MIPS_MIPS16,
MIPS_MDMX,
MIPS_MIPS3D,
MIPS_SMART,
MIPS_DSP,
MIPS_LAST_,
} MipsFeaturesEnum;

7
src/algorithms/libs/volk_gnsssdr_module/volk_gnsssdr/cpu_features/include/internal/hwcaps.h
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@ -105,6 +105,13 @@ CPU_FEATURES_START_CPP_NAMESPACE
#define MIPS_HWCAP_R6 (1UL << 0)
#define MIPS_HWCAP_MSA (1UL << 1)
#define MIPS_HWCAP_CRC32 (1UL << 2)
#define MIPS_HWCAP_MIPS16 (1UL << 3)
#define MIPS_HWCAP_MDMX (1UL << 4)
#define MIPS_HWCAP_MIPS3D (1UL << 5)
#define MIPS_HWCAP_SMARTMIPS (1UL << 6)
#define MIPS_HWCAP_DSP (1UL << 7)
#define MIPS_HWCAP_DSP2 (1UL << 8)
#define MIPS_HWCAP_DSP3 (1UL << 9)
// http://elixir.free-electrons.com/linux/latest/source/arch/powerpc/include/uapi/asm/cputable.h
#ifndef _UAPI__ASM_POWERPC_CPUTABLE_H

7
src/algorithms/libs/volk_gnsssdr_module/volk_gnsssdr/cpu_features/src/impl_mips_linux_or_android.c
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@ -14,7 +14,12 @@
#define INTROSPECTION_TABLE \
LINE(MIPS_MSA, msa, "msa", MIPS_HWCAP_MSA, 0) \
LINE(MIPS_EVA, eva, "eva", 0, 0) \
LINE(MIPS_R6, r6, "r6", MIPS_HWCAP_R6, 0)
LINE(MIPS_R6, r6, "r6", MIPS_HWCAP_R6, 0) \
LINE(MIPS_MIPS16, mips16, "mips16", MIPS_HWCAP_MIPS16, 0) \
LINE(MIPS_MDMX, mdmx, "mdmx", MIPS_HWCAP_MDMX, 0) \
LINE(MIPS_MIPS3D, mips3d, "mips3d", MIPS_HWCAP_MIPS3D, 0) \
LINE(MIPS_SMART, smart, "smartmips", MIPS_HWCAP_SMARTMIPS, 0) \
LINE(MIPS_DSP, dsp, "dsp", MIPS_HWCAP_DSP, 0)
#define INTROSPECTION_PREFIX Mips
#define INTROSPECTION_ENUM_PREFIX MIPS
#include "define_introspection_and_hwcaps.inl"

39
src/algorithms/libs/volk_gnsssdr_module/volk_gnsssdr/cpu_features/test/cpuinfo_mips_test.cc
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@ -60,6 +60,12 @@ VPE : 0
const auto info = GetMipsInfo();
EXPECT_FALSE(info.features.msa);
EXPECT_TRUE(info.features.eva);
EXPECT_FALSE(info.features.r6);
EXPECT_TRUE(info.features.mips16);
EXPECT_FALSE(info.features.mdmx);
EXPECT_FALSE(info.features.mips3d);
EXPECT_FALSE(info.features.smart);
EXPECT_TRUE(info.features.dsp);
}
TEST(CpuinfoMipsTest, AR7161)
@ -87,6 +93,7 @@ VCEI exceptions : not available
const auto info = GetMipsInfo();
EXPECT_FALSE(info.features.msa);
EXPECT_FALSE(info.features.eva);
EXPECT_TRUE(info.features.mips16);
}
TEST(CpuinfoMipsTest, Goldfish)
@ -115,5 +122,37 @@ VCEI exceptions : not available
EXPECT_FALSE(info.features.eva);
}
TEST(CpuinfoMipsTest, BCM1250)
{
ResetHwcaps();
auto& fs = GetEmptyFilesystem();
fs.CreateFile("/proc/cpuinfo", R"(system type : SiByte BCM91250A (SWARM)
processor : 0
cpu model : SiByte SB1 V0.2 FPU V0.2
BogoMIPS : 532.48
wait instruction : no
microsecond timers : yes
tlb_entries : 64
extra interrupt vector : yes
hardware watchpoint : yes, count: 1, address/irw mask: [0x0ff8]
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
ASEs implemented : mdmx mips3d
shadow register sets : 1
kscratch registers : 0
package : 0
core : 0
VCED exceptions : not available
VCEI exceptions : not available
)");
const auto info = GetMipsInfo();
EXPECT_FALSE(info.features.msa);
EXPECT_FALSE(info.features.eva);
EXPECT_FALSE(info.features.mips16);
EXPECT_TRUE(info.features.mdmx);
EXPECT_TRUE(info.features.mips3d);
EXPECT_FALSE(info.features.smart);
EXPECT_FALSE(info.features.dsp);
}
} // namespace
} // namespace cpu_features