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https://github.com/gnss-sdr/gnss-sdr
synced 2024-12-15 12:40:35 +00:00
implemented 64-bit global sample counter
started programming the FPGA tracking unit tests
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@ -223,7 +223,7 @@ void pcps_acquisition_fpga::set_active(bool active)
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// no CFAR algorithm in the FPGA
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<< ", use_CFAR_algorithm_flag: false";
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unsigned int initial_sample;
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unsigned long int initial_sample;
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float input_power_all = 0.0;
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float input_power_computed = 0.0;
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@ -328,7 +328,7 @@ void pcps_acquisition_fpga::set_active(bool active)
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printf("##### d_test_statistics = %f\n", d_test_statistics);
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printf("##### debug_d_max_absolute =%f\n",debug_d_max_absolute);
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printf("##### debug_d_input_power_absolute =%f\n",debug_d_input_power_absolute);
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printf("##### initial_sample = %d\n",initial_sample);
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printf("##### initial_sample = %lu\n",initial_sample);
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printf("##### debug_doppler_index = %d\n",debug_doppler_index);
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send_positive_acquisition();
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d_state = 0; // Positive acquisition
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@ -369,13 +369,20 @@ void fpga_acquisition::set_phase_step(unsigned int doppler_index)
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void fpga_acquisition::read_acquisition_results(uint32_t *max_index,
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float *max_magnitude, unsigned *initial_sample, float *power_sum, unsigned *doppler_index)
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float *max_magnitude, unsigned long int *initial_sample, float *power_sum, unsigned *doppler_index)
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{
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unsigned long int initial_sample_tmp;
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unsigned readval = 0;
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unsigned long int readval_long = 0;
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readval = d_map_base[1];
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*initial_sample = readval;
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initial_sample_tmp = readval;
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//*initial_sample = readval;
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//printf("read initial sample dmap 1 = %d\n", readval);
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readval = d_map_base[2];
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readval_long = d_map_base[2];
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initial_sample_tmp = initial_sample_tmp + (readval_long * (2^32));
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*initial_sample = initial_sample_tmp;
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readval = d_map_base[6];
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*max_magnitude = static_cast<float>(readval);
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//printf("read max_magnitude dmap 2 = %d\n", readval);
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readval = d_map_base[4];
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@ -61,7 +61,7 @@ public:
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void run_acquisition(void);
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void set_phase_step(unsigned int doppler_index);
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void read_acquisition_results(uint32_t *max_index, float *max_magnitude,
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unsigned *initial_sample, float *power_sum, unsigned *doppler_index);
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unsigned long int *initial_sample, float *power_sum, unsigned *doppler_index);
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void block_samples();
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void unblock_samples();
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@ -1251,14 +1251,14 @@ int dll_pll_veml_tracking_fpga::general_work (int noutput_items __attribute__((u
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{
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d_pull_in = 0;
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multicorrelator_fpga->lock_channel();
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unsigned counter_value = multicorrelator_fpga->read_sample_counter();
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unsigned long int counter_value = multicorrelator_fpga->read_sample_counter();
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//printf("333333 counter_value = %d\n", counter_value);
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//printf("333333 current_synchro_data.Acq_samplestamp_samples = %d\n", current_synchro_data.Acq_samplestamp_samples);
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//printf("333333 current_synchro_data.Acq_delay_samples = %f\n", current_synchro_data.Acq_delay_samples);
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//printf("333333 d_correlation_length_samples = %d\n", d_correlation_length_samples);
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unsigned num_frames = ceil((counter_value - current_synchro_data.Acq_samplestamp_samples - current_synchro_data.Acq_delay_samples)/d_correlation_length_samples);
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//printf("333333 num_frames = %d\n", num_frames);
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unsigned absolute_samples_offset = current_synchro_data.Acq_delay_samples + current_synchro_data.Acq_samplestamp_samples + num_frames*d_correlation_length_samples;
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unsigned long int absolute_samples_offset = current_synchro_data.Acq_delay_samples + current_synchro_data.Acq_samplestamp_samples + num_frames*d_correlation_length_samples;
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//printf("333333 absolute_samples_offset = %d\n", absolute_samples_offset);
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multicorrelator_fpga->set_initial_sample(absolute_samples_offset);
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d_absolute_samples_offset = absolute_samples_offset;
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@ -84,16 +84,22 @@
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#define LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY 0x0C000000
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#define TEST_REGISTER_TRACK_WRITEVAL 0x55AA
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int fpga_multicorrelator_8sc::read_sample_counter()
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unsigned long int fpga_multicorrelator_8sc::read_sample_counter()
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{
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return d_map_base[d_SAMPLE_COUNTER_REG_ADDR];
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unsigned long int sample_counter_tmp, sample_counter_msw_tmp;
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sample_counter_tmp = d_map_base[d_SAMPLE_COUNTER_REG_ADDR_LSW];
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sample_counter_msw_tmp = d_map_base[d_SAMPLE_COUNTER_REG_ADDR_MSW];
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sample_counter_tmp = sample_counter_tmp + (sample_counter_msw_tmp * (2^32));
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//return d_map_base[d_SAMPLE_COUNTER_REG_ADDR];
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return sample_counter_tmp;
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}
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void fpga_multicorrelator_8sc::set_initial_sample(int samples_offset)
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void fpga_multicorrelator_8sc::set_initial_sample(unsigned long int samples_offset)
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{
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d_initial_sample_counter = samples_offset;
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//printf("www writing d map base %d = d_initial_sample_counter = %d\n", d_INITIAL_COUNTER_VALUE_REG_ADDR, d_initial_sample_counter);
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d_map_base[d_INITIAL_COUNTER_VALUE_REG_ADDR] = d_initial_sample_counter;
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d_map_base[d_INITIAL_COUNTER_VALUE_REG_ADDR_LSW] = (d_initial_sample_counter & 0xFFFFFFFF);
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d_map_base[d_INITIAL_COUNTER_VALUE_REG_ADDR_MSW] = (d_initial_sample_counter >> 32) & 0xFFFFFFFF;
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}
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//void fpga_multicorrelator_8sc::set_local_code_and_taps(int code_length_chips,
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@ -228,7 +234,8 @@ fpga_multicorrelator_8sc::fpga_multicorrelator_8sc(int n_correlators,
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d_PHASE_STEP_RAD_REG_ADDR = 16;
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d_PROG_MEMS_ADDR = 17;
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d_DROP_SAMPLES_REG_ADDR = 18;
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d_INITIAL_COUNTER_VALUE_REG_ADDR = 19;
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d_INITIAL_COUNTER_VALUE_REG_ADDR_LSW = 19;
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d_INITIAL_COUNTER_VALUE_REG_ADDR_MSW = 20;
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d_START_FLAG_ADDR = 30;
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// }
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@ -247,16 +254,16 @@ fpga_multicorrelator_8sc::fpga_multicorrelator_8sc(int n_correlators,
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// }
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// result 2's complement saturation value
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if (d_multicorr_type == 0)
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{
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// multicorrelator with 3 correlators (16 registers only)
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d_result_SAT_value = 1048576; // 21 bits 2's complement -> 2^20
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}
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else
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{
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// other types of multicorrelators (32 registers)
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d_result_SAT_value = 4194304; // 23 bits 2's complement -> 2^22
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}
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// if (d_multicorr_type == 0)
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// {
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// // multicorrelator with 3 correlators (16 registers only)
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// d_result_SAT_value = 1048576; // 21 bits 2's complement -> 2^20
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// }
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// else
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// {
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// // other types of multicorrelators (32 registers)
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// d_result_SAT_value = 4194304; // 23 bits 2's complement -> 2^22
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// }
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// read only registers
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d_RESULT_REG_REAL_BASE_ADDR = 1;
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@ -275,7 +282,8 @@ fpga_multicorrelator_8sc::fpga_multicorrelator_8sc(int n_correlators,
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d_RESULT_REG_IMAG_BASE_ADDR = 7;
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d_RESULT_REG_DATA_REAL_BASE_ADDR = 6; // no pilot tracking
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d_RESULT_REG_DATA_IMAG_BASE_ADDR = 12;
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d_SAMPLE_COUNTER_REG_ADDR = 13;
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d_SAMPLE_COUNTER_REG_ADDR_LSW = 13;
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d_SAMPLE_COUNTER_REG_ADDR_MSW = 14;
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// }
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@ -68,8 +68,8 @@ public:
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float rem_code_phase_chips, float code_phase_step_chips,
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int signal_length_samples);bool free();
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void set_channel(unsigned int channel);
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void set_initial_sample(int samples_offset);
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int read_sample_counter();
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void set_initial_sample(unsigned long int samples_offset);
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unsigned long int read_sample_counter();
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void lock_channel(void);
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void unlock_channel(void);
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//void read_sample_counters(int *sample_counter, int *secondary_sample_counter, int *counter_corr_0_in, int *counter_corr_0_out); // debug
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@ -103,7 +103,7 @@ private:
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unsigned d_code_phase_step_chips_num;
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int d_rem_carr_phase_rad_int;
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int d_phase_step_rad_int;
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unsigned d_initial_sample_counter;
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unsigned long int d_initial_sample_counter;
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// driver
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std::string d_device_name;
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@ -131,7 +131,8 @@ private:
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unsigned int d_PHASE_STEP_RAD_REG_ADDR;
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unsigned int d_PROG_MEMS_ADDR;
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unsigned int d_DROP_SAMPLES_REG_ADDR;
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unsigned int d_INITIAL_COUNTER_VALUE_REG_ADDR;
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unsigned int d_INITIAL_COUNTER_VALUE_REG_ADDR_LSW;
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unsigned int d_INITIAL_COUNTER_VALUE_REG_ADDR_MSW;
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unsigned int d_START_FLAG_ADDR;
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// read-write regs
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unsigned int d_TEST_REG_ADDR;
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@ -140,7 +141,8 @@ private:
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unsigned int d_RESULT_REG_IMAG_BASE_ADDR;
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unsigned int d_RESULT_REG_DATA_REAL_BASE_ADDR;
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unsigned int d_RESULT_REG_DATA_IMAG_BASE_ADDR;
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unsigned int d_SAMPLE_COUNTER_REG_ADDR;
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unsigned int d_SAMPLE_COUNTER_REG_ADDR_LSW;
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unsigned int d_SAMPLE_COUNTER_REG_ADDR_MSW;
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// private functions
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unsigned fpga_acquisition_test_register(unsigned writeval);
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@ -149,6 +149,9 @@ DECLARE_string(log_dir);
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#include "unit-tests/signal-processing-blocks/tracking/gps_l2_m_dll_pll_tracking_test.cc"
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#include "unit-tests/signal-processing-blocks/tracking/gps_l1_ca_dll_pll_tracking_test.cc"
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#include "unit-tests/signal-processing-blocks/tracking/tracking_pull-in_test.cc"
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#if ENABLE_FPGA
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#include "unit-tests/signal-processing-blocks/tracking/tracking_pull-in_test_fpga.cc"
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#endif
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#include "unit-tests/signal-processing-blocks/telemetry_decoder/gps_l1_ca_telemetry_decoder_test.cc"
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#include "unit-tests/signal-processing-blocks/observables/hybrid_observables_test.cc"
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#endif
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