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write the code phase rate and the nco phase rate parameters in the FPGA

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This commit is contained in:
Marc Majoral
2019-04-10 11:31:34 +02:00
parent 19184da0f9
commit 91f509abf9
3 changed files with 41 additions and 18 deletions
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7
src/algorithms/acquisition/libs/fpga_acquisition.cc
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@@ -53,6 +53,9 @@
#define MEM_LOCAL_CODE_WR_ENABLE 0x0C000000 // command to enable the ENA and WR pins of the internal memory of the multicorrelator
#define POW_2_2 4 // 2^2 (used for the conversion of floating point numbers to integers)
#define POW_2_31 2147483648 // 2^31 (used for the conversion of floating point numbers to integers)
#define ENABLE_INT_ON_RESET 2 // flag that causes the acquisition to trigger an interrupt when it is reset. It is used \
// to avoid a potential deadlock caused by the SW waiting for an interrupt from the FPGA when the \
// HW is reset
#define SELECT_LSBits 0x0000FFFF // Select the 10 LSbits out of a 20-bit word
#define SELECT_MSBbits 0xFFFF0000 // Select the 10 MSbits out of a 20-bit word
@@ -311,7 +314,9 @@ void Fpga_Acquisition::close_device()
void Fpga_Acquisition::reset_acquisition(void)
{
d_map_base[8] = RESET_ACQUISITION; // writing a 2 to d_map_base[8] resets the multicorrelator
d_map_base[8] = RESET_ACQUISITION; // writing a 2 to d_map_base[8] resets the acquisition. This causes a reset of all
// the FPGA HW modules including the multicorrelators
d_map_base[14] = ENABLE_INT_ON_RESET; // enable int on reset
}

45
src/algorithms/tracking/libs/fpga_multicorrelator.cc
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@@ -59,7 +59,8 @@
#define LOCAL_CODE_FPGA_CLEAR_ADDRESS_COUNTER 0x10000000
#define LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY 0x0C000000
#define TEST_REGISTER_TRACK_WRITEVAL 0x55AA
#define ENABLE_TRK_INT_ON_RESET 1 /* flag that causes the tracking HW accelerator to trigger an interrupt when it is reset. It is used \
to avoid a potential deadlock caused by the SW waiting for an interrupt from the FPGA when the HW is reset */
#ifndef TEMP_FAILURE_RETRY
#define TEMP_FAILURE_RETRY(exp) \
({ \
@@ -182,19 +183,21 @@ void Fpga_Multicorrelator_8sc::update_local_code()
void Fpga_Multicorrelator_8sc::Carrier_wipeoff_multicorrelator_resampler(
float rem_carrier_phase_in_rad,
float phase_step_rad,
float carrier_phase_rate_step_rad __attribute__((unused)),
float rem_code_phase_chips,
float code_phase_step_chips __attribute__((unused)),
float code_phase_rate_step_chips __attribute__((unused)),
int32_t signal_length_samples)
float rem_carrier_phase_in_rad, // nco phase initial position
float phase_step_rad, // nco phase step
float carrier_phase_rate_step_rad __attribute__((unused)), // nco phase step rate change
float rem_code_phase_chips, // code resampler initial position
float code_phase_step_chips __attribute__((unused)), // code resampler step
float code_phase_rate_step_chips __attribute__((unused)), // code resampler step rate
int32_t signal_length_samples) // number of samples
{
d_rem_code_phase_chips = rem_code_phase_chips;
d_rem_carrier_phase_in_rad = rem_carrier_phase_in_rad;
d_code_phase_step_chips = code_phase_step_chips;
d_phase_step_rad = phase_step_rad;
d_correlator_length_samples = signal_length_samples;
d_rem_carrier_phase_in_rad = rem_carrier_phase_in_rad; // nco phase initial position
d_phase_step_rad = phase_step_rad; // nco phase step
d_carrier_phase_rate_step_rad = carrier_phase_rate_step_rad; // nco phase step rate
d_rem_code_phase_chips = rem_code_phase_chips; // code resampler initial position
d_code_phase_step_chips = code_phase_step_chips; // code resampler step
d_code_phase_rate_step_chips = code_phase_rate_step_chips; // code resampler step rate
d_correlator_length_samples = signal_length_samples; // number of samples
Fpga_Multicorrelator_8sc::update_local_code();
Fpga_Multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga();
Fpga_Multicorrelator_8sc::fpga_configure_signal_parameters_in_fpga();
@@ -287,6 +290,8 @@ void Fpga_Multicorrelator_8sc::set_channel(uint32_t channel)
LOG(INFO) << "Test register sanity check success !";
}
d_map_base[INT_ON_RST_REG_ADDR] = ENABLE_TRK_INT_ON_RESET; // enable interrupts on reset to prevent deadlock
// enable interrupts
int32_t reenable = 1;
ssize_t nbytes = TEMP_FAILURE_RETRY(write(d_device_descriptor, reinterpret_cast<void *>(&reenable), sizeof(int32_t)));
@@ -396,6 +401,7 @@ void Fpga_Multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga(void)
float d_rem_carrier_phase_in_rad_temp;
d_code_phase_step_chips_num = static_cast<uint32_t>(roundf(MAX_CODE_RESAMPLER_COUNTER * d_code_phase_step_chips));
d_code_phase_rate_step_chips_num = static_cast<uint32_t>(roundf(MAX_CODE_RESAMPLER_COUNTER * d_code_phase_rate_step_chips));
if (d_rem_carrier_phase_in_rad > M_PI)
{
@@ -412,18 +418,23 @@ void Fpga_Multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga(void)
d_rem_carr_phase_rad_int = static_cast<int32_t>(roundf((d_rem_carrier_phase_in_rad_temp)*PHASE_CARR_MAX_div_PI));
d_phase_step_rad_int = static_cast<int32_t>(roundf((d_phase_step_rad)*PHASE_CARR_MAX_div_PI)); // the FPGA accepts a range for the phase step between -pi and +pi
d_carrier_phase_rate_step_rad_int = static_cast<int32_t>(roundf((d_carrier_phase_rate_step_rad)*PHASE_CARR_MAX_div_PI));
}
void Fpga_Multicorrelator_8sc::fpga_configure_signal_parameters_in_fpga(void)
{
d_map_base[CODE_PHASE_STEP_CHIPS_NUM_REG_ADDR] = d_code_phase_step_chips_num;
d_map_base[CODE_PHASE_STEP_CHIPS_NUM_REG_ADDR] = d_code_phase_step_chips_num; // code phase step
d_map_base[NSAMPLES_MINUS_1_REG_ADDR] = d_correlator_length_samples - 1;
d_map_base[CODE_PHASE_STEP_CHIPS_RATE] = d_code_phase_rate_step_chips_num; // code phase step rate
d_map_base[REM_CARR_PHASE_RAD_REG_ADDR] = d_rem_carr_phase_rad_int;
d_map_base[NSAMPLES_MINUS_1_REG_ADDR] = d_correlator_length_samples - 1; // number of samples
d_map_base[PHASE_STEP_RAD_REG_ADDR] = d_phase_step_rad_int;
d_map_base[REM_CARR_PHASE_RAD_REG_ADDR] = d_rem_carr_phase_rad_int; // initial nco phase
d_map_base[PHASE_STEP_RAD_REG_ADDR] = d_phase_step_rad_int; // nco phase step
d_map_base[PHASE_STEP_RATE_REG_ADDR] = d_carrier_phase_rate_step_rad_int; // nco phase step rate
}

7
src/algorithms/tracking/libs/fpga_multicorrelator.h
View File

@@ -54,7 +54,10 @@
#define DROP_SAMPLES_REG_ADDR 18
#define INITIAL_COUNTER_VALUE_REG_ADDR_LSW 19
#define INITIAL_COUNTER_VALUE_REG_ADDR_MSW 20
#define CODE_PHASE_STEP_CHIPS_RATE 21
#define PHASE_STEP_RATE_REG_ADDR 22
#define STOP_TRACKING_REG_ADDR 23
#define INT_ON_RST_REG_ADDR 24 // cause interrupt on reset to prevent deadlock
#define START_FLAG_ADDR 30
// read-write addresses
#define TEST_REG_ADDR 31
@@ -109,15 +112,19 @@ private:
uint32_t d_correlator_length_samples;
float d_rem_code_phase_chips;
float d_code_phase_step_chips;
float d_code_phase_rate_step_chips;
float d_rem_carrier_phase_in_rad;
float d_phase_step_rad;
float d_carrier_phase_rate_step_rad;
// configuration data computed in the format that the FPGA expects
uint32_t *d_initial_index;
uint32_t *d_initial_interp_counter;
uint32_t d_code_phase_step_chips_num;
uint32_t d_code_phase_rate_step_chips_num;
int32_t d_rem_carr_phase_rad_int;
int32_t d_phase_step_rad_int;
int32_t d_carrier_phase_rate_step_rad_int;
uint64_t d_initial_sample_counter;
// driver