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Code Issues Releases Wiki Activity

more code cleaning

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removed some non used variables
This commit is contained in:
Marc Majoral
2019-02-27 13:30:09 +01:00
parent 2b6e7749a8
commit 8d770d9be9
22 changed files with 370 additions and 2057 deletions
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2
src/algorithms/acquisition/adapters/galileo_e1_pcps_ambiguous_acquisition_fpga.h
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@@ -65,7 +65,7 @@ public:
}
/*!
* \brief Returns "Galileo_E1_PCPS_Ambiguous_Acquisition"
* \brief Returns "Galileo_E1_PCPS_Ambiguous_Acquisition_Fpga"
*/
inline std::string implementation() override
{

3
src/algorithms/acquisition/adapters/galileo_e5a_pcps_acquisition_fpga.h
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@@ -57,6 +57,9 @@ public:
return role_;
}
/*!
* \brief Returns "Galileo_E5a_Pcps_Acquisition_Fpga"
*/
inline std::string implementation() override
{
return "Galileo_E5a_Pcps_Acquisition_Fpga";

2
src/algorithms/acquisition/adapters/gps_l1_ca_pcps_acquisition_fpga.h
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@@ -65,7 +65,7 @@ public:
}
/*!
* \brief Returns "GPS_L1_CA_PCPS_Acquisition"
* \brief Returns "GPS_L1_CA_PCPS_Acquisition_Fpga"
*/
inline std::string implementation() override
{

4
src/algorithms/acquisition/adapters/gps_l5i_pcps_acquisition_fpga.h
View File

@@ -67,11 +67,11 @@ public:
}
/*!
* \brief Returns "GPS_L5i_PCPS_Acquisition"
* \brief Returns "GPS_L5i_PCPS_Acquisition_Fpga"
*/
inline std::string implementation() override
{
return "GPS_L5i_PCPS_Acquisition";
return "GPS_L5i_PCPS_Acquisition_Fpga";
}
inline size_t item_size() override

6
src/algorithms/acquisition/gnuradio_blocks/pcps_acquisition_fpga.cc
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@@ -40,8 +40,6 @@
#include <gnuradio/io_signature.h>
#include <utility>
#include <unistd.h> // for the usleep function only (debug)
#define AQ_DOWNSAMPLING_DELAY 40 // delay due to the downsampling filter in the acquisition
using google::LogMessage;
@@ -196,10 +194,6 @@ void pcps_acquisition_fpga::set_active(bool active)
<< ", use_CFAR_algorithm_flag: false";
uint64_t initial_sample;
float input_power_all = 0.0;
float input_power_computed = 0.0;
float temp_d_input_power;
acquisition_fpga->configure_acquisition();
acquisition_fpga->set_doppler_sweep(d_num_doppler_bins);

6
src/algorithms/acquisition/gnuradio_blocks/pcps_acquisition_fpga.h
View File

@@ -178,9 +178,7 @@ public:
*/
inline void set_threshold(float threshold)
{
// printf("acq set threshold start\n");
d_threshold = threshold;
// printf("acq set threshold end\n");
}
/*!
@@ -189,10 +187,8 @@ public:
*/
inline void set_doppler_max(uint32_t doppler_max)
{
// printf("acq set doppler max start\n");
acq_parameters.doppler_max = doppler_max;
acquisition_fpga->set_doppler_max(doppler_max);
// printf("acq set doppler max end\n");
}
/*!
@@ -201,10 +197,8 @@ public:
*/
inline void set_doppler_step(uint32_t doppler_step)
{
// printf("acq set doppler step start\n");
d_doppler_step = doppler_step;
acquisition_fpga->set_doppler_step(doppler_step);
// printf("acq set doppler step end\n");
}
/*!

6
src/algorithms/acquisition/libs/fpga_acquisition.cc
View File

@@ -212,8 +212,8 @@ void fpga_acquisition::run_acquisition(void)
nb = read(d_fd, &irq_count, sizeof(irq_count));
if (nb != sizeof(irq_count))
{
printf("acquisition module Read failed to retrieve 4 bytes!\n");
printf("acquisition module Interrupt number %d\n", irq_count);
std::cout << "acquisition module Read failed to retrieve 4 bytes!" << std::endl;
std::cout << "acquisition module Interrupt number " << irq_count << std::endl;
}
write(d_fd, reinterpret_cast<void *>(&disable_int), sizeof(int32_t));
@@ -359,7 +359,7 @@ void fpga_acquisition::close_device()
uint32_t *aux = const_cast<uint32_t *>(d_map_base);
if (munmap(static_cast<void *>(aux), PAGE_SIZE) == -1)
{
printf("Failed to unmap memory uio\n");
std::cout << "Failed to unmap memory uio" << std::endl;
}
close(d_fd);
}

1
src/algorithms/acquisition/libs/fpga_acquisition.h
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@@ -102,7 +102,6 @@ public:
void configure_acquisition(void);
//void configure_acquisition_debug(void);
void close_device();
void open_device();

26
src/algorithms/libs/gnss_sdr_fpga_sample_counter.cc
View File

@@ -53,10 +53,7 @@ gnss_sdr_fpga_sample_counter::gnss_sdr_fpga_sample_counter(
set_max_noutput_items(1);
interval_ms = _interval_ms;
fs = _fs;
//printf("CREATOR fs = %f\n", fs);
//printf("CREATOR interval_ms = %" PRIu32 "\n", interval_ms);
samples_per_output = std::round(fs * static_cast<double>(interval_ms) / 1e3);
//printf("CREATOR samples_per_output = %" PRIu32 "\n", samples_per_output);
//todo: Load here the hardware counter register with this amount of samples. It should produce an
//interrupt every samples_per_output count.
//The hardware timer must keep always interrupting the PS. It must not wait for the interrupt to
@@ -122,7 +119,6 @@ int gnss_sdr_fpga_sample_counter::general_work(int noutput_items __attribute__((
uint32_t counter = wait_for_interrupt_and_read_counter();
uint64_t samples_passed = 2 * static_cast<uint64_t>(samples_per_output) - static_cast<uint64_t>(counter); // ellapsed samples
//printf("============================================ interrupter : samples_passed = %" PRIu64 "\n", samples_passed);
// Note: at this moment the sample counter is implemented as a sample counter that decreases to zero and then it is automatically
// reloaded again and keeps counter. It is done in this way to minimize the logic in the FPGA and maximize the FPGA clock performance
// (it takes less resources and latency in the FPGA to compare a number against a fixed value like zero than to compare it to a programmable
@@ -137,10 +133,6 @@ int gnss_sdr_fpga_sample_counter::general_work(int noutput_items __attribute__((
out[0].fs = fs;
if ((current_T_rx_ms % report_interval_ms) == 0)
{
//printf("time to print sample_counter = %" PRIu64 "\n", sample_counter);
//printf("time to print current Tx ms : %" PRIu64 "\n", current_T_rx_ms);
//printf("time to print report_interval_ms : %" PRIu32 "\n", report_interval_ms);
//printf("time to print %f\n", (current_T_rx_ms % report_interval_ms));
current_s++;
if ((current_s % 60) == 0)
{
@@ -217,15 +209,7 @@ uint32_t gnss_sdr_fpga_sample_counter::test_register(uint32_t writeval)
void gnss_sdr_fpga_sample_counter::configure_samples_per_output(uint32_t interval)
{
// note : the counter is a 48-bit value in the HW.
//printf("============================================ total counter - interrupted interval : %" PRIu32 "\n", interval);
//uint64_t temp_interval;
//temp_interval = (interval & static_cast<uint32_t>(0xFFFFFFFF));
//printf("LSW counter - interrupted interval : %" PRIu32 "\n", static_cast<uint32_t>(temp_interval));
//map_base[0] = static_cast<uint32_t>(temp_interval);
map_base[0] = interval - 1;
//temp_interval = (interval >> 32) & static_cast<uint32_t>(0xFFFFFFFF);
//printf("MSbits counter - interrupted interval : %" PRIu32 "\n", static_cast<uint32_t>(temp_interval));
//map_base[1] = static_cast<uint32_t>(temp_interval); // writing the most significant bits also enables the interrupts
}
void gnss_sdr_fpga_sample_counter::open_device()
@@ -262,13 +246,12 @@ void gnss_sdr_fpga_sample_counter::open_device()
void gnss_sdr_fpga_sample_counter::close_device()
{
//printf("=========================================== NOW closing device ...\n");
map_base[2] = 0; // disable the generation of the interrupt in the device
auto *aux = const_cast<uint32_t *>(map_base);
if (munmap(static_cast<void *>(aux), PAGE_SIZE) == -1)
{
printf("Failed to unmap memory uio\n");
std::cout << "Failed to unmap memory uio" << std::endl;
}
close(fd);
}
@@ -284,14 +267,11 @@ uint32_t gnss_sdr_fpga_sample_counter::wait_for_interrupt_and_read_counter()
write(fd, reinterpret_cast<void *>(&reenable), sizeof(int32_t));
// wait for interrupt
//printf("============================================ interrupter : going to wait for interupt\n");
nb = read(fd, &irq_count, sizeof(irq_count));
//printf("============================================ interrupter : interrupt received\n");
//printf("interrupt received\n");
if (nb != sizeof(irq_count))
{
printf("acquisition module Read failed to retrieve 4 bytes!\n");
printf("acquisition module Interrupt number %d\n", irq_count);
std::cout << "fpga sample counter module read failed to retrieve 4 bytes!" << std::endl;
std::cout << "fpga sample counter module interrupt number " << irq_count << std::endl;
}
// it is a rising edge interrupt, the interrupt does not need to be acknowledged

2
src/algorithms/tracking/adapters/gps_l2_m_dll_pll_tracking_fpga.h
View File

@@ -63,7 +63,7 @@ public:
return role_;
}
//! Returns "GPS_L2_M_DLL_PLL_Tracking"
//! Returns "GPS_L2_M_DLL_PLL_Tracking_Fpga"
inline std::string implementation() override
{
return "GPS_L2_M_DLL_PLL_Tracking_Fpga";

2
src/algorithms/tracking/adapters/gps_l5_dll_pll_tracking_fpga.cc
View File

@@ -83,7 +83,6 @@ GpsL5DllPllTrackingFpga::GpsL5DllPllTrackingFpga(
trk_param_fpga.early_late_space_chips = early_late_space_chips;
int vector_length = std::round(static_cast<double>(fs_in) / (static_cast<double>(GPS_L5I_CODE_RATE_HZ) / static_cast<double>(GPS_L5I_CODE_LENGTH_CHIPS)));
trk_param_fpga.vector_length = vector_length;
printf("trk vector length = %d\n", vector_length);
int extend_correlation_symbols = configuration->property(role + ".extend_correlation_symbols", 1);
float early_late_space_narrow_chips = configuration->property(role + ".early_late_space_narrow_chips", 0.15);
trk_param_fpga.early_late_space_narrow_chips = early_late_space_narrow_chips;
@@ -152,7 +151,6 @@ GpsL5DllPllTrackingFpga::GpsL5DllPllTrackingFpga(
d_data_codes = static_cast<int *>(volk_gnsssdr_malloc((static_cast<unsigned int>(code_length_chips)) * NUM_PRNs * sizeof(int), volk_gnsssdr_get_alignment()));
}
//printf("start \n");
for (unsigned int PRN = 1; PRN <= NUM_PRNs; PRN++)
{
if (track_pilot)

183
src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.cc
View File

@@ -1,7 +1,7 @@
/*!
* \file dll_pll_veml_tracking_fpga.cc
* \brief Implementation of a code DLL + carrier PLL tracking block using an FPGA
* \author Marc Majoral, 2018. marc.majoral(at)cttc.es
* \author Marc Majoral, 2019. marc.majoral(at)cttc.es
* \author Antonio Ramos, 2018 antonio.ramosdet(at)gmail.com
* \author Javier Arribas, 2018. jarribas(at)cttc.es
*
@@ -12,7 +12,7 @@
*
* -------------------------------------------------------------------------
*
* Copyright (C) 2010-2018 (see AUTHORS file for a list of contributors)
* Copyright (C) 2010-2019 (see AUTHORS file for a list of contributors)
*
* GNSS-SDR is a software defined Global Navigation
* Satellite Systems receiver
@@ -63,30 +63,6 @@
#include <sstream>
#include <numeric>
//#include "GPS_L1_CA.h"
//#include "gps_sdr_signal_processing.h"
//#include "GPS_L2C.h"
//#include "GPS_L5.h"
//#include "Galileo_E1.h"
//#include "Galileo_E5a.h"
//#include "MATH_CONSTANTS.h"
//#include "control_message_factory.h"
//#include "gnss_sdr_create_directory.h"
//#include "gps_l2c_signal.h"
//#include "gps_l5_signal.h"
//#include "lock_detectors.h"
//#include "tracking_discriminators.h"
//#include <boost/filesystem/path.hpp>
//#include <glog/logging.h>
//#include <gnuradio/io_signature.h>
//#include <matio.h>
//#include <volk_gnsssdr/volk_gnsssdr.h>
//#include <algorithm>
//#include <cmath>
//#include <iostream>
//#include <sstream>
//#include <numeric>
using google::LogMessage;
dll_pll_veml_tracking_fpga_sptr dll_pll_veml_make_tracking_fpga(const Dll_Pll_Conf_Fpga &conf_)
@@ -139,8 +115,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
d_code_chip_rate = GPS_L1_CA_CODE_RATE_HZ;
d_symbols_per_bit = GPS_CA_TELEMETRY_SYMBOLS_PER_BIT;
d_correlation_length_ms = 1;
//d_code_samples_per_chip = 1;
//d_code_length_chips = static_cast<uint32_t>(GPS_L1_CA_CODE_LENGTH_CHIPS);
// GPS L1 C/A does not have pilot component nor secondary code
d_secondary = false;
trk_parameters.track_pilot = false;
@@ -175,10 +149,8 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
d_signal_carrier_freq = GPS_L2_FREQ_HZ;
d_code_period = GPS_L2_M_PERIOD;
d_code_chip_rate = GPS_L2_M_CODE_RATE_HZ;
//d_code_length_chips = static_cast<uint32_t>(GPS_L2_M_CODE_LENGTH_CHIPS);
d_symbols_per_bit = GPS_L2_SAMPLES_PER_SYMBOL;
d_correlation_length_ms = 20;
//d_code_samples_per_chip = 1;
// GPS L2 does not have pilot component nor secondary code
d_secondary = false;
trk_parameters.track_pilot = false;
@@ -191,8 +163,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
d_code_chip_rate = GPS_L5I_CODE_RATE_HZ;
d_symbols_per_bit = GPS_L5_SAMPLES_PER_SYMBOL;
d_correlation_length_ms = 1;
//d_code_samples_per_chip = 1;
//d_code_length_chips = static_cast<uint32_t>(GPS_L5i_CODE_LENGTH_CHIPS);
d_secondary = true;
if (trk_parameters.track_pilot)
{
@@ -218,8 +188,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
interchange_iq = false;
d_signal_carrier_freq = 0.0;
d_code_period = 0.0;
//d_code_length_chips = 0U;
//d_code_samples_per_chip = 0U;
d_symbols_per_bit = 0;
}
}
@@ -231,10 +199,8 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
d_signal_carrier_freq = GALILEO_E1_FREQ_HZ;
d_code_period = GALILEO_E1_CODE_PERIOD;
d_code_chip_rate = GALILEO_E1_CODE_CHIP_RATE_HZ;
//d_code_length_chips = static_cast<uint32_t >(Galileo_E1_B_CODE_LENGTH_CHIPS);
d_symbols_per_bit = 1;
d_correlation_length_ms = 4;
//d_code_samples_per_chip = 2; // CBOC disabled: 2 samples per chip. CBOC enabled: 12 samples per chip
d_veml = true;
if (trk_parameters.track_pilot)
{
@@ -257,8 +223,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
d_code_chip_rate = GALILEO_E5A_CODE_CHIP_RATE_HZ;
d_symbols_per_bit = 20;
d_correlation_length_ms = 1;
//d_code_samples_per_chip = 1;
//d_code_length_chips = static_cast<uint32_t>(Galileo_E5a_CODE_LENGTH_CHIPS);
if (trk_parameters.track_pilot)
{
@@ -271,10 +235,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
{
//Do not acquire secondary code in data component. It is done in telemetry decoder
d_secondary = false;
//=======
// d_secondary_code_length = static_cast<uint32_t>(GALILEO_E5A_I_SECONDARY_CODE_LENGTH);
// d_secondary_code_string = const_cast<std::string *>(&GALILEO_E5A_I_SECONDARY_CODE);
//>>>>>>> 4fe976ba016fa9c1c64ece88b26a9a93d93a84f4
signal_pretty_name = signal_pretty_name + "I";
interchange_iq = false;
}
@@ -288,8 +248,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
interchange_iq = false;
d_signal_carrier_freq = 0.0;
d_code_period = 0.0;
//d_code_length_chips = 0U;
//d_code_samples_per_chip = 0U;
d_symbols_per_bit = 0;
}
}
@@ -302,8 +260,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
interchange_iq = false;
d_signal_carrier_freq = 0.0;
d_code_period = 0.0;
//d_code_length_chips = 0U;
//d_code_samples_per_chip = 0U;
d_symbols_per_bit = 0;
}
T_chip_seconds = 0.0;
@@ -317,10 +273,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
d_code_loop_filter = Tracking_2nd_DLL_filter(static_cast<float>(d_code_period));
d_carrier_loop_filter = Tracking_2nd_PLL_filter(static_cast<float>(d_code_period));
// Initialization of local code replica
// Get space for a vector with the sinboc(1,1) replica sampled 2x/chip
//d_tracking_code = static_cast<float *>(volk_gnsssdr_malloc(2 * d_code_length_chips * sizeof(float), volk_gnsssdr_get_alignment()));
// correlator outputs (scalar)
if (d_veml)
{
// Very-Early, Early, Prompt, Late, Very-Late
@@ -363,7 +315,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
d_prompt_data_shift = &d_local_code_shift_chips[1];
}
//multicorrelator_cpu.init(2 * trk_parameters.vector_length, d_n_correlator_taps);
if (trk_parameters.extend_correlation_symbols > 1)
{
@@ -375,21 +326,7 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
trk_parameters.extend_correlation_symbols = 1;
}
// Enable Data component prompt correlator (slave to Pilot prompt) if tracking uses Pilot signal
if (trk_parameters.track_pilot)
{
// Extra correlator for the data component
//correlator_data_cpu.init(2 * trk_parameters.vector_length, 1);
//correlator_data_cpu.set_high_dynamics_resampler(trk_parameters.high_dyn);
//d_data_code = static_cast<float *>(volk_gnsssdr_malloc(2 * d_code_length_chips * sizeof(float), volk_gnsssdr_get_alignment()));
}
else
{
//d_data_code = nullptr;
}
// --- Initializations ---
//multicorrelator_cpu.set_high_dynamics_resampler(trk_parameters.high_dyn);
// --- Initializations ---
// Initial code frequency basis of NCO
d_code_freq_chips = d_code_chip_rate;
// Residual code phase (in chips)
@@ -494,8 +431,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
void dll_pll_veml_tracking_fpga::start_tracking()
{
//gr::thread::scoped_lock l(d_setlock);
// correct the code phase according to the delay between acq and trk
d_acq_code_phase_samples = d_acquisition_gnss_synchro->Acq_delay_samples;
d_acq_carrier_doppler_hz = d_acquisition_gnss_synchro->Acq_doppler_hz;
@@ -510,64 +445,29 @@ void dll_pll_veml_tracking_fpga::start_tracking()
d_carrier_loop_filter.initialize(); // initialize the carrier filter
d_code_loop_filter.initialize(); // initialize the code filter
if (systemName == "GPS" and signal_type == "1C")
{
//gps_l1_ca_code_gen_float(d_tracking_code, d_acquisition_gnss_synchro->PRN, 0);
}
else if (systemName == "GPS" and signal_type == "2S")
{
//gps_l2c_m_code_gen_float(d_tracking_code, d_acquisition_gnss_synchro->PRN);
}
else if (systemName == "GPS" and signal_type == "L5")
if (systemName == "GPS" and signal_type == "L5")
{
if (trk_parameters.track_pilot)
{
//gps_l5q_code_gen_float(d_tracking_code, d_acquisition_gnss_synchro->PRN);
//gps_l5i_code_gen_float(d_data_code, d_acquisition_gnss_synchro->PRN);
d_Prompt_Data[0] = gr_complex(0.0, 0.0);
//correlator_data_cpu.set_local_code_and_taps(d_code_length_chips, d_data_code, d_prompt_data_shift);
}
else
{
//gps_l5i_code_gen_float(d_tracking_code, d_acquisition_gnss_synchro->PRN);
}
}
else if (systemName == "Galileo" and signal_type == "1B")
{
if (trk_parameters.track_pilot)
{
//char pilot_signal[3] = "1C";
//galileo_e1_code_gen_sinboc11_float(d_tracking_code, pilot_signal, d_acquisition_gnss_synchro->PRN);
//galileo_e1_code_gen_sinboc11_float(d_data_code, d_acquisition_gnss_synchro->Signal, d_acquisition_gnss_synchro->PRN);
d_Prompt_Data[0] = gr_complex(0.0, 0.0);
//correlator_data_cpu.set_local_code_and_taps(d_code_samples_per_chip * d_code_length_chips, d_data_code, d_prompt_data_shift);
}
else
{
//galileo_e1_code_gen_sinboc11_float(d_tracking_code, d_acquisition_gnss_synchro->Signal, d_acquisition_gnss_synchro->PRN);
}
}
else if (systemName == "Galileo" and signal_type == "5X")
{
//gr_complex *aux_code = static_cast<gr_complex *>(volk_gnsssdr_malloc(sizeof(gr_complex) * d_code_length_chips, volk_gnsssdr_get_alignment()));
//galileo_e5_a_code_gen_complex_primary(aux_code, d_acquisition_gnss_synchro->PRN, const_cast<char *>(signal_type.c_str()));
if (trk_parameters.track_pilot)
{
d_secondary_code_string = const_cast<std::string *>(&GALILEO_E5A_Q_SECONDARY_CODE[d_acquisition_gnss_synchro->PRN - 1]);
d_Prompt_Data[0] = gr_complex(0.0, 0.0);
//correlator_data_cpu.set_local_code_and_taps(d_code_length_chips, d_data_code, d_prompt_data_shift);
}
else
{
//for (uint32_t i = 0; i < d_code_length_chips; i++)
// {
// d_tracking_code[i] = aux_code[i].real();
// }
}
//volk_gnsssdr_free(aux_code);
}
//multicorrelator_cpu.set_local_code_and_taps(d_code_samples_per_chip * d_code_length_chips, d_tracking_code, d_local_code_shift_chips);
std::fill_n(d_correlator_outs, d_n_correlator_taps, gr_complex(0.0, 0.0));
d_carrier_lock_fail_counter = 0;
@@ -645,15 +545,8 @@ dll_pll_veml_tracking_fpga::~dll_pll_veml_tracking_fpga()
{
volk_gnsssdr_free(d_local_code_shift_chips);
volk_gnsssdr_free(d_correlator_outs);
//volk_gnsssdr_free(d_tracking_code);
volk_gnsssdr_free(d_Prompt_Data);
if (trk_parameters.track_pilot)
{
//volk_gnsssdr_free(d_data_code);
//correlator_data_cpu.free();
}
delete[] d_Prompt_buffer;
//multicorrelator_cpu.free();
multicorrelator_fpga->free();
}
catch (const std::exception &ex)
@@ -763,30 +656,6 @@ void dll_pll_veml_tracking_fpga::do_correlation_step(void)
{
// // ################# CARRIER WIPEOFF AND CORRELATORS ##############################
// // perform carrier wipe-off and compute Early, Prompt and Late correlation
// multicorrelator_cpu.set_input_output_vectors(d_correlator_outs, input_samples);
// multicorrelator_cpu.Carrier_wipeoff_multicorrelator_resampler(
// d_rem_carr_phase_rad,
// d_carrier_phase_step_rad, d_carrier_phase_rate_step_rad,
// static_cast<float>(d_rem_code_phase_chips) * static_cast<float>(d_code_samples_per_chip),
// static_cast<float>(d_code_phase_step_chips) * static_cast<float>(d_code_samples_per_chip),
// static_cast<float>(d_code_phase_rate_step_chips) * static_cast<float>(d_code_samples_per_chip),
// trk_parameters.vector_length);
//
// // DATA CORRELATOR (if tracking tracks the pilot signal)
// if (trk_parameters.track_pilot)
// {
// correlator_data_cpu.set_input_output_vectors(d_Prompt_Data, input_samples);
// correlator_data_cpu.Carrier_wipeoff_multicorrelator_resampler(
// d_rem_carr_phase_rad,
// d_carrier_phase_step_rad, d_carrier_phase_rate_step_rad,
// static_cast<float>(d_rem_code_phase_chips) * static_cast<float>(d_code_samples_per_chip),
// static_cast<float>(d_code_phase_step_chips) * static_cast<float>(d_code_samples_per_chip),
// static_cast<float>(d_code_phase_rate_step_chips) * static_cast<float>(d_code_samples_per_chip),
// trk_parameters.vector_length);
// }
//
//
multicorrelator_fpga->Carrier_wipeoff_multicorrelator_resampler(
d_rem_carr_phase_rad,
@@ -873,9 +742,7 @@ void dll_pll_veml_tracking_fpga::update_tracking_vars()
// Compute the next buffer length based in the new period of the PRN sequence and the code phase error estimation
T_prn_samples = T_prn_seconds * trk_parameters.fs_in;
K_blk_samples = T_prn_samples + d_rem_code_phase_samples;
//d_current_prn_length_samples = static_cast<int32_t>(round(K_blk_samples)); // round to a discrete number of samples
d_next_prn_length_samples = static_cast<int32_t>(std::floor(K_blk_samples)); // round to a discrete number of samples
//d_current_prn_length_samples = static_cast<int32_t>(std::floor(K_blk_samples)); // round to a discrete number of samples
//################### PLL COMMANDS #################################################
// carrier phase step (NCO phase increment per sample) [rads/sample]
@@ -900,16 +767,12 @@ void dll_pll_veml_tracking_fpga::update_tracking_vars()
d_carrier_phase_rate_step_rad = (tmp_cp2 - tmp_cp1) / tmp_samples;
}
}
//std::cout << d_carrier_phase_rate_step_rad * trk_parameters.fs_in * trk_parameters.fs_in / PI_2 << std::endl;
// remnant carrier phase to prevent overflow in the code NCO
d_rem_carr_phase_rad += static_cast<float>(d_carrier_phase_step_rad * static_cast<double>(d_current_prn_length_samples) + 0.5 * d_carrier_phase_rate_step_rad * static_cast<double>(d_current_prn_length_samples) * static_cast<double>(d_current_prn_length_samples));
d_rem_carr_phase_rad = fmod(d_rem_carr_phase_rad, PI_2);
// carrier phase accumulator
//double a = d_carrier_phase_step_rad * static_cast<double>(d_current_prn_length_samples);
//double b = 0.5 * d_carrier_phase_rate_step_rad * static_cast<double>(d_current_prn_length_samples) * static_cast<double>(d_current_prn_length_samples);
//std::cout << fmod(b, PI_2) / fmod(a, PI_2) << std::endl;
d_acc_carrier_phase_rad -= (d_carrier_phase_step_rad * static_cast<double>(d_current_prn_length_samples) + 0.5 * d_carrier_phase_rate_step_rad * static_cast<double>(d_current_prn_length_samples) * static_cast<double>(d_current_prn_length_samples));
//################### DLL COMMANDS #################################################
@@ -1372,7 +1235,6 @@ int32_t dll_pll_veml_tracking_fpga::save_matfile()
void dll_pll_veml_tracking_fpga::set_channel(uint32_t channel)
{
//gr::thread::scoped_lock l(d_setlock);
d_channel = channel;
multicorrelator_fpga->set_channel(d_channel);
LOG(INFO) << "Tracking Channel set to " << d_channel;
@@ -1389,8 +1251,6 @@ void dll_pll_veml_tracking_fpga::set_channel(uint32_t channel)
{
try
{
//trk_parameters.dump_filename.append(boost::lexical_cast<std::string>(d_channel));
//trk_parameters.dump_filename.append(".dat");
d_dump_file.exceptions(std::ifstream::failbit | std::ifstream::badbit);
d_dump_file.open(dump_filename_.c_str(), std::ios::out | std::ios::binary);
LOG(INFO) << "Tracking dump enabled on channel " << d_channel << " Log file: " << dump_filename_.c_str();
@@ -1407,14 +1267,12 @@ void dll_pll_veml_tracking_fpga::set_channel(uint32_t channel)
void dll_pll_veml_tracking_fpga::set_gnss_synchro(Gnss_Synchro *p_gnss_synchro)
{
//gr::thread::scoped_lock l(d_setlock);
d_acquisition_gnss_synchro = p_gnss_synchro;
}
void dll_pll_veml_tracking_fpga::stop_tracking()
{
//gr::thread::scoped_lock l(d_setlock);
d_state = 0;
}
@@ -1423,8 +1281,6 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
{
//gr::thread::scoped_lock l(d_setlock);
//const gr_complex *in = reinterpret_cast<const gr_complex *>(input_items[0]);
Gnss_Synchro **out = reinterpret_cast<Gnss_Synchro **>(&output_items[0]);
Gnss_Synchro current_synchro_data = Gnss_Synchro();
@@ -1435,8 +1291,6 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
{
case 0: // Standby - Consume samples at full throttle, do nothing
{
//d_sample_counter += static_cast<uint64_t>(ninput_items[0]);
//consume_each(ninput_items[0]);
return 0;
break;
}
@@ -1446,21 +1300,17 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
double acq_trk_diff_seconds;
double delta_trk_to_acq_prn_start_samples;
//printf("state 1\n");
multicorrelator_fpga->lock_channel();
uint64_t counter_value = multicorrelator_fpga->read_sample_counter();
uint64_t absolute_samples_offset;
if (counter_value > (d_acq_sample_stamp + d_acq_code_phase_samples))
{
// Signal alignment (skip samples until the incoming signal is aligned with local replica)
//int64_t acq_trk_diff_samples = static_cast<int64_t>(d_sample_counter) - static_cast<int64_t>(d_acq_sample_stamp);
acq_trk_diff_samples = static_cast<int64_t>(counter_value) - static_cast<int64_t>(d_acq_sample_stamp);
acq_trk_diff_seconds = static_cast<double>(acq_trk_diff_samples) / trk_parameters.fs_in;
delta_trk_to_acq_prn_start_samples = static_cast<double>(acq_trk_diff_samples) - d_acq_code_phase_samples;
//uint32_t num_frames = ceil((counter_value - d_acq_sample_stamp - d_acq_code_phase_samples) / d_correlation_length_samples);
uint32_t num_frames = ceil((delta_trk_to_acq_prn_start_samples) / d_correlation_length_samples);
//absolute_samples_offset = static_cast<uint64_t>(d_acq_code_phase_samples + d_acq_sample_stamp + num_frames * d_correlation_length_samples);
absolute_samples_offset = static_cast<uint64_t>(d_acq_code_phase_samples + d_acq_sample_stamp + num_frames * d_correlation_length_samples);
}
else
@@ -1471,7 +1321,6 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
acq_trk_diff_seconds = static_cast<double>(acq_trk_diff_samples) / trk_parameters.fs_in;
delta_trk_to_acq_prn_start_samples = static_cast<double>(acq_trk_diff_samples) + d_acq_code_phase_samples;
//absolute_samples_offset = static_cast<uint64_t>(d_acq_code_phase_samples + d_acq_sample_stamp);
absolute_samples_offset = static_cast<uint64_t>(delta_trk_to_acq_prn_start_samples);
}
multicorrelator_fpga->set_initial_sample(absolute_samples_offset);
@@ -1481,11 +1330,7 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
d_sample_counter_next = d_sample_counter;
// // Signal alignment (skip samples until the incoming signal is aligned with local replica)
// //int64_t acq_trk_diff_samples = static_cast<int64_t>(d_sample_counter) - static_cast<int64_t>(d_acq_sample_stamp);
// int64_t acq_trk_diff_samples = static_cast<int64_t>(counter_value) - static_cast<int64_t>(d_acq_sample_stamp);
// double acq_trk_diff_seconds = static_cast<double>(acq_trk_diff_samples) / trk_parameters.fs_in;
// double delta_trk_to_acq_prn_start_samples = static_cast<double>(acq_trk_diff_samples) - d_acq_code_phase_samples;
// Signal alignment (skip samples until the incoming signal is aligned with local replica)
// Doppler effect Fd = (C / (C + Vr)) * F
double radial_velocity = (d_signal_carrier_freq + d_acq_carrier_doppler_hz) / d_signal_carrier_freq;
@@ -1497,7 +1342,6 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
double T_prn_mod_seconds = T_chip_mod_seconds * static_cast<double>(d_code_length_chips);
double T_prn_mod_samples = T_prn_mod_seconds * trk_parameters.fs_in;
//d_acq_code_phase_samples = T_prn_mod_samples - std::fmod(delta_trk_to_acq_prn_start_samples, T_prn_mod_samples);
d_acq_code_phase_samples = absolute_samples_offset;
d_current_prn_length_samples = round(T_prn_mod_samples);
@@ -1511,11 +1355,11 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
DLOG(INFO) << "PULL-IN Doppler [Hz] = " << d_carrier_doppler_hz
<< ". PULL-IN Code Phase [samples] = " << d_acq_code_phase_samples;
// don't leave the HW module blocking the signal path before the first sample arrives
// start the first tracking process
run_state_2(current_synchro_data);
break;
//consume_each(samples_offset); // shift input to perform alignment with local replica
//return 0;
}
case 2: // Wide tracking and symbol synchronization
{
@@ -1524,7 +1368,6 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
}
case 3: // coherent integration (correlation time extension)
{
//printf("state 3\n");
d_sample_counter = d_sample_counter_next;
d_sample_counter_next = d_sample_counter + static_cast<uint64_t>(d_current_prn_length_samples);
@@ -1581,7 +1424,6 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
}
case 4: // narrow tracking
{
//printf("state 4\n");
d_sample_counter = d_sample_counter_next;
d_sample_counter_next = d_sample_counter + static_cast<uint64_t>(d_current_prn_length_samples);
// Fill the acquisition data
@@ -1652,15 +1494,12 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
}
}
}
//consume_each(d_current_prn_length_samples);
//d_sample_counter += static_cast<uint64_t>(d_current_prn_length_samples);
if (current_synchro_data.Flag_valid_symbol_output)
{
current_synchro_data.fs = static_cast<int64_t>(trk_parameters.fs_in);
// two choices for the reporting of the sample counter:
// either the sample counter position that should be (d_sample_counter_next)
//or the sample counter corresponding to the number of samples that the FPGA actually consumed.
//current_synchro_data.Tracking_sample_counter = d_sample_counter + static_cast<uint64_t>(d_current_prn_length_samples);
// two choices for the reporting of the sample counter:
// either the sample counter position that should be (d_sample_counter_next)
//or the sample counter corresponding to the number of samples that the FPGA actually consumed.
current_synchro_data.Tracking_sample_counter = d_sample_counter_next;
*out[0] = current_synchro_data;
return 1;
@@ -1670,7 +1509,6 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
void dll_pll_veml_tracking_fpga::run_state_2(Gnss_Synchro &current_synchro_data)
{
//printf("state 2\n");
d_sample_counter = d_sample_counter_next;
d_sample_counter_next = d_sample_counter + static_cast<uint64_t>(d_current_prn_length_samples);
@@ -1740,7 +1578,6 @@ void dll_pll_veml_tracking_fpga::run_state_2(Gnss_Synchro &current_synchro_data)
}
if (corr_value == GPS_CA_PREAMBLE_LENGTH_SYMBOLS)
{
//std::cout << "Preamble detected at tracking!" << std::endl;
next_state = true;
}
else

9
src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.h
View File

@@ -1,13 +1,13 @@
/*!
* \file dll_pll_veml_tracking.h
* \brief Implementation of a code DLL + carrier PLL tracking block.
* \author Marc Majoral, 2018. marc.majoral(at)cttc.es
* \file dll_pll_veml_tracking_fpga.h
* \brief Implementation of a code DLL + carrier PLL tracking block using an FPGA.
* \author Marc Majoral, 2019. marc.majoral(at)cttc.es
* \author Javier Arribas, 2018. jarribas(at)cttc.es
* \author Antonio Ramos, 2018 antonio.ramosdet(at)gmail.com
*
* -------------------------------------------------------------------------
*
* Copyright (C) 2010-2018 (see AUTHORS file for a list of contributors)
* Copyright (C) 2010-2019 (see AUTHORS file for a list of contributors)
*
* GNSS-SDR is a software defined Global Navigation
* Satellite Systems receiver
@@ -80,7 +80,6 @@ private:
bool cn0_and_tracking_lock_status(double coh_integration_time_s);
bool acquire_secondary();
//void do_correlation_step(const gr_complex *input_samples);
void do_correlation_step(void);
void run_dll_pll();
void update_tracking_vars();

7
src/algorithms/tracking/libs/dll_pll_conf_fpga.cc
View File

@@ -1,12 +1,13 @@
/*!
* \file dll_pll_conf.cc
* \file dll_pll_conf_fpga.cc
* \brief Class that contains all the configuration parameters for generic
* tracking block based on a DLL and a PLL.
* tracking block based on a DLL and a PLL for the FPGA.
* \author Marc Majoral, 2019. mmajoral(at)cttc.cat
* \author Javier Arribas, 2018. jarribas(at)cttc.es
*
* -------------------------------------------------------------------------
*
* Copyright (C) 2010-2018 (see AUTHORS file for a list of contributors)
* Copyright (C) 2010-2019 (see AUTHORS file for a list of contributors)
*
* GNSS-SDR is a software defined Global Navigation
* Satellite Systems receiver

8
src/algorithms/tracking/libs/dll_pll_conf_fpga.h
View File

@@ -1,13 +1,15 @@
/*!
* \file dll_pll_conf.h
* \brief Class that contains all the configuration parameters for generic tracking block based on a DLL and a PLL.
* \file dll_pll_conf_fpga.h
* \brief Class that contains all the configuration parameters for generic
* tracking block based on a DLL and a PLL for the FPGA.
* \author Marc Majoral, 2019. mmajoral(at)cttc.cat
* \author Javier Arribas, 2018. jarribas(at)cttc.es
*
* Class that contains all the configuration parameters for generic tracking block based on a DLL and a PLL.
*
* -------------------------------------------------------------------------
*
* Copyright (C) 2010-2018 (see AUTHORS file for a list of contributors)
* Copyright (C) 2010-2019 (see AUTHORS file for a list of contributors)
*
* GNSS-SDR is a software defined Global Navigation
* Satellite Systems receiver

371
src/algorithms/tracking/libs/fpga_multicorrelator.cc
View File

@@ -2,7 +2,7 @@
* \file fpga_multicorrelator_8sc.cc
* \brief High optimized FPGA vector correlator class
* \authors <ul>
* <li> Marc Majoral, 2017. mmajoral(at)cttc.cat
* <li> Marc Majoral, 2019. mmajoral(at)cttc.cat
* <li> Javier Arribas, 2015. jarribas(at)cttc.es
* </ul>
*
@@ -11,7 +11,7 @@
*
* -------------------------------------------------------------------------
*
* Copyright (C) 2010-2018 (see AUTHORS file for a list of contributors)
* Copyright (C) 2010-2019 (see AUTHORS file for a list of contributors)
*
* GNSS-SDR is a software defined Global Navigation
* Satellite Systems receiver
@@ -36,81 +36,62 @@
#include "fpga_multicorrelator.h"
#include <cmath>
// FPGA stuff
#include <new>
// libraries used by DMA test code and GIPO test code
#include <cerrno>
#include <cstdio>
#include <fcntl.h>
#include <unistd.h>
// libraries used by DMA test code
#include <cassert>
#include <cstdint>
#include <sys/stat.h>
#include <unistd.h>
// libraries used by GPIO test code
#include <csignal>
#include <cstdlib>
#include <sys/mman.h>
// logging
#include <glog/logging.h>
// string manipulation
#include <string>
#include <utility>
// constants
#include "GPS_L1_CA.h"
// FPGA register access constants
#define PAGE_SIZE 0x10000
#define MAX_LENGTH_DEVICEIO_NAME 50
#define CODE_RESAMPLER_NUM_BITS_PRECISION 20
#define CODE_PHASE_STEP_CHIPS_NUM_NBITS CODE_RESAMPLER_NUM_BITS_PRECISION
#define pwrtwo(x) (1 << (x))
#define MAX_CODE_RESAMPLER_COUNTER pwrtwo(CODE_PHASE_STEP_CHIPS_NUM_NBITS) // 2^CODE_PHASE_STEP_CHIPS_NUM_NBITS
#define PHASE_CARR_NBITS 32
#define PHASE_CARR_NBITS_INT 1
#define PHASE_CARR_NBITS_FRAC PHASE_CARR_NBITS - PHASE_CARR_NBITS_INT
#define LOCAL_CODE_FPGA_CORRELATOR_SELECT_COUNT 0x20000000
#define LOCAL_CODE_FPGA_CLEAR_ADDRESS_COUNTER 0x10000000
#define LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY 0x0C000000
#define TEST_REGISTER_TRACK_WRITEVAL 0x55AA
//#include "gps_sdr_signal_processing.h"
#define NUM_PRNs 32
#define PAGE_SIZE 0x10000
#define MAX_LENGTH_DEVICEIO_NAME 50
#define CODE_RESAMPLER_NUM_BITS_PRECISION 20
#define CODE_PHASE_STEP_CHIPS_NUM_NBITS CODE_RESAMPLER_NUM_BITS_PRECISION
#define pwrtwo(x) (1 << (x))
#define MAX_CODE_RESAMPLER_COUNTER pwrtwo(CODE_PHASE_STEP_CHIPS_NUM_NBITS) // 2^CODE_PHASE_STEP_CHIPS_NUM_NBITS
#define PHASE_CARR_NBITS 32
#define PHASE_CARR_NBITS_INT 1
#define PHASE_CARR_NBITS_FRAC PHASE_CARR_NBITS - PHASE_CARR_NBITS_INT
#define LOCAL_CODE_FPGA_CORRELATOR_SELECT_COUNT 0x20000000
#define LOCAL_CODE_FPGA_CLEAR_ADDRESS_COUNTER 0x10000000
#define LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY 0x0C000000
#define TEST_REGISTER_TRACK_WRITEVAL 0x55AA
uint64_t fpga_multicorrelator_8sc::read_sample_counter()
{
uint64_t sample_counter_tmp, sample_counter_msw_tmp;
sample_counter_tmp = d_map_base[d_SAMPLE_COUNTER_REG_ADDR_LSW];
sample_counter_msw_tmp = d_map_base[d_SAMPLE_COUNTER_REG_ADDR_MSW];
sample_counter_tmp = d_map_base[SAMPLE_COUNTER_REG_ADDR_LSW];
sample_counter_msw_tmp = d_map_base[SAMPLE_COUNTER_REG_ADDR_MSW];
sample_counter_msw_tmp = sample_counter_msw_tmp << 32;
sample_counter_tmp = sample_counter_tmp + sample_counter_msw_tmp; // 2^32
//return d_map_base[d_SAMPLE_COUNTER_REG_ADDR];
return sample_counter_tmp;
}
void fpga_multicorrelator_8sc::set_initial_sample(uint64_t samples_offset)
{
d_initial_sample_counter = samples_offset;
//printf("www writing d map base %d = d_initial_sample_counter = %d\n", d_INITIAL_COUNTER_VALUE_REG_ADDR, d_initial_sample_counter);
d_map_base[d_INITIAL_COUNTER_VALUE_REG_ADDR_LSW] = (d_initial_sample_counter & 0xFFFFFFFF);
d_map_base[d_INITIAL_COUNTER_VALUE_REG_ADDR_MSW] = (d_initial_sample_counter >> 32) & 0xFFFFFFFF;
d_map_base[INITIAL_COUNTER_VALUE_REG_ADDR_LSW] = (d_initial_sample_counter & 0xFFFFFFFF);
d_map_base[INITIAL_COUNTER_VALUE_REG_ADDR_MSW] = (d_initial_sample_counter >> 32) & 0xFFFFFFFF;
}
//void fpga_multicorrelator_8sc::set_local_code_and_taps(int32_t code_length_chips,
// float *shifts_chips, int32_t PRN)
void fpga_multicorrelator_8sc::set_local_code_and_taps(float *shifts_chips, float *prompt_data_shift, int32_t PRN)
{
d_shifts_chips = shifts_chips;
d_prompt_data_shift = prompt_data_shift;
//d_code_length_chips = code_length_chips;
fpga_multicorrelator_8sc::fpga_configure_tracking_gps_local_code(PRN);
}
@@ -123,7 +104,6 @@ void fpga_multicorrelator_8sc::set_output_vectors(gr_complex *corr_out, gr_compl
void fpga_multicorrelator_8sc::update_local_code(float rem_code_phase_chips)
{
d_rem_code_phase_chips = rem_code_phase_chips;
//printf("uuuuu d_rem_code_phase_chips = %f\n", d_rem_code_phase_chips);
fpga_multicorrelator_8sc::fpga_compute_code_shift_parameters();
fpga_multicorrelator_8sc::fpga_configure_code_parameters_in_fpga();
}
@@ -146,13 +126,11 @@ void fpga_multicorrelator_8sc::Carrier_wipeoff_multicorrelator_resampler(
fpga_multicorrelator_8sc::fpga_launch_multicorrelator_fpga();
int32_t irq_count;
ssize_t nb;
//printf("$$$$$ waiting for interrupt ... \n");
nb = read(d_device_descriptor, &irq_count, sizeof(irq_count));
//printf("$$$$$ interrupt received ... \n");
if (nb != sizeof(irq_count))
{
printf("Tracking_module Read failed to retrieve 4 bytes!\n");
printf("Tracking_module Interrupt number %d\n", irq_count);
std::cout << "Tracking_module Read failed to retrieve 4 bytes!" << std::endl;
std::cout << "Tracking_module Interrupt number " << irq_count << std::endl;
}
fpga_multicorrelator_8sc::read_tracking_gps_results();
}
@@ -161,7 +139,6 @@ fpga_multicorrelator_8sc::fpga_multicorrelator_8sc(int32_t n_correlators,
std::string device_name, uint32_t device_base, int32_t *ca_codes, int32_t *data_codes, uint32_t code_length_chips, bool track_pilot,
uint32_t multicorr_type, uint32_t code_samples_per_chip)
{
//printf("tracking fpga class created\n");
d_n_correlators = n_correlators;
d_device_name = std::move(device_name);
d_device_base = device_base;
@@ -197,103 +174,18 @@ fpga_multicorrelator_8sc::fpga_multicorrelator_8sc(int32_t n_correlators,
d_initial_sample_counter = 0;
d_channel = 0;
d_correlator_length_samples = 0,
//d_code_length = code_length;
d_code_length_chips = code_length_chips;
d_code_length_chips = code_length_chips;
d_ca_codes = ca_codes;
d_data_codes = data_codes;
d_multicorr_type = multicorr_type;
d_code_samples_per_chip = code_samples_per_chip;
// set up register mapping
// write-only registers
d_CODE_PHASE_STEP_CHIPS_NUM_REG_ADDR = 0;
d_INITIAL_INDEX_REG_BASE_ADDR = 1;
// if (d_multicorr_type == 0)
// {
// // multicorrelator with 3 correlators (16 registers only)
// d_INITIAL_INTERP_COUNTER_REG_BASE_ADDR = 4;
// d_NSAMPLES_MINUS_1_REG_ADDR = 7;
// d_CODE_LENGTH_MINUS_1_REG_ADDR = 8;
// d_REM_CARR_PHASE_RAD_REG_ADDR = 9;
// d_PHASE_STEP_RAD_REG_ADDR = 10;
// d_PROG_MEMS_ADDR = 11;
// d_DROP_SAMPLES_REG_ADDR = 12;
// d_INITIAL_COUNTER_VALUE_REG_ADDR = 13;
// d_START_FLAG_ADDR = 14;
// }
// else
// {
// other types of multicorrelators (32 registers)
d_INITIAL_INTERP_COUNTER_REG_BASE_ADDR = 7;
d_NSAMPLES_MINUS_1_REG_ADDR = 13;
d_CODE_LENGTH_MINUS_1_REG_ADDR = 14;
d_REM_CARR_PHASE_RAD_REG_ADDR = 15;
d_PHASE_STEP_RAD_REG_ADDR = 16;
d_PROG_MEMS_ADDR = 17;
d_DROP_SAMPLES_REG_ADDR = 18;
d_INITIAL_COUNTER_VALUE_REG_ADDR_LSW = 19;
d_INITIAL_COUNTER_VALUE_REG_ADDR_MSW = 20;
d_START_FLAG_ADDR = 30;
// }
//printf("d_n_correlators = %d\n", d_n_correlators);
//printf("d_multicorr_type = %d\n", d_multicorr_type);
// read-write registers
// if (d_multicorr_type == 0)
// {
// // multicorrelator with 3 correlators (16 registers only)
// d_TEST_REG_ADDR = 15;
// }
// else
// {
// other types of multicorrelators (32 registers)
d_TEST_REG_ADDR = 31;
// }
// result 2's complement saturation value
// if (d_multicorr_type == 0)
// {
// // multicorrelator with 3 correlators (16 registers only)
// d_result_SAT_value = 1048576; // 21 bits 2's complement -> 2^20
// }
// else
// {
// // other types of multicorrelators (32 registers)
// d_result_SAT_value = 4194304; // 23 bits 2's complement -> 2^22
// }
// read only registers
d_RESULT_REG_REAL_BASE_ADDR = 1;
// if (d_multicorr_type == 0)
// {
// // multicorrelator with 3 correlators (16 registers only)
// d_RESULT_REG_IMAG_BASE_ADDR = 4;
// d_RESULT_REG_DATA_REAL_BASE_ADDR = 0; // no pilot tracking
// d_RESULT_REG_DATA_IMAG_BASE_ADDR = 0;
// d_SAMPLE_COUNTER_REG_ADDR = 7;
//
// }
// else
// {
// other types of multicorrelators (32 registers)
d_RESULT_REG_IMAG_BASE_ADDR = 7;
//d_RESULT_REG_DATA_REAL_BASE_ADDR = 6; // no pilot tracking
//d_RESULT_REG_DATA_IMAG_BASE_ADDR = 12;
d_SAMPLE_COUNTER_REG_ADDR_LSW = 13;
d_SAMPLE_COUNTER_REG_ADDR_MSW = 14;
// }
//printf("d_SAMPLE_COUNTER_REG_ADDR = %d\n", d_SAMPLE_COUNTER_REG_ADDR);
//printf("mmmmmmmmmmmmm d_n_correlators = %d\n", d_n_correlators);
DLOG(INFO) << "TRACKING FPGA CLASS CREATED";
}
fpga_multicorrelator_8sc::~fpga_multicorrelator_8sc()
{
//delete[] d_ca_codes;
close_device();
}
@@ -322,7 +214,6 @@ bool fpga_multicorrelator_8sc::free()
void fpga_multicorrelator_8sc::set_channel(uint32_t channel)
{
//printf("www trk set channel channel=%lu\n", (unsigned long) channel);
char device_io_name[MAX_LENGTH_DEVICEIO_NAME]; // driver io name
d_channel = channel;
@@ -334,22 +225,13 @@ void fpga_multicorrelator_8sc::set_channel(uint32_t channel)
mergedname = d_device_name + devicebasetemp.str();
strcpy(device_io_name, mergedname.c_str());
//printf("ppps opening device %s\n", device_io_name);
printf("trk device_io_name = %s\n", device_io_name);
std::cout << "trk device_io_name = " << device_io_name << std::endl;
if ((d_device_descriptor = open(device_io_name, O_RDWR | O_SYNC)) == -1)
{
LOG(WARNING) << "Cannot open deviceio" << device_io_name;
std::cout << "Cannot open deviceio" << device_io_name << std::endl;
//printf("error opening device\n");
}
// else
// {
// std::cout << "deviceio" << device_io_name << " opened successfully" << std::endl;
//
// }
d_map_base = reinterpret_cast<volatile uint32_t *>(mmap(nullptr, PAGE_SIZE,
PROT_READ | PROT_WRITE, MAP_SHARED, d_device_descriptor, 0));
@@ -358,16 +240,7 @@ void fpga_multicorrelator_8sc::set_channel(uint32_t channel)
LOG(WARNING) << "Cannot map the FPGA tracking module "
<< d_channel << "into user memory";
std::cout << "Cannot map deviceio" << device_io_name << std::endl;
//printf("error mapping registers\n");
}
// else
// {
// std::cout << "deviceio" << device_io_name << "mapped successfully" << std::endl;
// }
// else
// {
// printf("trk mapping registers succes\n"); // this is for debug -- remove !
// }
// sanity check : check test register
uint32_t writeval = TEST_REGISTER_TRACK_WRITEVAL;
@@ -376,15 +249,11 @@ void fpga_multicorrelator_8sc::set_channel(uint32_t channel)
if (writeval != readval)
{
LOG(WARNING) << "Test register sanity check failed";
printf("tracking test register sanity check failed\n");
//printf("lslslls test sanity check reg failure\n");
std::cout << "tracking test register sanity check failed" << std::endl;
}
else
{
LOG(INFO) << "Test register sanity check success !";
//printf("tracking test register sanity check success\n");
//printf("lslslls test sanity check reg success\n");
}
}
@@ -392,13 +261,11 @@ void fpga_multicorrelator_8sc::set_channel(uint32_t channel)
uint32_t fpga_multicorrelator_8sc::fpga_acquisition_test_register(
uint32_t writeval)
{
//printf("d_TEST_REG_ADDR = %d\n", d_TEST_REG_ADDR);
uint32_t readval = 0;
// write value to test register
d_map_base[d_TEST_REG_ADDR] = writeval;
d_map_base[TEST_REG_ADDR] = writeval;
// read value from test register
readval = d_map_base[d_TEST_REG_ADDR];
readval = d_map_base[TEST_REG_ADDR];
// return read value
return readval;
}
@@ -409,28 +276,10 @@ void fpga_multicorrelator_8sc::fpga_configure_tracking_gps_local_code(int32_t PR
uint32_t k;
uint32_t code_chip;
uint32_t select_pilot_corelator = LOCAL_CODE_FPGA_CORRELATOR_SELECT_COUNT;
// select_fpga_correlator = 0;
//printf("kkk d_n_correlators = %x\n", d_n_correlators);
//printf("kkk d_code_length_chips = %d\n", d_code_length_chips);
//printf("programming mems d map base %d\n", d_PROG_MEMS_ADDR);
//FILE *fp;
//char str[80];
//sprintf(str, "generated_code_PRN%d", PRN);
//fp = fopen(str,"w");
// for (s = 0; s < d_n_correlators; s++)
// {
//printf("kkk select_fpga_correlator = %x\n", select_fpga_correlator);
d_map_base[d_PROG_MEMS_ADDR] = LOCAL_CODE_FPGA_CLEAR_ADDRESS_COUNTER;
//printf("trk lib d_code_length_chips = %d, d_code_samples_per_chip = %d\n", d_code_length_chips, d_code_samples_per_chip);
d_map_base[PROG_MEMS_ADDR] = LOCAL_CODE_FPGA_CLEAR_ADDRESS_COUNTER;
for (k = 0; k < d_code_length_chips * d_code_samples_per_chip; k++)
{
//if (d_local_code_in[k] == 1)
//printf("kkk d_ca_codes %d = %d\n", k, d_ca_codes[((int(d_code_length)) * (PRN - 1)) + k]);
//fprintf(fp, "%d\n", d_ca_codes[((int(d_code_length_chips)) * d_code_samples_per_chip * (PRN - 1)) + k]);
if (d_ca_codes[((int(d_code_length_chips)) * d_code_samples_per_chip * (PRN - 1)) + k] == 1)
{
code_chip = 1;
@@ -441,21 +290,14 @@ void fpga_multicorrelator_8sc::fpga_configure_tracking_gps_local_code(int32_t PR
}
// copy the local code to the FPGA memory one by one
d_map_base[d_PROG_MEMS_ADDR] = LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY | code_chip; // | select_fpga_correlator;
d_map_base[PROG_MEMS_ADDR] = LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY | code_chip; // | select_fpga_correlator;
}
// select_fpga_correlator = select_fpga_correlator
// + LOCAL_CODE_FPGA_CORRELATOR_SELECT_COUNT;
// }
//fclose(fp);
//printf("kkk d_track_pilot = %d\n", d_track_pilot);
if (d_track_pilot)
{
//printf("kkk select_fpga_correlator = %x\n", select_fpga_correlator);
d_map_base[d_PROG_MEMS_ADDR] = LOCAL_CODE_FPGA_CLEAR_ADDRESS_COUNTER;
d_map_base[PROG_MEMS_ADDR] = LOCAL_CODE_FPGA_CLEAR_ADDRESS_COUNTER;
for (k = 0; k < d_code_length_chips * d_code_samples_per_chip; k++)
{
//if (d_local_code_in[k] == 1)
if (d_data_codes[((int(d_code_length_chips)) * d_code_samples_per_chip * (PRN - 1)) + k] == 1)
{
code_chip = 1;
@@ -464,12 +306,9 @@ void fpga_multicorrelator_8sc::fpga_configure_tracking_gps_local_code(int32_t PR
{
code_chip = 0;
}
//printf("%d %d | ", d_data_codes, code_chip);
// copy the local code to the FPGA memory one by one
d_map_base[d_PROG_MEMS_ADDR] = LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY | code_chip | select_pilot_corelator;
d_map_base[PROG_MEMS_ADDR] = LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY | code_chip | select_pilot_corelator;
}
}
//printf("\n");
}
@@ -478,39 +317,27 @@ void fpga_multicorrelator_8sc::fpga_compute_code_shift_parameters(void)
float temp_calculation;
int32_t i;
//printf("ppp d_rem_code_phase_chips = %f\n", d_rem_code_phase_chips);
for (i = 0; i < d_n_correlators; i++)
{
//printf("ppp d_shifts_chips %d = %f\n", i, d_shifts_chips[i]);
//printf("ppp d_code_samples_per_chip = %d\n", d_code_samples_per_chip);
temp_calculation = floor(
d_shifts_chips[i] - d_rem_code_phase_chips);
//printf("ppp d_rem_code_phase_chips = %f\n", d_rem_code_phase_chips);
//printf("ppp temp calculation %d = %f ================================ \n", i, temp_calculation);
if (temp_calculation < 0)
{
temp_calculation = temp_calculation + (d_code_length_chips * d_code_samples_per_chip); // % operator does not work as in Matlab with negative numbers
}
//printf("ppp d_rem_code_phase_chips = %f\n", d_rem_code_phase_chips);
//printf("ppp temp calculation %d = %f ================================ \n", i, temp_calculation);
d_initial_index[i] = static_cast<uint32_t>((static_cast<int32_t>(temp_calculation)) % (d_code_length_chips * d_code_samples_per_chip));
//printf("ppp d_initial_index %d = %d\n", i, d_initial_index[i]);
temp_calculation = fmod(d_shifts_chips[i] - d_rem_code_phase_chips,
1.0);
//printf("ppp fmod %d = fmod(%f, 1) = %f\n", i, d_shifts_chips[i] - d_rem_code_phase_chips, temp_calculation);
if (temp_calculation < 0)
{
temp_calculation = temp_calculation + 1.0; // fmod operator does not work as in Matlab with negative numbers
}
d_initial_interp_counter[i] = static_cast<uint32_t>(floor(MAX_CODE_RESAMPLER_COUNTER * temp_calculation));
//printf("ppp d_initial_interp_counter %d = %d\n", i, d_initial_interp_counter[i]);
//printf("MAX_CODE_RESAMPLER_COUNTER = %d\n", MAX_CODE_RESAMPLER_COUNTER);
}
if (d_track_pilot)
{
//printf("tracking pilot !!!!!!!!!!!!!!!!\n");
temp_calculation = floor(
d_prompt_data_shift[0] - d_rem_code_phase_chips);
@@ -527,7 +354,6 @@ void fpga_multicorrelator_8sc::fpga_compute_code_shift_parameters(void)
}
d_initial_interp_counter[d_n_correlators] = static_cast<uint32_t>(floor(MAX_CODE_RESAMPLER_COUNTER * temp_calculation));
}
//while(1);
}
@@ -536,23 +362,16 @@ void fpga_multicorrelator_8sc::fpga_configure_code_parameters_in_fpga(void)
int32_t i;
for (i = 0; i < d_n_correlators; i++)
{
//printf("www writing d map base %d = d_initial_index %d = %d\n", d_INITIAL_INDEX_REG_BASE_ADDR + i, i, d_initial_index[i]);
d_map_base[d_INITIAL_INDEX_REG_BASE_ADDR + i] = d_initial_index[i];
//d_map_base[1 + d_n_correlators + i] = d_initial_interp_counter[i];
//printf("www writing d map base %d = d_initial_interp_counter %d = %d\n", d_INITIAL_INTERP_COUNTER_REG_BASE_ADDR + i, i, d_initial_interp_counter[i]);
d_map_base[d_INITIAL_INTERP_COUNTER_REG_BASE_ADDR + i] = d_initial_interp_counter[i];
d_map_base[INITIAL_INDEX_REG_BASE_ADDR + i] = d_initial_index[i];
d_map_base[INITIAL_INTERP_COUNTER_REG_BASE_ADDR + i] = d_initial_interp_counter[i];
}
if (d_track_pilot)
{
//printf("www writing d map base %d = d_initial_index %d = %d\n", d_INITIAL_INDEX_REG_BASE_ADDR + d_n_correlators, d_n_correlators, d_initial_index[d_n_correlators]);
d_map_base[d_INITIAL_INDEX_REG_BASE_ADDR + d_n_correlators] = d_initial_index[d_n_correlators];
//d_map_base[1 + d_n_correlators + i] = d_initial_interp_counter[i];
//printf("www writing d map base %d = d_initial_interp_counter %d = %d\n", d_INITIAL_INTERP_COUNTER_REG_BASE_ADDR + d_n_correlators, d_n_correlators, d_initial_interp_counter[d_n_correlators]);
d_map_base[d_INITIAL_INTERP_COUNTER_REG_BASE_ADDR + d_n_correlators] = d_initial_interp_counter[d_n_correlators];
d_map_base[INITIAL_INDEX_REG_BASE_ADDR + d_n_correlators] = d_initial_index[d_n_correlators];
d_map_base[INITIAL_INTERP_COUNTER_REG_BASE_ADDR + d_n_correlators] = d_initial_interp_counter[d_n_correlators];
}
//printf("www writing d map base %d = d_code_length_chips*d_code_samples_per_chip - 1 = %d\n", d_CODE_LENGTH_MINUS_1_REG_ADDR, (d_code_length_chips*d_code_samples_per_chip) - 1);
d_map_base[d_CODE_LENGTH_MINUS_1_REG_ADDR] = (d_code_length_chips * d_code_samples_per_chip) - 1; // number of samples - 1
d_map_base[CODE_LENGTH_MINUS_1_REG_ADDR] = (d_code_length_chips * d_code_samples_per_chip) - 1; // number of samples - 1
}
@@ -563,11 +382,9 @@ void fpga_multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga(void)
d_code_phase_step_chips_num = static_cast<uint32_t>(roundf(MAX_CODE_RESAMPLER_COUNTER * d_code_phase_step_chips));
if (d_code_phase_step_chips > 1.0)
{
printf("Warning : d_code_phase_step_chips = %f cannot be bigger than one\n", d_code_phase_step_chips);
std::cout << "Warning : d_code_phase_step_chips = " << d_code_phase_step_chips << " cannot be bigger than one" << std::endl;
}
//printf("d_rem_carrier_phase_in_rad = %f\n", d_rem_carrier_phase_in_rad);
if (d_rem_carrier_phase_in_rad > M_PI)
{
d_rem_carrier_phase_in_rad_temp = -2 * M_PI + d_rem_carrier_phase_in_rad;
@@ -589,29 +406,23 @@ void fpga_multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga(void)
d_phase_step_rad_int = static_cast<int32_t>(roundf(
(fabs(d_phase_step_rad) / M_PI) * pow(2, PHASE_CARR_NBITS_FRAC))); // the FPGA accepts a range for the phase step between -pi and +pi
//printf("d_phase_step_rad_int = %d\n", d_phase_step_rad_int);
if (d_phase_step_rad < 0)
{
d_phase_step_rad_int = -d_phase_step_rad_int;
}
//printf("d_phase_step_rad_int = %d\n", d_phase_step_rad_int);
}
void fpga_multicorrelator_8sc::fpga_configure_signal_parameters_in_fpga(void)
{
//printf("www d map base %d = d_code_phase_step_chips_num = %d\n", d_CODE_PHASE_STEP_CHIPS_NUM_REG_ADDR, d_code_phase_step_chips_num);
d_map_base[d_CODE_PHASE_STEP_CHIPS_NUM_REG_ADDR] = d_code_phase_step_chips_num;
d_map_base[CODE_PHASE_STEP_CHIPS_NUM_REG_ADDR] = d_code_phase_step_chips_num;
//printf("www d map base %d = d_correlator_length_samples - 1 = %d\n", d_NSAMPLES_MINUS_1_REG_ADDR, d_correlator_length_samples - 1);
d_map_base[d_NSAMPLES_MINUS_1_REG_ADDR] = d_correlator_length_samples - 1;
d_map_base[NSAMPLES_MINUS_1_REG_ADDR] = d_correlator_length_samples - 1;
//printf("www d map base %d = d_rem_carr_phase_rad_int = %d\n", d_REM_CARR_PHASE_RAD_REG_ADDR, d_rem_carr_phase_rad_int);
d_map_base[d_REM_CARR_PHASE_RAD_REG_ADDR] = d_rem_carr_phase_rad_int;
d_map_base[REM_CARR_PHASE_RAD_REG_ADDR] = d_rem_carr_phase_rad_int;
//printf("www d map base %d = d_phase_step_rad_int = %d\n", d_PHASE_STEP_RAD_REG_ADDR, d_phase_step_rad_int);
d_map_base[d_PHASE_STEP_RAD_REG_ADDR] = d_phase_step_rad_int;
d_map_base[PHASE_STEP_RAD_REG_ADDR] = d_phase_step_rad_int;
}
@@ -622,9 +433,7 @@ void fpga_multicorrelator_8sc::fpga_launch_multicorrelator_fpga(void)
write(d_device_descriptor, reinterpret_cast<void *>(&reenable), sizeof(int32_t));
// writing 1 to reg 14 launches the tracking
//printf("www writing 1 to d map base %d = start flag\n", d_START_FLAG_ADDR);
d_map_base[d_START_FLAG_ADDR] = 1;
//while(1);
d_map_base[START_FLAG_ADDR] = 1;
}
@@ -634,76 +443,17 @@ void fpga_multicorrelator_8sc::read_tracking_gps_results(void)
int32_t readval_imag;
int32_t k;
//printf("www reading trk results\n");
for (k = 0; k < d_n_correlators; k++)
{
readval_real = d_map_base[d_RESULT_REG_REAL_BASE_ADDR + k];
//printf("read real before checking d map base %d = %d\n", d_RESULT_REG_BASE_ADDR + k, readval_real);
//// if (readval_real > debug_max_readval_real[k])
//// {
//// debug_max_readval_real[k] = readval_real;
//// }
// if (readval_real >= d_result_SAT_value) // 0x100000 (21 bits two's complement)
// {
// readval_real = -2*d_result_SAT_value + readval_real;
// }
//// if (readval_real > debug_max_readval_real_after_check[k])
//// {
//// debug_max_readval_real_after_check[k] = readval_real;
//// }
//printf("read real d map base %d = %d\n", d_RESULT_REG_BASE_ADDR + k, readval_real);
readval_imag = d_map_base[d_RESULT_REG_IMAG_BASE_ADDR + k];
//printf("read imag before checking d map base %d = %d\n", d_RESULT_REG_BASE_ADDR + k, readval_imag);
//// if (readval_imag > debug_max_readval_imag[k])
//// {
//// debug_max_readval_imag[k] = readval_imag;
//// }
//
// if (readval_imag >= d_result_SAT_value) // 0x100000 (21 bits two's complement)
// {
// readval_imag = -2*d_result_SAT_value + readval_imag;
// }
//// if (readval_imag > debug_max_readval_imag_after_check[k])
//// {
//// debug_max_readval_imag_after_check[k] = readval_real;
//// }
//printf("read imag d map base %d = %d\n", d_RESULT_REG_BASE_ADDR + k, readval_imag);
readval_real = d_map_base[RESULT_REG_REAL_BASE_ADDR + k];
readval_imag = d_map_base[RESULT_REG_IMAG_BASE_ADDR + k];
d_corr_out[k] = gr_complex(readval_real, readval_imag);
// if (printcounter > 100)
// {
// printcounter = 0;
// for (int32_t ll=0;ll<d_n_correlators;ll++)
// {
// printf("debug_max_readval_real %d = %d\n", ll, debug_max_readval_real[ll]);
// printf("debug_max_readval_imag %d = %d\n", ll, debug_max_readval_imag[ll]);
// printf("debug_max_readval_real_%d after_check = %d\n", ll, debug_max_readval_real_after_check[ll]);
// printf("debug_max_readval_imag_%d after_check = %d\n", ll, debug_max_readval_imag_after_check[ll]);
// }
//
// }
// else
// {
// printcounter = printcounter + 1;
// }
}
if (d_track_pilot)
{
//printf("reading pilot !!!\n");
//readval_real = d_map_base[d_RESULT_REG_DATA_REAL_BASE_ADDR];
readval_real = d_map_base[d_RESULT_REG_REAL_BASE_ADDR + d_n_correlators];
// if (readval_real >= d_result_SAT_value) // 0x100000 (21 bits two's complement)
// {
// readval_real = -2*d_result_SAT_value + readval_real;
// }
//readval_imag = d_map_base[d_RESULT_REG_DATA_IMAG_BASE_ADDR];
readval_imag = d_map_base[d_RESULT_REG_IMAG_BASE_ADDR + d_n_correlators];
// if (readval_imag >= d_result_SAT_value) // 0x100000 (21 bits two's complement)
// {
// readval_imag = -2*d_result_SAT_value + readval_imag;
// }
d_Prompt_Data[0] = gr_complex(readval_real, readval_imag);
readval_real = d_map_base[RESULT_REG_REAL_BASE_ADDR + d_n_correlators];
readval_imag = d_map_base[RESULT_REG_IMAG_BASE_ADDR + d_n_correlators];
d_Prompt_Data[0] = gr_complex(readval_real, readval_imag);
}
}
@@ -711,9 +461,8 @@ void fpga_multicorrelator_8sc::read_tracking_gps_results(void)
void fpga_multicorrelator_8sc::unlock_channel(void)
{
// unlock the channel to let the next samples go through
//printf("www writing 1 to d map base %d = drop samples\n", d_DROP_SAMPLES_REG_ADDR);
d_map_base[d_DROP_SAMPLES_REG_ADDR] = 1; // unlock the channel
d_map_base[23] = 1; // set the tracking module back to idle
d_map_base[DROP_SAMPLES_REG_ADDR] = 1; // unlock the channel
d_map_base[STOP_TRACKING_REG_ADDR] = 1; // set the tracking module back to idle
}
void fpga_multicorrelator_8sc::close_device()
@@ -721,7 +470,7 @@ void fpga_multicorrelator_8sc::close_device()
auto *aux = const_cast<uint32_t *>(d_map_base);
if (munmap(static_cast<void *>(aux), PAGE_SIZE) == -1)
{
printf("Failed to unmap memory uio\n");
std::cout << "Failed to unmap memory uio" << std::endl;
}
close(d_device_descriptor);
}
@@ -730,20 +479,6 @@ void fpga_multicorrelator_8sc::close_device()
void fpga_multicorrelator_8sc::lock_channel(void)
{
// lock the channel for processing
//printf("www writing 0 to d map base %d = drop samples\n", d_DROP_SAMPLES_REG_ADDR);
d_map_base[d_DROP_SAMPLES_REG_ADDR] = 0; // lock the channel
d_map_base[DROP_SAMPLES_REG_ADDR] = 0; // lock the channel
}
//void fpga_multicorrelator_8sc::read_sample_counters(int32_t *sample_counter, int32_t *secondary_sample_counter, int32_t *counter_corr_0_in, int32_t *counter_corr_0_out)
//{
// *sample_counter = d_map_base[11];
// *secondary_sample_counter = d_map_base[8];
// *counter_corr_0_in = d_map_base[10];
// *counter_corr_0_out = d_map_base[9];
//
//}
//void fpga_multicorrelator_8sc::reset_multicorrelator(void)
//{
// d_map_base[14] = 2; // writing a 2 to d_map_base[14] resets the multicorrelator
//}

91
src/algorithms/tracking/libs/fpga_multicorrelator.h
View File

@@ -1,8 +1,8 @@
/*!
* \file fpga_multicorrelator_8sc.h
* \brief High optimized FPGA vector correlator class for lv_16sc_t (short int32_t complex)
* \brief High optimized FPGA vector correlator class
* \authors <ul>
* <li> Marc Majoral, 2017. mmajoral(at)cttc.cat
* <li> Marc Majoral, 2019. mmajoral(at)cttc.cat
* <li> Javier Arribas, 2016. jarribas(at)cttc.es
* </ul>
*
@@ -11,7 +11,7 @@
*
* -------------------------------------------------------------------------
*
* Copyright (C) 2010-2017 (see AUTHORS file for a list of contributors)
* Copyright (C) 2010-2019 (see AUTHORS file for a list of contributors)
*
* GNSS-SDR is a software defined Global Navigation
* Satellite Systems receiver
@@ -41,7 +41,31 @@
#include <volk_gnsssdr/volk_gnsssdr.h>
#include <cstdint>
#define MAX_LENGTH_DEVICEIO_NAME 50
// FPGA register addresses
// write addresses
#define CODE_PHASE_STEP_CHIPS_NUM_REG_ADDR 0
#define INITIAL_INDEX_REG_BASE_ADDR 1
#define INITIAL_INTERP_COUNTER_REG_BASE_ADDR 7
#define NSAMPLES_MINUS_1_REG_ADDR 13
#define CODE_LENGTH_MINUS_1_REG_ADDR 14
#define REM_CARR_PHASE_RAD_REG_ADDR 15
#define PHASE_STEP_RAD_REG_ADDR 16
#define PROG_MEMS_ADDR 17
#define DROP_SAMPLES_REG_ADDR 18
#define INITIAL_COUNTER_VALUE_REG_ADDR_LSW 19
#define INITIAL_COUNTER_VALUE_REG_ADDR_MSW 20
#define STOP_TRACKING_REG_ADDR 23
#define START_FLAG_ADDR 30
// read-write addresses
#define TEST_REG_ADDR 31
// read addresses
#define RESULT_REG_REAL_BASE_ADDR 1
#define RESULT_REG_IMAG_BASE_ADDR 7
#define SAMPLE_COUNTER_REG_ADDR_LSW 13
#define SAMPLE_COUNTER_REG_ADDR_MSW 14
/*!
* \brief Class that implements carrier wipe-off and correlators.
@@ -50,36 +74,26 @@ class fpga_multicorrelator_8sc
{
public:
fpga_multicorrelator_8sc(int32_t n_correlators, std::string device_name,
uint32_t device_base, int32_t *ca_codes, int32_t *data_codes, uint32_t code_length_chips, bool track_pilot, uint32_t multicorr_type, uint32_t code_samples_per_chip);
uint32_t device_base, int32_t *ca_codes, int32_t *data_codes, uint32_t code_length_chips, bool track_pilot, uint32_t multicorr_type, uint32_t code_samples_per_chip);
~fpga_multicorrelator_8sc();
//bool set_output_vectors(gr_complex* corr_out);
void set_output_vectors(gr_complex *corr_out, gr_complex *Prompt_Data);
// bool set_local_code_and_taps(
// int32_t code_length_chips, const int* local_code_in,
// float *shifts_chips, int32_t PRN);
//bool set_local_code_and_taps(
void set_local_code_and_taps(
// int32_t code_length_chips,
float *shifts_chips, float *prompt_data_shift, int32_t PRN);
//bool set_output_vectors(lv_16sc_t* corr_out);
float *shifts_chips, float *prompt_data_shift, int32_t PRN);
void update_local_code(float rem_code_phase_chips);
//bool Carrier_wipeoff_multicorrelator_resampler(
void Carrier_wipeoff_multicorrelator_resampler(
float rem_carrier_phase_in_rad, float phase_step_rad,
float carrier_phase_rate_step_rad,
float rem_code_phase_chips, float code_phase_step_chips,
float code_phase_rate_step_chips,
int32_t signal_length_samples);
float rem_carrier_phase_in_rad, float phase_step_rad,
float carrier_phase_rate_step_rad,
float rem_code_phase_chips, float code_phase_step_chips,
float code_phase_rate_step_chips,
int32_t signal_length_samples);
bool free();
void set_channel(uint32_t channel);
void set_initial_sample(uint64_t samples_offset);
uint64_t read_sample_counter();
void lock_channel(void);
void unlock_channel(void);
//void read_sample_counters(int32_t *sample_counter, int32_t *secondary_sample_counter, int32_t *counter_corr_0_in, int32_t *counter_corr_0_out); // debug
private:
//const int32_t *d_local_code_in;
gr_complex *d_corr_out;
gr_complex *d_Prompt_Data;
float *d_shifts_chips;
@@ -115,37 +129,11 @@ private:
int32_t *d_ca_codes;
int32_t *d_data_codes;
//uint32_t d_code_length; // nominal number of chips
uint32_t d_code_samples_per_chip;
bool d_track_pilot;
uint32_t d_multicorr_type;
// register addresses
// write-only regs
uint32_t d_CODE_PHASE_STEP_CHIPS_NUM_REG_ADDR;
uint32_t d_INITIAL_INDEX_REG_BASE_ADDR;
uint32_t d_INITIAL_INTERP_COUNTER_REG_BASE_ADDR;
uint32_t d_NSAMPLES_MINUS_1_REG_ADDR;
uint32_t d_CODE_LENGTH_MINUS_1_REG_ADDR;
uint32_t d_REM_CARR_PHASE_RAD_REG_ADDR;
uint32_t d_PHASE_STEP_RAD_REG_ADDR;
uint32_t d_PROG_MEMS_ADDR;
uint32_t d_DROP_SAMPLES_REG_ADDR;
uint32_t d_INITIAL_COUNTER_VALUE_REG_ADDR_LSW;
uint32_t d_INITIAL_COUNTER_VALUE_REG_ADDR_MSW;
uint32_t d_START_FLAG_ADDR;
// read-write regs
uint32_t d_TEST_REG_ADDR;
// read-only regs
uint32_t d_RESULT_REG_REAL_BASE_ADDR;
uint32_t d_RESULT_REG_IMAG_BASE_ADDR;
uint32_t d_RESULT_REG_DATA_REAL_BASE_ADDR;
uint32_t d_RESULT_REG_DATA_IMAG_BASE_ADDR;
uint32_t d_SAMPLE_COUNTER_REG_ADDR_LSW;
uint32_t d_SAMPLE_COUNTER_REG_ADDR_MSW;
// private functions
uint32_t fpga_acquisition_test_register(uint32_t writeval);
void fpga_configure_tracking_gps_local_code(int32_t PRN);
@@ -155,17 +143,8 @@ private:
void fpga_configure_signal_parameters_in_fpga(void);
void fpga_launch_multicorrelator_fpga(void);
void read_tracking_gps_results(void);
//void reset_multicorrelator(void);
void close_device(void);
uint32_t d_result_SAT_value;
int32_t debug_max_readval_real[5] = {0, 0, 0, 0, 0};
int32_t debug_max_readval_imag[5] = {0, 0, 0, 0, 0};
int32_t debug_max_readval_real_after_check[5] = {0, 0, 0, 0, 0};
int32_t debug_max_readval_imag_after_check[5] = {0, 0, 0, 0, 0};
int32_t printcounter = 0;
};
#endif /* GNSS_SDR_FPGA_MULTICORRELATOR_H_ */