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Carles Fernandez 2019-04-14 00:03:59 +02:00
commit 8673e1dacd
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15 changed files with 347 additions and 304 deletions
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2
src/algorithms/acquisition/adapters/galileo_e5a_pcps_acquisition_fpga.cc
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@ -189,7 +189,7 @@ GalileoE5aPcpsAcquisitionFpga::GalileoE5aPcpsAcquisitionFpga(ConfigurationInterf
channel_ = 0;
doppler_step_ = 0;
gnss_synchro_ = nullptr;
// temporary buffers that we can delete
delete[] code;
delete fft_if;

2
src/algorithms/acquisition/adapters/gps_l1_ca_pcps_acquisition_fpga.cc
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@ -158,7 +158,7 @@ GpsL1CaPcpsAcquisitionFpga::GpsL1CaPcpsAcquisitionFpga(
acq_parameters.all_fft_codes = d_all_fft_codes_;
// reference for the FPGA FFT-IFFT attenuation factor
acq_parameters.total_block_exp = configuration_->property(role + ".total_block_exp", 11);
acq_parameters.total_block_exp = configuration_->property(role + ".total_block_exp", 10);
acq_parameters.num_doppler_bins_step2 = configuration_->property(role + ".second_nbins", 4);
acq_parameters.doppler_step2 = configuration_->property(role + ".second_doppler_step", 125.0);

4
src/algorithms/acquisition/adapters/gps_l5i_pcps_acquisition_fpga.cc
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@ -161,7 +161,7 @@ GpsL5iPcpsAcquisitionFpga::GpsL5iPcpsAcquisitionFpga(
acq_parameters.all_fft_codes = d_all_fft_codes_;
// reference for the FPGA FFT-IFFT attenuation factor
acq_parameters.total_block_exp = configuration_->property(role + ".total_block_exp", 11);
acq_parameters.total_block_exp = configuration_->property(role + ".total_block_exp", 13);
acq_parameters.num_doppler_bins_step2 = configuration_->property(role + ".second_nbins", 4);
acq_parameters.doppler_step2 = configuration_->property(role + ".second_doppler_step", 125.0);
@ -172,7 +172,7 @@ GpsL5iPcpsAcquisitionFpga::GpsL5iPcpsAcquisitionFpga(
channel_ = 0;
doppler_step_ = 0;
gnss_synchro_ = nullptr;
// temporary buffers that we can delete
delete[] code;
delete fft_if;

6
src/algorithms/acquisition/gnuradio_blocks/pcps_acquisition_fpga.cc
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@ -85,11 +85,7 @@ pcps_acquisition_fpga::pcps_acquisition_fpga(pcpsconf_fpga_t conf_)
}
pcps_acquisition_fpga::~pcps_acquisition_fpga()
{
acquisition_fpga->free();
}
pcps_acquisition_fpga::~pcps_acquisition_fpga() = default;
void pcps_acquisition_fpga::set_local_code()
{

29
src/algorithms/acquisition/libs/fpga_acquisition.cc
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@ -53,6 +53,7 @@
#define MEM_LOCAL_CODE_WR_ENABLE 0x0C000000 // command to enable the ENA and WR pins of the internal memory of the multicorrelator
#define POW_2_2 4 // 2^2 (used for the conversion of floating point numbers to integers)
#define POW_2_31 2147483648 // 2^31 (used for the conversion of floating point numbers to integers)
#define ENABLE_INT_ON_RESET 2 // flag that causes the acquisition to trigger an interrupt when it is reset.
#define SELECT_LSBits 0x0000FFFF // Select the 10 LSbits out of a 20-bit word
#define SELECT_MSBbits 0xFFFF0000 // Select the 10 MSbits out of a 20-bit word
@ -150,12 +151,6 @@ void Fpga_Acquisition::open_device()
}
bool Fpga_Acquisition::free()
{
return true;
}
void Fpga_Acquisition::fpga_acquisition_test_register()
{
// sanity check : check test register
@ -256,33 +251,31 @@ void Fpga_Acquisition::read_acquisition_results(uint32_t *max_index,
uint64_t readval_long = 0;
uint64_t readval_long_shifted = 0;
readval = d_map_base[1];
readval = d_map_base[1]; // read sample counter (LSW)
initial_sample_tmp = readval;
readval_long = d_map_base[2];
readval_long = d_map_base[2]; // read sample counter (MSW)
readval_long_shifted = readval_long << 32; // 2^32
initial_sample_tmp = initial_sample_tmp + readval_long_shifted; // 2^32
*initial_sample = initial_sample_tmp;
readval = d_map_base[3];
readval = d_map_base[3]; // read first peak value
*firstpeak = static_cast<float>(readval);
readval = d_map_base[4];
readval = d_map_base[4]; // read second peak value
*secondpeak = static_cast<float>(readval);
readval = d_map_base[5];
readval = d_map_base[5]; // read max index position
*max_index = readval;
*power_sum = 0;
readval = d_map_base[8];
*total_blk_exp = readval;
*power_sum = 0; // power sum is not used
readval = d_map_base[7]; // read doppler index -- this read releases the interrupt line
*doppler_index = readval;
readval = d_map_base[15]; // read dummy (to be removed)
readval = d_map_base[8]; // read FFT block exponent
*total_blk_exp = readval;
}
@ -311,7 +304,9 @@ void Fpga_Acquisition::close_device()
void Fpga_Acquisition::reset_acquisition(void)
{
d_map_base[8] = RESET_ACQUISITION; // writing a 2 to d_map_base[8] resets the multicorrelator
d_map_base[8] = RESET_ACQUISITION; // writing a 2 to d_map_base[8] resets the acquisition. This causes a reset of all
// the FPGA HW modules including the multicorrelators
d_map_base[14] = ENABLE_INT_ON_RESET; // enable int on reset
}

1
src/algorithms/acquisition/libs/fpga_acquisition.h
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@ -58,7 +58,6 @@ public:
~Fpga_Acquisition();
bool set_local_code(uint32_t PRN);
bool free();
void set_doppler_sweep(uint32_t num_sweeps, uint32_t doppler_step, int32_t doppler_min);
void run_acquisition(void);

7
src/algorithms/signal_source/adapters/labsat_signal_source.cc
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@ -40,21 +40,20 @@ LabsatSignalSource::LabsatSignalSource(ConfigurationInterface* configuration,
const std::string& role, unsigned int in_stream, unsigned int out_stream, gr::msg_queue::sptr queue) : role_(role), in_stream_(in_stream), out_stream_(out_stream), queue_(std::move(queue))
{
std::string default_item_type = "gr_complex";
std::string default_dump_file = "./data/source.bin";
std::string default_dump_file = "./labsat_output.dat";
item_type_ = configuration->property(role + ".item_type", default_item_type);
dump_ = configuration->property(role + ".dump", false);
dump_filename_ = configuration->property(role + ".dump_filename", default_dump_file);
int channel_selector = configuration->property(role + ".selected_channel", 1);
std::string default_filename = "./example_capture.LS3";
samples_ = configuration->property(role + ".samples", 0);
std::string default_filename = "./example_capture.LS3";
filename_ = configuration->property(role + ".filename", default_filename);
if (item_type_ == "gr_complex")
{
item_size_ = sizeof(gr_complex);
labsat23_source_ = labsat23_make_source(filename_.c_str(), channel_selector);
labsat23_source_ = labsat23_make_source_sptr(filename_.c_str(), channel_selector, queue_);
DLOG(INFO) << "Item size " << item_size_;
DLOG(INFO) << "labsat23_source_(" << labsat23_source_->unique_id() << ")";
}

1
src/algorithms/signal_source/adapters/labsat_signal_source.h
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@ -81,7 +81,6 @@ private:
unsigned int out_stream_;
std::string item_type_;
size_t item_size_;
uint64_t samples_;
std::string filename_;
bool dump_;
std::string dump_filename_;

1
src/algorithms/signal_source/gnuradio_blocks/CMakeLists.txt
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@ -64,6 +64,7 @@ target_link_libraries(signal_source_gr_blocks
Gnuradio::runtime
signal_source_libs
PRIVATE
core_receiver
Gflags::gflags
Glog::glog
)

101
src/algorithms/signal_source/gnuradio_blocks/labsat23_source.cc
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@ -30,30 +30,25 @@
#include "labsat23_source.h"
#include "control_message_factory.h"
#include <gnuradio/io_signature.h>
#include <exception>
#include <iostream>
#include <sstream>
labsat23_source_sptr labsat23_make_source(const char *signal_file_basename, int channel_selector)
labsat23_source_sptr labsat23_make_source_sptr(const char *signal_file_basename, int channel_selector, gr::msg_queue::sptr queue)
{
return labsat23_source_sptr(new labsat23_source(signal_file_basename, channel_selector));
}
std::string labsat23_source::generate_filename()
{
std::ostringstream ss;
ss << std::setw(4) << std::setfill('0') << d_current_file_number;
return d_signal_file_basename + "_" + ss.str() + ".LS3";
return labsat23_source_sptr(new labsat23_source(signal_file_basename, channel_selector, queue));
}
labsat23_source::labsat23_source(const char *signal_file_basename,
int channel_selector) : gr::block("labsat23_source",
gr::io_signature::make(0, 0, 0),
gr::io_signature::make(1, 1, sizeof(gr_complex)))
int channel_selector,
gr::msg_queue::sptr queue) : gr::block("labsat23_source",
gr::io_signature::make(0, 0, 0),
gr::io_signature::make(1, 1, sizeof(gr_complex))),
d_queue(queue)
{
if (channel_selector < 1 or channel_selector > 2)
{
@ -108,6 +103,25 @@ labsat23_source::~labsat23_source()
}
std::string labsat23_source::generate_filename()
{
if (d_signal_file_basename.substr(d_signal_file_basename.length() - 4, 4) == ".ls2" or d_signal_file_basename.substr(d_signal_file_basename.length() - 4, 4) == ".LS2")
{
if (d_current_file_number == 0)
{
return d_signal_file_basename;
}
else
{
return std::string("donotexist"); // just to stop processing
}
}
std::ostringstream ss;
ss << std::setw(4) << std::setfill('0') << d_current_file_number;
return d_signal_file_basename + "_" + ss.str() + ".LS3";
}
int labsat23_source::getBit(uint8_t byte, int position)
{
return (byte >> position) & 0x01;
@ -120,7 +134,7 @@ void labsat23_source::decode_samples_one_channel(int16_t input_short, gr_complex
switch (type)
{
case 2:
//two bits per sample, 8 samples per int16
// two bits per sample, 8 samples per int16
for (int i = 0; i < 8; i++)
{
out[i] = gr_complex(static_cast<float>(bs[15 - (2 * i)]),
@ -129,45 +143,45 @@ void labsat23_source::decode_samples_one_channel(int16_t input_short, gr_complex
}
break;
case 4:
//four bits per sample, 4 samples per int16
// bits per sample, 4 samples per int16
for (int i = 0; i < 4; i++)
{
out[i] = gr_complex(0.0, 0.0);
//In-Phase
// In-Phase
if (bs[15 - 4 * i])
{
if (bs[13 - 4 * i]) //11
if (bs[13 - 4 * i]) // 11
{
out[i] += gr_complex(-1, 0);
}
else //10
else // 10
{
out[i] += gr_complex(-2, 0);
}
}
else
{
if (bs[13 - 4 * i]) //01
if (bs[13 - 4 * i]) // 01
{
out[i] += gr_complex(1, 0);
}
}
//Quadrature
// Quadrature
if (bs[14 - 4 * i])
{
if (bs[12 - 4 * i]) //11
if (bs[12 - 4 * i]) // 11
{
out[i] += gr_complex(0, -1);
}
else //10
else // 10
{
out[i] += gr_complex(0, -2);
}
}
else
{
if (bs[12 - 4 * i]) //01
if (bs[12 - 4 * i]) // 01
{
out[i] += gr_complex(0, 1);
}
@ -192,8 +206,8 @@ int labsat23_source::general_work(int noutput_items,
{
char memblock[1024];
binary_input_file->read(memblock, 1024);
//parse Labsat header
//check preamble
// parse Labsat header
// check preamble
int byte_counter = 0;
bool preamble_ok = true;
for (int i = 0; i < 8; i++)
@ -388,7 +402,6 @@ int labsat23_source::general_work(int noutput_items,
return -1;
}
// ready to start reading samples
switch (d_bits_per_sample)
{
@ -419,8 +432,10 @@ int labsat23_source::general_work(int noutput_items,
}
// trigger the read of the next file in the sequence
std::cout << "End of current file, reading the next Labsat file in sequence: " << generate_filename() << std::endl;
if (d_labsat_version == 3)
{
std::cout << "End of current file, reading the next Labsat file in sequence: " << generate_filename() << std::endl;
}
d_current_file_number++;
binary_input_file->close();
binary_input_file->open(generate_filename().c_str(), std::ios::in | std::ios::binary);
@ -430,7 +445,17 @@ int labsat23_source::general_work(int noutput_items,
}
else
{
std::cout << "Last file reached, LabSat source stop" << std::endl;
if (d_labsat_version == 3)
{
std::cout << "Last file reached, LabSat source stop" << std::endl;
}
else
{
std::cout << "End of file reached, LabSat source stop" << std::endl;
}
auto *cmf = new ControlMessageFactory();
d_queue->handle(cmf->GetQueueMessage(200, 0));
delete cmf;
return -1;
}
}
@ -468,8 +493,10 @@ int labsat23_source::general_work(int noutput_items,
}
// trigger the read of the next file in the sequence
std::cout << "End of current file, reading the next Labsat file in sequence: " << generate_filename() << std::endl;
if (d_labsat_version == 3)
{
std::cout << "End of current file, reading the next Labsat file in sequence: " << generate_filename() << std::endl;
}
d_current_file_number++;
binary_input_file->close();
binary_input_file->open(generate_filename().c_str(), std::ios::in | std::ios::binary);
@ -479,7 +506,17 @@ int labsat23_source::general_work(int noutput_items,
}
else
{
std::cout << "Last file reached, LabSat source stop" << std::endl;
if (d_labsat_version == 3)
{
std::cout << "Last file reached, LabSat source stop" << std::endl;
}
else
{
std::cout << "End of file reached, LabSat source stop" << std::endl;
}
auto *cmf = new ControlMessageFactory();
d_queue->handle(cmf->GetQueueMessage(200, 0));
delete cmf;
return -1;
}
}

8
src/algorithms/signal_source/gnuradio_blocks/labsat23_source.h
View File

@ -32,6 +32,7 @@
#define GNSS_SDR_LABSAT23_SOURCE_H
#include <gnuradio/block.h>
#include <gnuradio/msg_queue.h> // for msg_queue, msg_queue::sptr
#include <cstdint>
#include <fstream>
#include <string>
@ -41,7 +42,7 @@ class labsat23_source;
using labsat23_source_sptr = boost::shared_ptr<labsat23_source>;
labsat23_source_sptr labsat23_make_source(const char *signal_file_basename, int channel_selector);
labsat23_source_sptr labsat23_make_source_sptr(const char *signal_file_basename, int channel_selector, gr::msg_queue::sptr queue);
/*!
* \brief This class implements conversion between Labsat2 and 3 format byte packet samples to gr_complex
@ -49,7 +50,8 @@ labsat23_source_sptr labsat23_make_source(const char *signal_file_basename, int
class labsat23_source : public gr::block
{
private:
friend labsat23_source_sptr labsat23_make_source_sptr(const char *signal_file_basename, int channel_selector);
friend labsat23_source_sptr labsat23_make_source_sptr(const char *signal_file_basename, int channel_selector, gr::msg_queue::sptr queue);
labsat23_source(const char *signal_file_basename, int channel_selector, gr::msg_queue::sptr queue);
std::string generate_filename();
void decode_samples_one_channel(int16_t input_short, gr_complex *out, int type);
int getBit(uint8_t byte, int position);
@ -62,9 +64,9 @@ private:
std::ifstream *binary_input_file;
uint8_t d_ref_clock;
uint8_t d_bits_per_sample;
gr::msg_queue::sptr d_queue;
public:
labsat23_source(const char *signal_file_basename, int channel_selector);
~labsat23_source();
int general_work(int noutput_items,
gr_vector_int &ninput_items,

410
src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.cc
View File

@ -33,7 +33,6 @@
*
* -------------------------------------------------------------------------
*/
#include "dll_pll_veml_tracking_fpga.h"
#include "GPS_L1_CA.h"
#include "GPS_L2C.h"
@ -61,7 +60,6 @@
#include <iostream>
#include <map>
dll_pll_veml_tracking_fpga_sptr dll_pll_veml_make_tracking_fpga(const Dll_Pll_Conf_Fpga &conf_)
{
return dll_pll_veml_tracking_fpga_sptr(new dll_pll_veml_tracking_fpga(conf_));
@ -272,7 +270,7 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
// Initialize tracking ==========================================
d_code_loop_filter = Tracking_loop_filter(d_code_period, trk_parameters.dll_bw_hz, trk_parameters.dll_filter_order, false);
printf("trk_parameters.fll_bw_hz = %f trk_parameters.pll_bw_hz = %f trk_parameters.pll_filter_order = %d\n", trk_parameters.fll_bw_hz, trk_parameters.pll_bw_hz, trk_parameters.pll_filter_order);
//printf("trk_parameters.fll_bw_hz = %f trk_parameters.pll_bw_hz = %f trk_parameters.pll_filter_order = %d\n", trk_parameters.fll_bw_hz, trk_parameters.pll_bw_hz, trk_parameters.pll_filter_order);
d_carrier_loop_filter.set_params(trk_parameters.fll_bw_hz, trk_parameters.pll_bw_hz, trk_parameters.pll_filter_order);
if (d_veml)
@ -369,7 +367,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
d_carrier_phase_step_rad = 0.0;
d_carrier_phase_rate_step_rad = 0.0;
d_rem_code_phase_chips = 0.0;
d_last_prompt = gr_complex(0.0, 0.0);
d_state = 0; // initial state: standby
clear_tracking_vars();
@ -479,6 +476,7 @@ void dll_pll_veml_tracking_fpga::start_tracking()
// filter initialization
d_carrier_loop_filter.initialize(static_cast<float>(d_acq_carrier_doppler_hz)); // initialize the carrier filter
// enable tracking pull-in
@ -648,13 +646,11 @@ void dll_pll_veml_tracking_fpga::run_dll_pll()
{
// Costas loop discriminator, insensitive to 180 deg phase transitions
d_carr_phase_error_hz = pll_cloop_two_quadrant_atan(d_P_accu) / PI_2;
d_carr_error_hz = pll_cloop_two_quadrant_atan(d_P_accu) / PI_2;
}
else
{
// Secondary code acquired. No symbols transition should be present in the signal
d_carr_phase_error_hz = pll_four_quadrant_atan(d_P_accu) / PI_2;
d_carr_error_hz = pll_four_quadrant_atan(d_P_accu) / PI_2;
}
if ((d_pull_in_transitory == true and trk_parameters.enable_fll_pull_in == true) or trk_parameters.enable_fll_steady_state)
@ -713,14 +709,12 @@ void dll_pll_veml_tracking_fpga::clear_tracking_vars()
d_P_accu_old = gr_complex(0.0, 0.0);
d_carr_phase_error_hz = 0.0;
d_carr_freq_error_hz = 0.0;
d_carr_error_hz = 0.0;
d_carr_error_filt_hz = 0.0;
d_code_error_chips = 0.0;
d_code_error_filt_chips = 0.0;
d_current_symbol = 0;
d_Prompt_circular_buffer.clear();
//d_Prompt_buffer_deque.clear();
d_last_prompt = gr_complex(0.0, 0.0);
d_carrier_phase_rate_step_rad = 0.0;
d_code_phase_rate_step_chips = 0.0;
d_carr_ph_history.clear();
@ -740,6 +734,8 @@ void dll_pll_veml_tracking_fpga::update_tracking_vars()
K_blk_samples = T_prn_samples + d_rem_code_phase_samples;
//d_next_prn_length_samples = static_cast<int32_t>(std::floor(K_blk_samples)); // round to a discrete number of samples
d_next_prn_length_samples = static_cast<int32_t>(std::floor(K_blk_samples)); // round to a discrete number of samples
//int32_t actual_prn_length_samples = static_cast<int32_t>(std::floor(K_blk_samples));
//d_next_prn_length_samples = actual_prn_length_samples + (actual_prn_length_samples - d_current_prn_length_samples);
//################### PLL COMMANDS #################################################
// carrier phase step (NCO phase increment per sample) [rads/sample]
@ -1267,8 +1263,6 @@ void dll_pll_veml_tracking_fpga::set_gnss_synchro(Gnss_Synchro *p_gnss_synchro)
d_acquisition_gnss_synchro = p_gnss_synchro;
if (p_gnss_synchro->PRN > 0)
{
//std::cout << "Acquisition is about to start " << std::endl;
// When using the FPGA the SW only reads the sample counter during active tracking in order to spare CPU clock cycles.
d_sample_counter = 0;
d_sample_counter_next = 0;
@ -1277,8 +1271,6 @@ void dll_pll_veml_tracking_fpga::set_gnss_synchro(Gnss_Synchro *p_gnss_synchro)
d_code_ph_history.clear();
// DLL/PLL filter initialization
d_code_loop_filter.initialize(); // initialize the code filter
d_carr_ph_history.clear();
@ -1331,16 +1323,16 @@ void dll_pll_veml_tracking_fpga::set_gnss_synchro(Gnss_Synchro *p_gnss_synchro)
d_current_correlation_time_s = d_code_period;
// DLL/PLL filter initialization
d_carrier_loop_filter.set_params(trk_parameters.fll_bw_hz, trk_parameters.pll_bw_hz, trk_parameters.pll_filter_order);
d_code_loop_filter.set_noise_bandwidth(trk_parameters.dll_bw_hz);
d_code_loop_filter.set_update_interval(d_code_period);
d_code_loop_filter.initialize(); // initialize the code filter
multicorrelator_fpga->set_local_code_and_taps(d_local_code_shift_chips, d_prompt_data_shift, d_acquisition_gnss_synchro->PRN);
d_pull_in_transitory = true;
//d_Prompt_buffer_deque.clear();
d_last_prompt = gr_complex(0.0, 0.0);
d_cloop = true;
d_Prompt_circular_buffer.clear();
@ -1388,7 +1380,6 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
*out[0] = *d_acquisition_gnss_synchro;
usleep(1000);
return 1;
break;
}
case 1: // Pull-in
{
@ -1427,20 +1418,20 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
current_synchro_data.Tracking_sample_counter = absolute_samples_offset;
d_sample_counter_next = d_sample_counter;
// Doppler effect Fd = (C / (C + Vr)) * F
double radial_velocity = (d_signal_carrier_freq + d_acq_carrier_doppler_hz) / d_signal_carrier_freq;
// new chip and PRN sequence periods based on acq Doppler
d_code_freq_chips = radial_velocity * d_code_chip_rate;
d_code_phase_step_chips = d_code_freq_chips / trk_parameters.fs_in;
d_code_phase_rate_step_chips = 0.0;
double T_chip_mod_seconds = 1.0 / d_code_freq_chips;
double T_prn_mod_seconds = T_chip_mod_seconds * static_cast<double>(d_code_length_chips);
double T_prn_mod_samples = T_prn_mod_seconds * trk_parameters.fs_in;
//double T_chip_mod_seconds = 1.0 / d_code_freq_chips;
//double T_prn_mod_seconds = T_chip_mod_seconds * static_cast<double>(d_code_length_chips);
//double T_prn_mod_samples = T_prn_mod_seconds * trk_parameters.fs_in;
d_acq_code_phase_samples = absolute_samples_offset;
d_current_prn_length_samples = round(T_prn_mod_samples);
//d_current_prn_length_samples = round(T_prn_mod_samples);
d_current_prn_length_samples = trk_parameters.vector_length;
d_next_prn_length_samples = d_current_prn_length_samples;
int32_t samples_offset = round(d_acq_code_phase_samples);
@ -1456,14 +1447,197 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
DLOG(INFO) << "PULL-IN Doppler [Hz] = " << d_carrier_doppler_hz
<< ". PULL-IN Code Phase [samples] = " << d_acq_code_phase_samples;
// don't leave the HW module blocking the signal path before the first sample arrives
// start the first tracking process
run_state_2(current_synchro_data);
break;
*out[0] = *d_acquisition_gnss_synchro;
return 1;
}
case 2: // Wide tracking and symbol synchronization
{
run_state_2(current_synchro_data);
d_sample_counter = d_sample_counter_next;
d_sample_counter_next = d_sample_counter + static_cast<uint64_t>(d_current_prn_length_samples);
do_correlation_step();
// Save single correlation step variables
if (d_veml)
{
d_VE_accu = *d_Very_Early;
d_VL_accu = *d_Very_Late;
}
d_E_accu = *d_Early;
d_P_accu = *d_Prompt;
d_L_accu = *d_Late;
// Check lock status
if (!cn0_and_tracking_lock_status(d_code_period))
{
clear_tracking_vars();
d_state = 0; // loss-of-lock detected
}
else
{
bool next_state = false;
// Perform DLL/PLL tracking loop computations. Costas Loop enabled
run_dll_pll();
update_tracking_vars();
// enable write dump file this cycle (valid DLL/PLL cycle)
log_data(false);
if (d_secondary)
{
// ####### SECONDARY CODE LOCK #####
d_Prompt_circular_buffer.push_back(*d_Prompt);
if (d_Prompt_circular_buffer.size() == d_secondary_code_length)
{
next_state = acquire_secondary();
if (next_state)
{
LOG(INFO) << systemName << " " << signal_pretty_name << " secondary code locked in channel " << d_channel
<< " for satellite " << Gnss_Satellite(systemName, d_acquisition_gnss_synchro->PRN) << std::endl;
std::cout << systemName << " " << signal_pretty_name << " secondary code locked in channel " << d_channel
<< " for satellite " << Gnss_Satellite(systemName, d_acquisition_gnss_synchro->PRN) << std::endl;
}
}
}
else if (d_symbols_per_bit > 1) //Signal does not have secondary code. Search a bit transition by sign change
{
float current_tracking_time_s = static_cast<float>(d_sample_counter - d_absolute_samples_offset) / trk_parameters.fs_in;
if (current_tracking_time_s > 10)
{
d_symbol_history.push_back(d_Prompt->real());
//******* preamble correlation ********
int32_t corr_value = 0;
if ((static_cast<int32_t>(d_symbol_history.size()) == d_preamble_length_symbols)) // and (d_make_correlation or !d_flag_frame_sync))
{
int i = 0;
for (const auto &iter : d_symbol_history)
{
if (iter < 0.0) // symbols clipping
{
corr_value -= d_preambles_symbols[i];
}
else
{
corr_value += d_preambles_symbols[i];
}
i++;
}
}
if (corr_value == d_preamble_length_symbols)
{
LOG(INFO) << systemName << " " << signal_pretty_name << " tracking preamble detected in channel " << d_channel
<< " for satellite " << Gnss_Satellite(systemName, d_acquisition_gnss_synchro->PRN) << std::endl;
next_state = true;
}
else
{
next_state = false;
}
}
else
{
next_state = false;
}
}
else
{
next_state = true;
}
// ########### Output the tracking results to Telemetry block ##########
if (interchange_iq)
{
if (trk_parameters.track_pilot)
{
// Note that data and pilot components are in quadrature. I and Q are interchanged
current_synchro_data.Prompt_I = static_cast<double>((*d_Prompt_Data).imag());
current_synchro_data.Prompt_Q = static_cast<double>((*d_Prompt_Data).real());
}
else
{
current_synchro_data.Prompt_I = static_cast<double>((*d_Prompt).imag());
current_synchro_data.Prompt_Q = static_cast<double>((*d_Prompt).real());
}
}
else
{
if (trk_parameters.track_pilot)
{
// Note that data and pilot components are in quadrature. I and Q are interchanged
current_synchro_data.Prompt_I = static_cast<double>((*d_Prompt_Data).real());
current_synchro_data.Prompt_Q = static_cast<double>((*d_Prompt_Data).imag());
}
else
{
current_synchro_data.Prompt_I = static_cast<double>((*d_Prompt).real());
current_synchro_data.Prompt_Q = static_cast<double>((*d_Prompt).imag());
}
}
current_synchro_data.Code_phase_samples = d_rem_code_phase_samples;
current_synchro_data.Carrier_phase_rads = d_acc_carrier_phase_rad;
current_synchro_data.Carrier_Doppler_hz = d_carrier_doppler_hz;
current_synchro_data.CN0_dB_hz = d_CN0_SNV_dB_Hz;
current_synchro_data.Flag_valid_symbol_output = true;
current_synchro_data.correlation_length_ms = d_correlation_length_ms;
if (next_state)
{ // reset extended correlator
d_VE_accu = gr_complex(0.0, 0.0);
d_E_accu = gr_complex(0.0, 0.0);
d_P_accu = gr_complex(0.0, 0.0);
d_L_accu = gr_complex(0.0, 0.0);
d_VL_accu = gr_complex(0.0, 0.0);
d_Prompt_circular_buffer.clear();
d_current_symbol = 0;
if (d_enable_extended_integration)
{
// UPDATE INTEGRATION TIME
d_extend_correlation_symbols_count = 0;
d_current_correlation_time_s = static_cast<float>(trk_parameters.extend_correlation_symbols) * static_cast<float>(d_code_period);
d_state = 3; // next state is the extended correlator integrator
LOG(INFO) << "Enabled " << trk_parameters.extend_correlation_symbols * static_cast<int32_t>(d_code_period * 1000.0) << " ms extended correlator in channel "
<< d_channel
<< " for satellite " << Gnss_Satellite(systemName, d_acquisition_gnss_synchro->PRN);
std::cout << "Enabled " << trk_parameters.extend_correlation_symbols * static_cast<int32_t>(d_code_period * 1000.0) << " ms extended correlator in channel "
<< d_channel
<< " for satellite " << Gnss_Satellite(systemName, d_acquisition_gnss_synchro->PRN) << std::endl;
// Set narrow taps delay values [chips]
d_code_loop_filter.set_update_interval(d_current_correlation_time_s);
d_code_loop_filter.set_noise_bandwidth(trk_parameters.dll_bw_narrow_hz);
d_carrier_loop_filter.set_params(trk_parameters.fll_bw_hz, trk_parameters.pll_bw_narrow_hz, trk_parameters.pll_filter_order);
if (d_veml)
{
d_local_code_shift_chips[0] = -trk_parameters.very_early_late_space_narrow_chips * static_cast<float>(d_code_samples_per_chip);
d_local_code_shift_chips[1] = -trk_parameters.early_late_space_narrow_chips * static_cast<float>(d_code_samples_per_chip);
d_local_code_shift_chips[3] = trk_parameters.early_late_space_narrow_chips * static_cast<float>(d_code_samples_per_chip);
d_local_code_shift_chips[4] = trk_parameters.very_early_late_space_narrow_chips * static_cast<float>(d_code_samples_per_chip);
}
else
{
d_local_code_shift_chips[0] = -trk_parameters.early_late_space_narrow_chips * static_cast<float>(d_code_samples_per_chip);
d_local_code_shift_chips[2] = trk_parameters.early_late_space_narrow_chips * static_cast<float>(d_code_samples_per_chip);
}
}
else
{
d_state = 4;
}
}
}
break;
}
case 3: // coherent integration (correlation time extension)
@ -1473,6 +1647,7 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
// Fill the acquisition data
current_synchro_data = *d_acquisition_gnss_synchro;
// perform a correlation step
do_correlation_step();
update_tracking_vars();
@ -1603,186 +1778,3 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
}
return 0;
}
void dll_pll_veml_tracking_fpga::run_state_2(Gnss_Synchro &current_synchro_data)
{
d_sample_counter = d_sample_counter_next;
d_sample_counter_next = d_sample_counter + static_cast<uint64_t>(d_current_prn_length_samples);
do_correlation_step();
// Save single correlation step variables
if (d_veml)
{
d_VE_accu = *d_Very_Early;
d_VL_accu = *d_Very_Late;
}
d_E_accu = *d_Early;
d_P_accu = *d_Prompt;
d_L_accu = *d_Late;
// Check lock status
if (!cn0_and_tracking_lock_status(d_code_period))
{
clear_tracking_vars();
d_state = 0; // loss-of-lock detected
}
else
{
bool next_state = false;
// Perform DLL/PLL tracking loop computations. Costas Loop enabled
run_dll_pll();
update_tracking_vars();
// enable write dump file this cycle (valid DLL/PLL cycle)
log_data(false);
if (d_secondary)
{
// ####### SECONDARY CODE LOCK #####
d_Prompt_circular_buffer.push_back(*d_Prompt);
//d_Prompt_buffer_deque.push_back(*d_Prompt);
//if (d_Prompt_buffer_deque.size() == d_secondary_code_length)
if (d_Prompt_circular_buffer.size() == d_secondary_code_length)
{
next_state = acquire_secondary();
if (next_state)
{
LOG(INFO) << systemName << " " << signal_pretty_name << " secondary code locked in channel " << d_channel
<< " for satellite " << Gnss_Satellite(systemName, d_acquisition_gnss_synchro->PRN) << std::endl;
std::cout << systemName << " " << signal_pretty_name << " secondary code locked in channel " << d_channel
<< " for satellite " << Gnss_Satellite(systemName, d_acquisition_gnss_synchro->PRN) << std::endl;
}
//d_Prompt_buffer_deque.pop_front();
}
}
else if (d_symbols_per_bit > 1) //Signal does not have secondary code. Search a bit transition by sign change
{
float current_tracking_time_s = static_cast<float>(d_sample_counter - d_absolute_samples_offset) / trk_parameters.fs_in;
if (current_tracking_time_s > 10)
{
d_symbol_history.push_back(d_Prompt->real());
//******* preamble correlation ********
int32_t corr_value = 0;
if ((d_symbol_history.size() == GPS_CA_PREAMBLE_LENGTH_SYMBOLS)) // and (d_make_correlation or !d_flag_frame_sync))
{
int i = 0;
for (const auto &iter : d_symbol_history)
{
if (iter < 0.0) // symbols clipping
{
corr_value -= d_preambles_symbols[i];
}
else
{
corr_value += d_preambles_symbols[i];
}
i++;
}
}
if (corr_value == GPS_CA_PREAMBLE_LENGTH_SYMBOLS)
{
LOG(INFO) << systemName << " " << signal_pretty_name << " tracking preamble detected in channel " << d_channel
<< " for satellite " << Gnss_Satellite(systemName, d_acquisition_gnss_synchro->PRN) << std::endl;
next_state = true;
}
else
{
next_state = false;
}
}
else
{
next_state = false;
}
}
else
{
next_state = true;
}
// ########### Output the tracking results to Telemetry block ##########
if (interchange_iq)
{
if (trk_parameters.track_pilot)
{
// Note that data and pilot components are in quadrature. I and Q are interchanged
current_synchro_data.Prompt_I = static_cast<double>((*d_Prompt_Data).imag());
current_synchro_data.Prompt_Q = static_cast<double>((*d_Prompt_Data).real());
}
else
{
current_synchro_data.Prompt_I = static_cast<double>((*d_Prompt).imag());
current_synchro_data.Prompt_Q = static_cast<double>((*d_Prompt).real());
}
}
else
{
if (trk_parameters.track_pilot)
{
// Note that data and pilot components are in quadrature. I and Q are interchanged
current_synchro_data.Prompt_I = static_cast<double>((*d_Prompt_Data).real());
current_synchro_data.Prompt_Q = static_cast<double>((*d_Prompt_Data).imag());
}
else
{
current_synchro_data.Prompt_I = static_cast<double>((*d_Prompt).real());
current_synchro_data.Prompt_Q = static_cast<double>((*d_Prompt).imag());
}
}
current_synchro_data.Code_phase_samples = d_rem_code_phase_samples;
current_synchro_data.Carrier_phase_rads = d_acc_carrier_phase_rad;
current_synchro_data.Carrier_Doppler_hz = d_carrier_doppler_hz;
current_synchro_data.CN0_dB_hz = d_CN0_SNV_dB_Hz;
current_synchro_data.Flag_valid_symbol_output = true;
current_synchro_data.correlation_length_ms = d_correlation_length_ms;
if (next_state)
{ // reset extended correlator
d_VE_accu = gr_complex(0.0, 0.0);
d_E_accu = gr_complex(0.0, 0.0);
d_P_accu = gr_complex(0.0, 0.0);
d_L_accu = gr_complex(0.0, 0.0);
d_VL_accu = gr_complex(0.0, 0.0);
d_Prompt_circular_buffer.clear();
d_current_symbol = 0;
d_last_prompt = gr_complex(0.0, 0.0);
//d_Prompt_buffer_deque.clear();
if (d_enable_extended_integration)
{
// UPDATE INTEGRATION TIME
d_extend_correlation_symbols_count = 0;
d_current_correlation_time_s = static_cast<float>(trk_parameters.extend_correlation_symbols) * static_cast<float>(d_code_period);
d_state = 3; // next state is the extended correlator integrator
LOG(INFO) << "Enabled " << trk_parameters.extend_correlation_symbols * static_cast<int32_t>(d_code_period * 1000.0) << " ms extended correlator in channel "
<< d_channel
<< " for satellite " << Gnss_Satellite(systemName, d_acquisition_gnss_synchro->PRN);
std::cout << "Enabled " << trk_parameters.extend_correlation_symbols * static_cast<int32_t>(d_code_period * 1000.0) << " ms extended correlator in channel "
<< d_channel
<< " for satellite " << Gnss_Satellite(systemName, d_acquisition_gnss_synchro->PRN) << std::endl;
// Set narrow taps delay values [chips]
d_code_loop_filter.set_update_interval(d_current_correlation_time_s);
d_code_loop_filter.set_noise_bandwidth(trk_parameters.dll_bw_narrow_hz);
d_carrier_loop_filter.set_params(trk_parameters.fll_bw_hz, trk_parameters.pll_bw_narrow_hz, trk_parameters.pll_filter_order);
if (d_veml)
{
d_local_code_shift_chips[0] = -trk_parameters.very_early_late_space_narrow_chips * static_cast<float>(d_code_samples_per_chip);
d_local_code_shift_chips[1] = -trk_parameters.early_late_space_narrow_chips * static_cast<float>(d_code_samples_per_chip);
d_local_code_shift_chips[3] = trk_parameters.early_late_space_narrow_chips * static_cast<float>(d_code_samples_per_chip);
d_local_code_shift_chips[4] = trk_parameters.very_early_late_space_narrow_chips * static_cast<float>(d_code_samples_per_chip);
}
else
{
d_local_code_shift_chips[0] = -trk_parameters.early_late_space_narrow_chips * static_cast<float>(d_code_samples_per_chip);
d_local_code_shift_chips[2] = trk_parameters.early_late_space_narrow_chips * static_cast<float>(d_code_samples_per_chip);
}
}
else
{
d_state = 4;
}
}
}
}

4
src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.h
View File

@ -91,7 +91,7 @@ private:
void log_data(bool integrating);
int32_t save_matfile();
void run_state_2(Gnss_Synchro &current_synchro_data);
//void run_state_2(Gnss_Synchro &current_synchro_data);
// tracking configuration vars
Dll_Pll_Conf_Fpga trk_parameters;
@ -146,7 +146,6 @@ private:
gr_complex d_P_accu_old;
gr_complex d_L_accu;
gr_complex d_VL_accu;
gr_complex d_last_prompt;
gr_complex *d_Prompt_Data;
@ -173,7 +172,6 @@ private:
double d_current_correlation_time_s;
double d_carr_phase_error_hz;
double d_carr_freq_error_hz;
double d_carr_error_hz;
double d_carr_error_filt_hz;
double d_code_error_chips;
double d_code_error_filt_chips;

68
src/algorithms/tracking/libs/fpga_multicorrelator.cc
View File

@ -58,7 +58,8 @@
#define LOCAL_CODE_FPGA_CLEAR_ADDRESS_COUNTER 0x10000000
#define LOCAL_CODE_FPGA_ENABLE_WRITE_MEMORY 0x0C000000
#define TEST_REGISTER_TRACK_WRITEVAL 0x55AA
#define ENABLE_TRK_INT_ON_RESET 1 /* flag that causes the tracking HW accelerator to trigger an interrupt when it is reset. It is used \
to avoid a potential deadlock caused by the SW waiting for an interrupt from the FPGA when the HW is reset */
#ifndef TEMP_FAILURE_RETRY
#define TEMP_FAILURE_RETRY(exp) \
({ \
@ -174,26 +175,27 @@ void Fpga_Multicorrelator_8sc::set_output_vectors(gr_complex *corr_out, gr_compl
void Fpga_Multicorrelator_8sc::update_local_code()
{
//d_rem_code_phase_chips = rem_code_phase_chips;
Fpga_Multicorrelator_8sc::fpga_compute_code_shift_parameters();
Fpga_Multicorrelator_8sc::fpga_configure_code_parameters_in_fpga();
}
void Fpga_Multicorrelator_8sc::Carrier_wipeoff_multicorrelator_resampler(
float rem_carrier_phase_in_rad,
float phase_step_rad,
float carrier_phase_rate_step_rad __attribute__((unused)),
float rem_code_phase_chips,
float code_phase_step_chips __attribute__((unused)),
float code_phase_rate_step_chips __attribute__((unused)),
int32_t signal_length_samples)
float rem_carrier_phase_in_rad, // nco phase initial position
float phase_step_rad, // nco phase step
float carrier_phase_rate_step_rad __attribute__((unused)), // nco phase step rate change
float rem_code_phase_chips, // code resampler initial position
float code_phase_step_chips __attribute__((unused)), // code resampler step
float code_phase_rate_step_chips __attribute__((unused)), // code resampler step rate
int32_t signal_length_samples) // number of samples
{
d_rem_code_phase_chips = rem_code_phase_chips;
d_rem_carrier_phase_in_rad = rem_carrier_phase_in_rad;
d_code_phase_step_chips = code_phase_step_chips;
d_phase_step_rad = phase_step_rad;
d_correlator_length_samples = signal_length_samples;
d_rem_carrier_phase_in_rad = rem_carrier_phase_in_rad; // nco phase initial position
d_phase_step_rad = phase_step_rad; // nco phase step
d_carrier_phase_rate_step_rad = carrier_phase_rate_step_rad; // nco phase step rate
d_rem_code_phase_chips = rem_code_phase_chips; // code resampler initial position
d_code_phase_step_chips = code_phase_step_chips; // code resampler step
d_code_phase_rate_step_chips = code_phase_rate_step_chips; // code resampler step rate
d_correlator_length_samples = signal_length_samples; // number of samples
Fpga_Multicorrelator_8sc::update_local_code();
Fpga_Multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga();
Fpga_Multicorrelator_8sc::fpga_configure_signal_parameters_in_fpga();
@ -281,6 +283,16 @@ void Fpga_Multicorrelator_8sc::set_channel(uint32_t channel)
{
LOG(INFO) << "Test register sanity check success !";
}
d_map_base[INT_ON_RST_REG_ADDR] = ENABLE_TRK_INT_ON_RESET; // enable interrupts on reset to prevent deadlock
// enable interrupts
int32_t reenable = 1;
ssize_t nbytes = TEMP_FAILURE_RETRY(write(d_device_descriptor, reinterpret_cast<void *>(&reenable), sizeof(int32_t)));
if (nbytes != sizeof(int32_t))
{
std::cerr << "Error launching the FPGA multicorrelator" << std::endl;
}
}
@ -383,6 +395,7 @@ void Fpga_Multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga(void)
float d_rem_carrier_phase_in_rad_temp;
d_code_phase_step_chips_num = static_cast<uint32_t>(roundf(MAX_CODE_RESAMPLER_COUNTER * d_code_phase_step_chips));
d_code_phase_rate_step_chips_num = static_cast<uint32_t>(roundf(MAX_CODE_RESAMPLER_COUNTER * d_code_phase_rate_step_chips));
if (d_rem_carrier_phase_in_rad > M_PI)
{
@ -399,30 +412,35 @@ void Fpga_Multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga(void)
d_rem_carr_phase_rad_int = static_cast<int32_t>(roundf((d_rem_carrier_phase_in_rad_temp)*PHASE_CARR_MAX_div_PI));
d_phase_step_rad_int = static_cast<int32_t>(roundf((d_phase_step_rad)*PHASE_CARR_MAX_div_PI)); // the FPGA accepts a range for the phase step between -pi and +pi
d_carrier_phase_rate_step_rad_int = static_cast<int32_t>(roundf((d_carrier_phase_rate_step_rad)*PHASE_CARR_MAX_div_PI));
}
void Fpga_Multicorrelator_8sc::fpga_configure_signal_parameters_in_fpga(void)
{
d_map_base[CODE_PHASE_STEP_CHIPS_NUM_REG_ADDR] = d_code_phase_step_chips_num;
d_map_base[CODE_PHASE_STEP_CHIPS_NUM_REG_ADDR] = d_code_phase_step_chips_num; // code phase step
d_map_base[NSAMPLES_MINUS_1_REG_ADDR] = d_correlator_length_samples - 1;
d_map_base[CODE_PHASE_STEP_CHIPS_RATE] = d_code_phase_rate_step_chips_num; // code phase step rate
d_map_base[REM_CARR_PHASE_RAD_REG_ADDR] = d_rem_carr_phase_rad_int;
d_map_base[NSAMPLES_MINUS_1_REG_ADDR] = d_correlator_length_samples - 1; // number of samples
d_map_base[PHASE_STEP_RAD_REG_ADDR] = d_phase_step_rad_int;
d_map_base[REM_CARR_PHASE_RAD_REG_ADDR] = d_rem_carr_phase_rad_int; // initial nco phase
d_map_base[PHASE_STEP_RAD_REG_ADDR] = d_phase_step_rad_int; // nco phase step
d_map_base[PHASE_STEP_RATE_REG_ADDR] = d_carrier_phase_rate_step_rad_int; // nco phase step rate
}
void Fpga_Multicorrelator_8sc::fpga_launch_multicorrelator_fpga(void)
{
// enable interrupts
int32_t reenable = 1;
ssize_t nbytes = TEMP_FAILURE_RETRY(write(d_device_descriptor, reinterpret_cast<void *>(&reenable), sizeof(int32_t)));
if (nbytes != sizeof(int32_t))
{
std::cerr << "Error launching the FPGA multicorrelator" << std::endl;
}
// // enable interrupts
// int32_t reenable = 1;
// ssize_t nbytes = TEMP_FAILURE_RETRY(write(d_device_descriptor, reinterpret_cast<void *>(&reenable), sizeof(int32_t)));
// if (nbytes != sizeof(int32_t))
// {
// std::cerr << "Error launching the FPGA multicorrelator" << std::endl;
// }
// writing 1 to reg 14 launches the tracking
d_map_base[START_FLAG_ADDR] = 1;
}

7
src/algorithms/tracking/libs/fpga_multicorrelator.h
View File

@ -54,7 +54,10 @@
#define DROP_SAMPLES_REG_ADDR 18
#define INITIAL_COUNTER_VALUE_REG_ADDR_LSW 19
#define INITIAL_COUNTER_VALUE_REG_ADDR_MSW 20
#define CODE_PHASE_STEP_CHIPS_RATE 21
#define PHASE_STEP_RATE_REG_ADDR 22
#define STOP_TRACKING_REG_ADDR 23
#define INT_ON_RST_REG_ADDR 24 // cause interrupt on reset to prevent deadlock
#define START_FLAG_ADDR 30
// read-write addresses
#define TEST_REG_ADDR 31
@ -109,15 +112,19 @@ private:
uint32_t d_correlator_length_samples;
float d_rem_code_phase_chips;
float d_code_phase_step_chips;
float d_code_phase_rate_step_chips;
float d_rem_carrier_phase_in_rad;
float d_phase_step_rad;
float d_carrier_phase_rate_step_rad;
// configuration data computed in the format that the FPGA expects
uint32_t *d_initial_index;
uint32_t *d_initial_interp_counter;
uint32_t d_code_phase_step_chips_num;
uint32_t d_code_phase_rate_step_chips_num;
int32_t d_rem_carr_phase_rad_int;
int32_t d_phase_step_rad_int;
int32_t d_carrier_phase_rate_step_rad_int;
uint64_t d_initial_sample_counter;
// driver