diff --git a/docs/CHANGELOG.md b/docs/CHANGELOG.md index 1a3b673d8..54e188f73 100644 --- a/docs/CHANGELOG.md +++ b/docs/CHANGELOG.md @@ -98,12 +98,14 @@ All notable changes to GNSS-SDR will be documented in this file. - Added a new output parameter `Flag_PLL_180_deg_phase_locked` in the monitor output that indicates if the PLL got locked at 180 degrees, so the symbol sign is reversed. -- Fix bug in the satellite selection algorithm for configurations with a large - number of channels. The maximum number of channels per signal is now limited - to the number of available satellites per system minus one. The number of - channels performing concurrent acquisition, `Channels.in_acquisition`, cannot - be larger than the total number of channels. The program will stop if those - requirements are not met in the configuration file. +- Fixed a bug in the satellite selection algorithm for configurations with a + large number of channels. The maximum number of channels per signal is now + limited to the number of available satellites per system minus one. The number + of channels performing concurrent acquisition, `Channels.in_acquisition`, + cannot be larger than the total number of channels. The program will stop if + those requirements are not met in the configuration file. +- Fixed program termination when using `File_Signal_Source` and extended + integration times. See the definitions of concepts and metrics at https://gnss-sdr.org/design-forces/ diff --git a/src/algorithms/signal_source/adapters/ad9361_fpga_signal_source.cc b/src/algorithms/signal_source/adapters/ad9361_fpga_signal_source.cc index 029f82e5c..c78e6da94 100644 --- a/src/algorithms/signal_source/adapters/ad9361_fpga_signal_source.cc +++ b/src/algorithms/signal_source/adapters/ad9361_fpga_signal_source.cc @@ -1,8 +1,11 @@ /*! * \file ad9361_fpga_signal_source.cc - * \brief signal source for Analog Devices front-end AD9361 connected directly to FPGA accelerators. - * This source implements only the AD9361 control. It is NOT compatible with conventional SDR acquisition and tracking blocks. - * Please use the fmcomms2 source if conventional SDR acquisition and tracking is selected in the configuration file. + * \brief signal source for Analog Devices front-end AD9361 connected directly + * to FPGA accelerators. + * This source implements only the AD9361 control. It is NOT compatible with + * conventional SDR acquisition and tracking blocks. + * Please use the fmcomms2 source if conventional SDR acquisition and tracking + * is selected in the configuration file. * \authors