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https://github.com/gnss-sdr/gnss-sdr
synced 2024-12-14 20:20:35 +00:00
removed integrating parameter from log_data()
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parent
3095176524
commit
718fc03442
@ -97,7 +97,7 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
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this->set_msg_handler(pmt::mp("telemetry_to_trk"), boost::bind(&dll_pll_veml_tracking_fpga::msg_handler_telemetry_to_trk, this, _1));
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this->set_msg_handler(pmt::mp("telemetry_to_trk"), boost::bind(&dll_pll_veml_tracking_fpga::msg_handler_telemetry_to_trk, this, _1));
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// initialize internal vars
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// initialize internal vars
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d_dll_filt_history.set_capacity(2000);
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d_dll_filt_history.set_capacity(1000);
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d_veml = false;
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d_veml = false;
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d_cloop = true;
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d_cloop = true;
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d_pull_in_transitory = true;
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d_pull_in_transitory = true;
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@ -1153,7 +1153,7 @@ void dll_pll_veml_tracking_fpga::save_correlation_results_extended_integration_i
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}
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}
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}
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}
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void dll_pll_veml_tracking_fpga::log_data(bool integrating)
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void dll_pll_veml_tracking_fpga::log_data()
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{
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{
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if (d_dump)
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if (d_dump)
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{
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{
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@ -1203,20 +1203,20 @@ void dll_pll_veml_tracking_fpga::log_data(bool integrating)
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tmp_E = std::abs<float>(d_E_accu);
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tmp_E = std::abs<float>(d_E_accu);
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tmp_P = std::abs<float>(d_P_accu);
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tmp_P = std::abs<float>(d_P_accu);
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tmp_L = std::abs<float>(d_L_accu);
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tmp_L = std::abs<float>(d_L_accu);
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if (integrating)
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// if (integrating)
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{
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// {
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//TODO: Improve this solution!
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// //TODO: Improve this solution!
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// It compensates the amplitude difference while integrating
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// // It compensates the amplitude difference while integrating
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if (d_extend_correlation_symbols_count > 0)
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// if (d_extend_correlation_symbols_count > 0)
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{
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// {
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float scale_factor = static_cast<float>(trk_parameters.extend_correlation_symbols) / static_cast<float>(d_extend_correlation_symbols_count);
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// float scale_factor = static_cast<float>(trk_parameters.extend_correlation_symbols) / static_cast<float>(d_extend_correlation_symbols_count);
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tmp_VE *= scale_factor;
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// tmp_VE *= scale_factor;
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tmp_E *= scale_factor;
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// tmp_E *= scale_factor;
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tmp_P *= scale_factor;
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// tmp_P *= scale_factor;
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tmp_L *= scale_factor;
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// tmp_L *= scale_factor;
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tmp_VL *= scale_factor;
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// tmp_VL *= scale_factor;
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}
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// }
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}
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// }
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try
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try
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{
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{
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@ -1280,7 +1280,7 @@ void dll_pll_veml_tracking_fpga::log_data(bool integrating)
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}
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}
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void dll_pll_veml_tracking_fpga::log_data_extended_integration_in_FPGA(bool integrating, bool extended_correlation_in_fpga_enabled)
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void dll_pll_veml_tracking_fpga::log_data_extended_integration_in_FPGA(bool extended_correlation_in_fpga_enabled)
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{
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{
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if (d_dump)
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if (d_dump)
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{
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{
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@ -2032,7 +2032,7 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
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d_num_current_syncrho_repetitions = 1;
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d_num_current_syncrho_repetitions = 1;
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// enable write dump file this cycle (valid DLL/PLL cycle)
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// enable write dump file this cycle (valid DLL/PLL cycle)
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log_data(false);
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log_data();
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if (d_secondary)
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if (d_secondary)
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{
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{
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@ -2278,7 +2278,7 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
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d_state = 4;
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d_state = 4;
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}
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}
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d_num_current_syncrho_repetitions = 1;
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d_num_current_syncrho_repetitions = 1;
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log_data(true);
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log_data();
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break;
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break;
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}
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}
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case 4: // narrow tracking
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case 4: // narrow tracking
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@ -2343,7 +2343,7 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
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d_num_current_syncrho_repetitions = 1;
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d_num_current_syncrho_repetitions = 1;
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log_data(false);
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log_data();
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// reset extended correlator
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// reset extended correlator
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d_VE_accu = gr_complex(0.0, 0.0);
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d_VE_accu = gr_complex(0.0, 0.0);
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d_E_accu = gr_complex(0.0, 0.0);
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d_E_accu = gr_complex(0.0, 0.0);
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@ -2430,7 +2430,7 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
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}
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}
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log_data_extended_integration_in_FPGA(false, true);
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log_data_extended_integration_in_FPGA(true);
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break;
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break;
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}
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}
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@ -2513,7 +2513,7 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
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d_extend_correlation_symbols_count = 0;
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d_extend_correlation_symbols_count = 0;
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// enable write dump file this cycle (valid DLL/PLL cycle)
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// enable write dump file this cycle (valid DLL/PLL cycle)
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log_data_extended_integration_in_FPGA(false, true);
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log_data_extended_integration_in_FPGA(true);
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// reset extended correlator
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// reset extended correlator
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d_VE_accu = gr_complex(0.0, 0.0);
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d_VE_accu = gr_complex(0.0, 0.0);
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d_E_accu = gr_complex(0.0, 0.0);
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d_E_accu = gr_complex(0.0, 0.0);
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@ -92,8 +92,8 @@ private:
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void clear_tracking_vars();
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void clear_tracking_vars();
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void save_correlation_results();
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void save_correlation_results();
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void save_correlation_results_extended_integration_in_FPGA();
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void save_correlation_results_extended_integration_in_FPGA();
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void log_data(bool integrating);
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void log_data();
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void log_data_extended_integration_in_FPGA(bool integrating, bool extended_correlation_in_fpga_enabled);
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void log_data_extended_integration_in_FPGA(bool extended_correlation_in_fpga_enabled);
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int32_t save_matfile();
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int32_t save_matfile();
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//void run_state_2(Gnss_Synchro ¤t_synchro_data);
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//void run_state_2(Gnss_Synchro ¤t_synchro_data);
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@ -112,12 +112,14 @@ private:
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double d_code_period;
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double d_code_period;
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double d_code_chip_rate;
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double d_code_chip_rate;
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uint32_t d_secondary_code_length;
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uint32_t d_secondary_code_length;
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uint32_t d_data_secondary_code_length;
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uint32_t d_code_length_chips;
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uint32_t d_code_length_chips;
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uint32_t d_code_samples_per_chip; // All signals have 1 sample per chip code except Gal. E1 which has 2 (CBOC disabled) or 12 (CBOC enabled)
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uint32_t d_code_samples_per_chip; // All signals have 1 sample per chip code except Gal. E1 which has 2 (CBOC disabled) or 12 (CBOC enabled)
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int32_t d_symbols_per_bit;
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int32_t d_symbols_per_bit;
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std::string systemName;
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std::string systemName;
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std::string signal_type;
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std::string signal_type;
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std::string *d_secondary_code_string;
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std::string *d_secondary_code_string;
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std::string *d_data_secondary_code_string;
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std::string signal_pretty_name;
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std::string signal_pretty_name;
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int32_t *d_preambles_symbols;
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int32_t *d_preambles_symbols;
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@ -146,6 +148,8 @@ private:
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bool d_enable_extended_integration;
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bool d_enable_extended_integration;
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int32_t d_extend_correlation_symbols_count;
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int32_t d_extend_correlation_symbols_count;
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int32_t d_current_symbol;
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int32_t d_current_symbol;
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int32_t d_current_data_symbol;
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gr_complex d_VE_accu;
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gr_complex d_VE_accu;
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gr_complex d_E_accu;
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gr_complex d_E_accu;
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@ -157,6 +161,7 @@ private:
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// gr_complex d_P_data_accu; // when the extended integration is done in the FPGA we need to accumulate the pilot correlator results too
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// gr_complex d_P_data_accu; // when the extended integration is done in the FPGA we need to accumulate the pilot correlator results too
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uint32_t d_num_current_syncrho_repetitions;
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uint32_t d_num_current_syncrho_repetitions;
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gr_complex d_P_data_accu;
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gr_complex *d_Prompt_Data;
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gr_complex *d_Prompt_Data;
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double d_code_phase_step_chips;
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double d_code_phase_step_chips;
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