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mirror of https://github.com/gnss-sdr/gnss-sdr synced 2024-12-14 20:20:35 +00:00

removed integrating parameter from log_data()

This commit is contained in:
Marc Majoral 2019-07-09 20:11:21 +02:00
parent 3095176524
commit 718fc03442
2 changed files with 29 additions and 24 deletions

View File

@ -97,7 +97,7 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
this->set_msg_handler(pmt::mp("telemetry_to_trk"), boost::bind(&dll_pll_veml_tracking_fpga::msg_handler_telemetry_to_trk, this, _1)); this->set_msg_handler(pmt::mp("telemetry_to_trk"), boost::bind(&dll_pll_veml_tracking_fpga::msg_handler_telemetry_to_trk, this, _1));
// initialize internal vars // initialize internal vars
d_dll_filt_history.set_capacity(2000); d_dll_filt_history.set_capacity(1000);
d_veml = false; d_veml = false;
d_cloop = true; d_cloop = true;
d_pull_in_transitory = true; d_pull_in_transitory = true;
@ -1153,7 +1153,7 @@ void dll_pll_veml_tracking_fpga::save_correlation_results_extended_integration_i
} }
} }
void dll_pll_veml_tracking_fpga::log_data(bool integrating) void dll_pll_veml_tracking_fpga::log_data()
{ {
if (d_dump) if (d_dump)
{ {
@ -1203,20 +1203,20 @@ void dll_pll_veml_tracking_fpga::log_data(bool integrating)
tmp_E = std::abs<float>(d_E_accu); tmp_E = std::abs<float>(d_E_accu);
tmp_P = std::abs<float>(d_P_accu); tmp_P = std::abs<float>(d_P_accu);
tmp_L = std::abs<float>(d_L_accu); tmp_L = std::abs<float>(d_L_accu);
if (integrating) // if (integrating)
{ // {
//TODO: Improve this solution! // //TODO: Improve this solution!
// It compensates the amplitude difference while integrating // // It compensates the amplitude difference while integrating
if (d_extend_correlation_symbols_count > 0) // if (d_extend_correlation_symbols_count > 0)
{ // {
float scale_factor = static_cast<float>(trk_parameters.extend_correlation_symbols) / static_cast<float>(d_extend_correlation_symbols_count); // float scale_factor = static_cast<float>(trk_parameters.extend_correlation_symbols) / static_cast<float>(d_extend_correlation_symbols_count);
tmp_VE *= scale_factor; // tmp_VE *= scale_factor;
tmp_E *= scale_factor; // tmp_E *= scale_factor;
tmp_P *= scale_factor; // tmp_P *= scale_factor;
tmp_L *= scale_factor; // tmp_L *= scale_factor;
tmp_VL *= scale_factor; // tmp_VL *= scale_factor;
} // }
} // }
try try
{ {
@ -1280,7 +1280,7 @@ void dll_pll_veml_tracking_fpga::log_data(bool integrating)
} }
void dll_pll_veml_tracking_fpga::log_data_extended_integration_in_FPGA(bool integrating, bool extended_correlation_in_fpga_enabled) void dll_pll_veml_tracking_fpga::log_data_extended_integration_in_FPGA(bool extended_correlation_in_fpga_enabled)
{ {
if (d_dump) if (d_dump)
{ {
@ -2032,7 +2032,7 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
d_num_current_syncrho_repetitions = 1; d_num_current_syncrho_repetitions = 1;
// enable write dump file this cycle (valid DLL/PLL cycle) // enable write dump file this cycle (valid DLL/PLL cycle)
log_data(false); log_data();
if (d_secondary) if (d_secondary)
{ {
@ -2278,7 +2278,7 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
d_state = 4; d_state = 4;
} }
d_num_current_syncrho_repetitions = 1; d_num_current_syncrho_repetitions = 1;
log_data(true); log_data();
break; break;
} }
case 4: // narrow tracking case 4: // narrow tracking
@ -2343,7 +2343,7 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
d_num_current_syncrho_repetitions = 1; d_num_current_syncrho_repetitions = 1;
log_data(false); log_data();
// reset extended correlator // reset extended correlator
d_VE_accu = gr_complex(0.0, 0.0); d_VE_accu = gr_complex(0.0, 0.0);
d_E_accu = gr_complex(0.0, 0.0); d_E_accu = gr_complex(0.0, 0.0);
@ -2430,7 +2430,7 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
} }
log_data_extended_integration_in_FPGA(false, true); log_data_extended_integration_in_FPGA(true);
break; break;
} }
@ -2513,7 +2513,7 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
d_extend_correlation_symbols_count = 0; d_extend_correlation_symbols_count = 0;
// enable write dump file this cycle (valid DLL/PLL cycle) // enable write dump file this cycle (valid DLL/PLL cycle)
log_data_extended_integration_in_FPGA(false, true); log_data_extended_integration_in_FPGA(true);
// reset extended correlator // reset extended correlator
d_VE_accu = gr_complex(0.0, 0.0); d_VE_accu = gr_complex(0.0, 0.0);
d_E_accu = gr_complex(0.0, 0.0); d_E_accu = gr_complex(0.0, 0.0);

View File

@ -92,8 +92,8 @@ private:
void clear_tracking_vars(); void clear_tracking_vars();
void save_correlation_results(); void save_correlation_results();
void save_correlation_results_extended_integration_in_FPGA(); void save_correlation_results_extended_integration_in_FPGA();
void log_data(bool integrating); void log_data();
void log_data_extended_integration_in_FPGA(bool integrating, bool extended_correlation_in_fpga_enabled); void log_data_extended_integration_in_FPGA(bool extended_correlation_in_fpga_enabled);
int32_t save_matfile(); int32_t save_matfile();
//void run_state_2(Gnss_Synchro &current_synchro_data); //void run_state_2(Gnss_Synchro &current_synchro_data);
@ -112,12 +112,14 @@ private:
double d_code_period; double d_code_period;
double d_code_chip_rate; double d_code_chip_rate;
uint32_t d_secondary_code_length; uint32_t d_secondary_code_length;
uint32_t d_data_secondary_code_length;
uint32_t d_code_length_chips; uint32_t d_code_length_chips;
uint32_t d_code_samples_per_chip; // All signals have 1 sample per chip code except Gal. E1 which has 2 (CBOC disabled) or 12 (CBOC enabled) uint32_t d_code_samples_per_chip; // All signals have 1 sample per chip code except Gal. E1 which has 2 (CBOC disabled) or 12 (CBOC enabled)
int32_t d_symbols_per_bit; int32_t d_symbols_per_bit;
std::string systemName; std::string systemName;
std::string signal_type; std::string signal_type;
std::string *d_secondary_code_string; std::string *d_secondary_code_string;
std::string *d_data_secondary_code_string;
std::string signal_pretty_name; std::string signal_pretty_name;
int32_t *d_preambles_symbols; int32_t *d_preambles_symbols;
@ -146,6 +148,8 @@ private:
bool d_enable_extended_integration; bool d_enable_extended_integration;
int32_t d_extend_correlation_symbols_count; int32_t d_extend_correlation_symbols_count;
int32_t d_current_symbol; int32_t d_current_symbol;
int32_t d_current_data_symbol;
gr_complex d_VE_accu; gr_complex d_VE_accu;
gr_complex d_E_accu; gr_complex d_E_accu;
@ -157,6 +161,7 @@ private:
// gr_complex d_P_data_accu; // when the extended integration is done in the FPGA we need to accumulate the pilot correlator results too // gr_complex d_P_data_accu; // when the extended integration is done in the FPGA we need to accumulate the pilot correlator results too
uint32_t d_num_current_syncrho_repetitions; uint32_t d_num_current_syncrho_repetitions;
gr_complex d_P_data_accu;
gr_complex *d_Prompt_Data; gr_complex *d_Prompt_Data;
double d_code_phase_step_chips; double d_code_phase_step_chips;