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https://github.com/gnss-sdr/gnss-sdr
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- set output vectors is only done in the class constructor, no need to do it continuously
- no need to multiply by two the results of the multicorrelator HW accelerators
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@ -172,6 +172,8 @@ Gps_L1_Ca_Dll_Pll_Tracking_fpga_sc::Gps_L1_Ca_Dll_Pll_Tracking_fpga_sc(
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d_carrier_phase_step_rad = 0.0;
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d_carrier_phase_step_rad = 0.0;
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set_relative_rate(1.0 / static_cast<double>(d_vector_length));
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set_relative_rate(1.0 / static_cast<double>(d_vector_length));
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multicorrelator_fpga_8sc->set_output_vectors(d_correlator_outs);
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}
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}
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void Gps_L1_Ca_Dll_Pll_Tracking_fpga_sc::start_tracking()
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void Gps_L1_Ca_Dll_Pll_Tracking_fpga_sc::start_tracking()
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@ -320,7 +322,6 @@ int Gps_L1_Ca_Dll_Pll_Tracking_fpga_sc::general_work (int noutput_items __attrib
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// ################# CARRIER WIPEOFF AND CORRELATORS ##############################
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// ################# CARRIER WIPEOFF AND CORRELATORS ##############################
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// perform carrier wipe-off and compute Early, Prompt and Late correlation
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// perform carrier wipe-off and compute Early, Prompt and Late correlation
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multicorrelator_fpga_8sc->set_output_vectors(d_correlator_outs);
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multicorrelator_fpga_8sc->Carrier_wipeoff_multicorrelator_resampler(
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multicorrelator_fpga_8sc->Carrier_wipeoff_multicorrelator_resampler(
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d_rem_carr_phase_rad, d_carrier_phase_step_rad,
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d_rem_carr_phase_rad, d_carrier_phase_step_rad,
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d_rem_code_phase_chips, d_code_phase_step_chips,
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d_rem_code_phase_chips, d_code_phase_step_chips,
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@ -403,14 +403,12 @@ void fpga_multicorrelator_8sc::read_tracking_gps_results(void)
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{
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{
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readval_real = -2097152 + readval_real;
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readval_real = -2097152 + readval_real;
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}
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}
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readval_real = readval_real * 2; // the results are shifted two bits to the left due to the complex multiplier in the FPGA
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readval_imag = d_map_base[1 + d_n_correlators + k];
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readval_imag = d_map_base[1 + d_n_correlators + k];
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if (readval_imag >= 1048576) // 0x100000 (21 bits two's complement)
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if (readval_imag >= 1048576) // 0x100000 (21 bits two's complement)
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{
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{
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readval_imag = -2097152 + readval_imag;
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readval_imag = -2097152 + readval_imag;
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}
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}
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readval_imag = readval_imag * 2; // the results are shifted two bits to the left due to the complex multiplier in the FPGA
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d_corr_out[k] = gr_complex(readval_real,readval_imag);
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d_corr_out[k] = gr_complex(readval_real,readval_imag);
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}
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}
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}
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}
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