diff --git a/src/algorithms/signal_source/adapters/max2771_evkit_signal_source_fpga.cc b/src/algorithms/signal_source/adapters/max2771_evkit_signal_source_fpga.cc index 17959efef..6aaafa414 100644 --- a/src/algorithms/signal_source/adapters/max2771_evkit_signal_source_fpga.cc +++ b/src/algorithms/signal_source/adapters/max2771_evkit_signal_source_fpga.cc @@ -45,7 +45,7 @@ MAX2771EVKITSignalSourceFPGA::MAX2771EVKITSignalSourceFPGA(const ConfigurationIn freq0_(configuration->property(role + ".freq0", freq_)), freq1_(configuration->property(role + ".freq1", static_cast(GPS_L5_FREQ_HZ))), sample_rate_(configuration->property(role + ".sampling_frequency", default_sampling_rate)), - RF_channels_(configuration->property(role + ".RF_channels", 1)), + RF_channels_(configuration->property(role + ".RF_channels", DEFAULT_NUM_FREQ_BANDS)), in_stream_(in_stream), out_stream_(out_stream), bandwidth_(configuration->property(role + ".bandwidth", DEFAULT_BANDWIDTH)), @@ -75,13 +75,13 @@ MAX2771EVKITSignalSourceFPGA::MAX2771EVKITSignalSourceFPGA(const ConfigurationIn if (freq0_ != GPS_L1_FREQ_HZ) { std::string freq_name = (RF_channels_ == 1) ? "freq" : "freq0"; - std::cout << "Configuration parameter " << freq_name << " should take values " << GPS_L1_FREQ_HZ << ", " << GPS_L2_FREQ_HZ << ", or " << GPS_L5_FREQ_HZ << "\n"; - std::cout << "Error: provided value " << freq_name << " = " << freq0_ << " is not among valid values\n"; + std::cout << "Configuration parameter " << freq_name << " should take value " << GPS_L1_FREQ_HZ << "\n"; + std::cout << "Error: provided value " << freq_name << " = " << freq0_ << " is not a valid value\n"; std::cout << " This parameter has been set to its default value " << freq_name << " = " << GPS_L1_FREQ_HZ << '\n'; LOG(WARNING) << "Invalid configuration value for " << freq_name << " parameter. Set to " << freq_name << " = " << GPS_L1_FREQ_HZ; freq0_ = GPS_L1_FREQ_HZ; } - if (freq1_ != GPS_L2_FREQ_HZ and freq1_ != GPS_L5_FREQ_HZ) + if (freq1_ != GPS_L1_FREQ_HZ and freq1_ != GPS_L2_FREQ_HZ and freq1_ != GPS_L5_FREQ_HZ) { std::cout << "Configuration parameter freq1 should take values " << GPS_L1_FREQ_HZ << ", " << GPS_L2_FREQ_HZ << ", or " << GPS_L5_FREQ_HZ << "\n"; std::cout << "Error: provided value freq1 = " << freq1_ << " is not among valid values\n"; @@ -169,7 +169,7 @@ MAX2771EVKITSignalSourceFPGA::MAX2771EVKITSignalSourceFPGA(const ConfigurationIn std::string dump_filename = configuration->property(role + ".dump_filename", DEFAULT_BUFF_MON_FILENAME); - buffer_monitor_fpga = std::make_shared(NUM_FREQ_BANDS, dump_, dump_filename); + buffer_monitor_fpga = std::make_shared(DEFAULT_NUM_FREQ_BANDS, dump_, dump_filename); thread_buffer_monitor = std::thread([&] { run_buffer_monitor_process(); }); if (in_stream_ > 0) @@ -217,6 +217,8 @@ std::vector MAX2771EVKITSignalSourceFPGA::setup_regs(uint64_t freq) uint32_t Filter_order_sel = (filter_order_ == 5) ? 0x0 : 0x1; uint32_t IF_filter_gain_sel = (if_filter_gain_) ? 0x1 : 0x0; + uint32_t mixermode_sel = (freq == GPS_L1_FREQ_HZ) ? MIXERMODE_HIGH_BAND : MIXERMODE_LOW_BAND; + register_values[0] = // configuration 1 register (chipen_select << 31) + (IDLE << 30) + @@ -226,7 +228,7 @@ std::vector MAX2771EVKITSignalSourceFPGA::setup_regs(uint64_t freq) (0x1 << 18) + // reserved (MIXPOLE << 17) + (LNA_mode << 15) + - (MIXERMODE << 13) + + (mixermode_sel << 13) + (FCEN << 6) + (Filter_Bandwidth << 3) + (Filter_order_sel << 2) + @@ -293,9 +295,11 @@ std::vector MAX2771EVKITSignalSourceFPGA::setup_regs(uint64_t freq) clock_out_div_ratio = 0x1; // default XTAL frequency } + uint32_t loband_sel = (freq == GPS_L1_FREQ_HZ) ? LOBAND_L1 : LOBAND_L5; + register_values[3] = // PLL configuration register (clock_out_div_ratio << 29) + - (LOBAND << 28) + + (loband_sel << 28) + (0x1 << 27) + // reserved (0x0 << 26) + // reserved (0x0 << 25) + // reserved diff --git a/src/algorithms/signal_source/adapters/max2771_evkit_signal_source_fpga.h b/src/algorithms/signal_source/adapters/max2771_evkit_signal_source_fpga.h index e11112935..6aef07d38 100644 --- a/src/algorithms/signal_source/adapters/max2771_evkit_signal_source_fpga.h +++ b/src/algorithms/signal_source/adapters/max2771_evkit_signal_source_fpga.h @@ -68,7 +68,7 @@ private: const std::string FREQ_BAND_0_SPI_DEVICE_NAME = std::string("/dev/spidev2.0"); // Switch UIO device name const std::string FREQ_BAND_1_SPI_DEVICE_NAME = std::string("/dev/spidev1.0"); // Switch UIO device name const uint32_t MAX_NUM_FREQ_BANDS = 2; - const uint32_t DEFAULT_NUM_FREQ_BANDS = 1; + const uint32_t DEFAULT_NUM_FREQ_BANDS = 1; // Default number of frequency bands used const uint64_t DEFAULT_BANDWIDTH = 2500000; const uint32_t default_filter_order = 5; const uint64_t default_sampling_rate = 4092000; @@ -82,50 +82,51 @@ private: // MAX2771 number of configuration registers const uint32_t MAX2771_NUM_REGS = 11; // MAX2771 configuration register fields - const uint32_t NUM_FREQ_BANDS = 1; - const uint32_t IDLE = 0x0; // Idle mode disabled - const uint32_t MIXPOLE = 0x0; // set the passive filter pole at mixer output at 13 MHz. - const uint32_t MIXERMODE = 0x0; // L1 band enabled - const uint32_t FCEN = 0x58; // Center frequency not used when in low-pass filter mode. Set to default value. - const uint32_t FCENX = 0x0; // POlyphase filter selection set to Lowpass filter - const uint32_t ANAIMON = 0x0; // analog monitor disabled - const uint32_t IQEN = 0x1; // I and Q channels enable - const uint32_t GAINREF = 0xAA; // AGC Gain ref - const uint32_t SPI_SDIO_CONFIG = 0x0; // SPI SDIO config when tri-stated: nothing applied - const uint32_t FORMAT = 0x1; // sign and magnitude - const uint32_t BITS = 0x2; // number of bits in the ADC = 2 - const uint32_t DRVCFG = 0x0; // output driver configuration = CMOS Logic - const uint32_t DIEID = 0x0; // identifies version of IC - const uint32_t HILOADEN = 0x0; // disable output driver for high loads - const uint32_t FHIPEN = 0x1; // enable highpass coupling between filter and PGA. - const uint32_t PGAIEN = 0x1; // I-Channel PGA Enable - const uint32_t PGAQEN = 0x1; // Q-Channel PGA Enable - const uint32_t STRMEN = 0x0; // disable DSP interface for serial streaming of data - const uint32_t STRMSTART = 0x0; // the rising edge of this bit enables data streaming to the output, clock, data, sync and frame sync outputs. - const uint32_t STRMSTOP = 0x0; // the rising edge of this bit disables data streaming to the output, clock, data sync and frame sync outputs. - const uint32_t STRMBITS = 0x1; // number of bits to be streamed: I MSB, I LSB - const uint32_t STAMPEN = 0x1; // enable frame number insertion - const uint32_t TIMESYNCEN = 0x1; // enable the output of the time sync pulses at all times when streaming is enabled. - const uint32_t DATASYNCEN = 0x0; // disable the sync pulses at the DATASYNC output - const uint32_t STRMRST = 0x0; // counter reset not active - const uint32_t LOBAND = 0x0; // L1 band - const uint32_t REFOUTEN = 0x1; // Output clock buffer enable - const uint32_t IXTAL = 0x1; // XTAL osscillator/buffer set to normal current - const uint32_t ICP = 0x0; // charge pump current selection set to 0.5 mA - const uint32_t INT_PLL = 0x1; // PLL mode set to integer-N PLL - const uint32_t PWRSAV = 0x0; // PLL power save mode disabled - const uint32_t RDIV = 0x10; // Set the PLL reference division ratio such that the L1 band is tuned to 1575.42 Mhz - const uint32_t FDIV = 0x80000; // PLL fractional division ratio not used. Set to default value - const uint32_t EXTADCCLK = 0x0; // use internally generated clock - const uint32_t REFCLK_L_CNT = 0x100; // set the L counter of the reference clock configuration to its default value - const uint32_t REFCLK_M_CNT = 0x61B; // set the M counter of the reference clock configuration to its default value - const uint32_t FCLKIN = 0x0; // fractional clock divider set to default value - const uint32_t ADCCLK = 0x0; // ADC clock selection set to reference clock divider/multiplier - const uint32_t MODE = 0x0; // DSP interface mode selection - const uint32_t ADCCLK_L_CNT = 0x100; // set the L counter of the ADC clock configuration to its default value - const uint32_t ADCCLK_M_CNT = 0x61B; // set the M counter of the ADC clock configuration to its default value - const uint32_t PRE_FRACDIV_SEL = 0x0; // bypass fractional clock divider - const uint32_t CLKOUT_SEL = 0x1; // CLKOUT selection set to ADC clock + const uint32_t IDLE = 0x0; // Idle mode disabled + const uint32_t MIXPOLE = 0x0; // set the passive filter pole at mixer output at 13 MHz. + const uint32_t MIXERMODE_HIGH_BAND = 0x0; // L1 band enabled + const uint32_t MIXERMODE_LOW_BAND = 0X1; // L2/L5 band enabled + const uint32_t FCEN = 0x58; // Center frequency not used when in low-pass filter mode. Set to default value. + const uint32_t FCENX = 0x0; // POlyphase filter selection set to Lowpass filter + const uint32_t ANAIMON = 0x0; // analog monitor disabled + const uint32_t IQEN = 0x1; // I and Q channels enable + const uint32_t GAINREF = 0xAA; // AGC Gain ref + const uint32_t SPI_SDIO_CONFIG = 0x0; // SPI SDIO config when tri-stated: nothing applied + const uint32_t FORMAT = 0x1; // sign and magnitude + const uint32_t BITS = 0x2; // number of bits in the ADC = 2 + const uint32_t DRVCFG = 0x0; // output driver configuration = CMOS Logic + const uint32_t DIEID = 0x0; // identifies version of IC + const uint32_t HILOADEN = 0x0; // disable output driver for high loads + const uint32_t FHIPEN = 0x1; // enable highpass coupling between filter and PGA. + const uint32_t PGAIEN = 0x1; // I-Channel PGA Enable + const uint32_t PGAQEN = 0x1; // Q-Channel PGA Enable + const uint32_t STRMEN = 0x0; // disable DSP interface for serial streaming of data + const uint32_t STRMSTART = 0x0; // the rising edge of this bit enables data streaming to the output, clock, data, sync and frame sync outputs. + const uint32_t STRMSTOP = 0x0; // the rising edge of this bit disables data streaming to the output, clock, data sync and frame sync outputs. + const uint32_t STRMBITS = 0x1; // number of bits to be streamed: I MSB, I LSB + const uint32_t STAMPEN = 0x1; // enable frame number insertion + const uint32_t TIMESYNCEN = 0x1; // enable the output of the time sync pulses at all times when streaming is enabled. + const uint32_t DATASYNCEN = 0x0; // disable the sync pulses at the DATASYNC output + const uint32_t STRMRST = 0x0; // counter reset not active + const uint32_t LOBAND_L1 = 0x0; // L1 band + const uint32_t LOBAND_L5 = 0x1; // L5 band + const uint32_t REFOUTEN = 0x1; // Output clock buffer enable + const uint32_t IXTAL = 0x1; // XTAL osscillator/buffer set to normal current + const uint32_t ICP = 0x0; // charge pump current selection set to 0.5 mA + const uint32_t INT_PLL = 0x1; // PLL mode set to integer-N PLL + const uint32_t PWRSAV = 0x0; // PLL power save mode disabled + const uint32_t RDIV = 0x10; // Set the PLL reference division ratio + const uint32_t FDIV = 0x80000; // PLL fractional division ratio not used. Set to default value + const uint32_t EXTADCCLK = 0x0; // use internally generated clock + const uint32_t REFCLK_L_CNT = 0x100; // set the L counter of the reference clock configuration to its default value + const uint32_t REFCLK_M_CNT = 0x61B; // set the M counter of the reference clock configuration to its default value + const uint32_t FCLKIN = 0x0; // fractional clock divider set to default value + const uint32_t ADCCLK = 0x0; // ADC clock selection set to reference clock divider/multiplier + const uint32_t MODE = 0x0; // DSP interface mode selection + const uint32_t ADCCLK_L_CNT = 0x100; // set the L counter of the ADC clock configuration to its default value + const uint32_t ADCCLK_M_CNT = 0x61B; // set the M counter of the ADC clock configuration to its default value + const uint32_t PRE_FRACDIV_SEL = 0x0; // bypass fractional clock divider + const uint32_t CLKOUT_SEL = 0x1; // CLKOUT selection set to ADC clock // MAX2771 configuration register registers const uint32_t TEST_MODE_1_REG_VAL = 0x01E0F401; // reserved const uint32_t TEST_MODE_2_REG_VAL = 0x00000002; diff --git a/src/algorithms/signal_source/libs/fpga_spidev.cc b/src/algorithms/signal_source/libs/fpga_spidev.cc index da3532bdd..a553e5d6b 100644 --- a/src/algorithms/signal_source/libs/fpga_spidev.cc +++ b/src/algorithms/signal_source/libs/fpga_spidev.cc @@ -24,6 +24,7 @@ int Fpga_spidev::SPI_open(std::string spi_device_name) { + std::cout << "opening SPI device file " << spi_device_name << std::endl; if ((d_fd = open(spi_device_name.c_str(), O_RDWR)) < 0) { std::cerr << "Failed to open the " << spi_device_name << " device file \n";