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https://github.com/gnss-sdr/gnss-sdr
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Merge pull request #729 from mmajoral/dyn_bit_sel
Optimize the use of the FPGA dynamic bit selection blocks. Reorder AD…
This commit is contained in:
commit
4105765637
@ -59,26 +59,26 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
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filename0_(configuration->property(role + ".filename", empty_string)),
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rf_gain_rx1_(configuration->property(role + ".gain_rx1", default_manual_gain_rx1)),
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rf_gain_rx2_(configuration->property(role + ".gain_rx2", default_manual_gain_rx2)),
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scale_dds_dbfs_(configuration->property(role + ".scale_dds_dbfs", -3.0)),
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phase_dds_deg_(configuration->property(role + ".phase_dds_deg", 0.0)),
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tx_attenuation_db_(configuration->property(role + ".tx_attenuation_db", default_tx_attenuation_db)),
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freq0_(configuration->property(role + ".freq", 0)),
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freq1_(configuration->property(role + ".freq1", static_cast<uint64_t>(GPS_L5_FREQ_HZ))),
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sample_rate_(configuration->property(role + ".sampling_frequency", default_bandwidth)),
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bandwidth_(configuration->property(role + ".bandwidth", default_bandwidth)),
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samples_to_skip_(0),
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samples_(configuration->property(role + ".samples", static_cast<int64_t>(0))),
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freq_dds_tx_hz_(configuration->property(role + ".freq_dds_tx_hz", uint64_t(10000))),
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freq_rf_tx_hz_(configuration->property(role + ".freq_rf_tx_hz", static_cast<uint64_t>(GPS_L1_FREQ_HZ - GPS_L5_FREQ_HZ - freq_dds_tx_hz_))),
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tx_bandwidth_(configuration->property(role + ".tx_bandwidth", static_cast<uint64_t>(500000))),
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Fpass_(configuration->property(role + ".Fpass", static_cast<float>(0.0))),
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Fstop_(configuration->property(role + ".Fstop", static_cast<float>(0.0))),
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num_freq_bands_(2),
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dma_buff_offset_pos_(0),
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scale_dds_dbfs_(configuration->property(role + ".scale_dds_dbfs", -3.0)),
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phase_dds_deg_(configuration->property(role + ".phase_dds_deg", 0.0)),
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tx_attenuation_db_(configuration->property(role + ".tx_attenuation_db", default_tx_attenuation_db)),
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freq_dds_tx_hz_(configuration->property(role + ".freq_dds_tx_hz", uint64_t(10000))),
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freq_rf_tx_hz_(configuration->property(role + ".freq_rf_tx_hz", static_cast<uint64_t>(GPS_L1_FREQ_HZ - GPS_L5_FREQ_HZ - freq_dds_tx_hz_))),
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tx_bandwidth_(configuration->property(role + ".tx_bandwidth", static_cast<uint64_t>(500000))),
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item_size_(sizeof(int8_t)),
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in_stream_(in_stream),
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out_stream_(out_stream),
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switch_position_(configuration->property(role + ".switch_position", 0)),
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item_size_(sizeof(int8_t)),
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enable_dds_lo_(configuration->property(role + ".enable_dds_lo", false)),
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filter_auto_(configuration->property(role + ".filter_auto", false)),
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quadrature_(configuration->property(role + ".quadrature", true)),
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@ -93,11 +93,17 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
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rf_shutdown_(configuration->property(role + ".rf_shutdown", FLAGS_rf_shutdown)),
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repeat_(configuration->property(role + ".repeat", false))
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{
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const int l1_band = configuration->property("Channels_1C.count", 0) +
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configuration->property("Channels_1B.count", 0);
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const double seconds_to_skip = configuration->property(role + ".seconds_to_skip", 0.0);
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const size_t header_size = configuration->property(role + ".header_size", 0);
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const int num_ch_rx1 = configuration->property("Channels_1C.count", 0) +
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configuration->property("Channels_1B.count", 0);
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const int num_ch_rx2 = (configuration->property("Channels_L2.count", 0) > 0) ? configuration->property("Channels_L2.count", 0) : configuration->property("Channels_L5.count", 0) + configuration->property("Channels_5X.count", 0);
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// number of frequency bands
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if (num_ch_rx2 == 0)
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{
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num_freq_bands_ = 1;
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}
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if (freq0_ == 0)
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{
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@ -135,8 +141,7 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
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// if more than one input file are specified then the DMA transfer the samples to both the L1 and the L2/L5 frequency channels.
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if (filename1_.empty())
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{
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num_freq_bands_ = 1;
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if (l1_band != 0)
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if (num_ch_rx1 != 0)
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{
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dma_buff_offset_pos_ = 2;
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}
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@ -160,7 +165,6 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
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if (find_uio_dev_file_name(device_io_name, switch_device_name, 0) < 0)
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{
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std::cerr << "Cannot find the FPGA uio device file corresponding to device name " << switch_device_name << '\n';
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item_size_ = 0;
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return;
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}
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@ -196,7 +200,6 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
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else
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{
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std::cerr << "SignalSource: Unable to open the samples file " << filename0_.c_str() << '\n';
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item_size_ = 0;
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return;
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}
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std::streamsize ss = std::cout.precision();
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@ -224,7 +227,6 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
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else
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{
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std::cerr << "SignalSource: Unable to open the samples file " << filename1_.c_str() << '\n';
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item_size_ = 0;
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return;
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}
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std::streamsize ss = std::cout.precision();
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@ -372,7 +374,6 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
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catch (const std::runtime_error &e)
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{
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std::cerr << "Exception cached when configuring the RX chain: " << e.what() << '\n';
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item_size_ = 0;
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return;
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}
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// LOCAL OSCILLATOR DDS GENERATOR FOR DUAL FREQUENCY OPERATION
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@ -407,7 +408,6 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
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catch (const std::runtime_error &e)
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{
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std::cerr << "Exception cached when configuring the TX carrier: " << e.what() << '\n';
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item_size_ = 0;
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return;
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}
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}
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@ -424,7 +424,6 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
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if (find_uio_dev_file_name(device_io_name_buffer_monitor, buffer_monitor_device_name, 0) < 0)
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{
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std::cerr << "Cannot find the FPGA uio device file corresponding to device name " << buffer_monitor_device_name << '\n';
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item_size_ = 0;
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return;
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}
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@ -435,25 +434,7 @@ Ad9361FpgaSignalSource::Ad9361FpgaSignalSource(const ConfigurationInterface *con
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// dynamic bits selection
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if (enable_dynamic_bit_selection_)
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{
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std::string device_io_name_dyn_bit_sel_0;
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std::string device_io_name_dyn_bit_sel_1;
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// find the uio device file corresponding to the dynamic bit selector 0 module.
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if (find_uio_dev_file_name(device_io_name_dyn_bit_sel_0, dyn_bit_sel_device_name, 0) < 0)
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{
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std::cerr << "Cannot find the FPGA uio device file corresponding to device name " << dyn_bit_sel_device_name << '\n';
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item_size_ = 0;
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return;
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}
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// find the uio device file corresponding to the dynamic bit selector 1 module.
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if (find_uio_dev_file_name(device_io_name_dyn_bit_sel_1, dyn_bit_sel_device_name, 1) < 0)
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{
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std::cerr << "Cannot find the FPGA uio device file corresponding to device name " << dyn_bit_sel_device_name << '\n';
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item_size_ = 0;
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return;
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}
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dynamic_bit_selection_fpga = std::make_shared<Fpga_dynamic_bit_selection>(device_io_name_dyn_bit_sel_0, device_io_name_dyn_bit_sel_1);
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dynamic_bit_selection_fpga = std::make_shared<Fpga_dynamic_bit_selection>(num_freq_bands_);
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thread_dynamic_bit_selection = std::thread([&] { run_dynamic_bit_selection_process(); });
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}
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@ -118,7 +118,6 @@ private:
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Concurrent_Queue<pmt::pmt_t> *queue_;
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// Front-end settings
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std::string gain_mode_rx1_;
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std::string gain_mode_rx2_;
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std::string rf_port_select_;
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@ -130,30 +129,31 @@ private:
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double rf_gain_rx1_;
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double rf_gain_rx2_;
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double scale_dds_dbfs_;
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double phase_dds_deg_;
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double tx_attenuation_db_;
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uint64_t freq0_; // frequency of local oscillator for ADRV9361-A 0
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uint64_t freq1_; // frequency of local oscillator for ADRV9361-B (if present)
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uint64_t sample_rate_;
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uint64_t bandwidth_;
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uint64_t samples_to_skip_;
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int64_t samples_;
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uint64_t freq_dds_tx_hz_;
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uint64_t freq_rf_tx_hz_;
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uint64_t tx_bandwidth_;
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float Fpass_;
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float Fstop_;
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uint32_t num_freq_bands_;
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uint32_t dma_buff_offset_pos_;
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// DDS configuration for LO generation for external mixer
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double scale_dds_dbfs_;
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double phase_dds_deg_;
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double tx_attenuation_db_;
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uint64_t freq_dds_tx_hz_;
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uint64_t freq_rf_tx_hz_;
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uint64_t tx_bandwidth_;
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size_t item_size_;
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uint32_t in_stream_;
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uint32_t out_stream_;
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int32_t switch_position_;
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bool enable_dds_lo_;
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size_t item_size_;
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bool enable_dds_lo_;
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bool filter_auto_;
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bool quadrature_;
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bool rf_dc_;
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@ -2,7 +2,7 @@
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* \file fpga_dynamic_bit_selection.cc
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* \brief Dynamic Bit Selection in the received signal.
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* \authors <ul>
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* <li> Marc Majoral, 2020. mmajoral(at)cttc.es
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* <li> Marc Majoral, 2023. mmajoral(at)cttc.es
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* </ul>
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*
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* Class that controls the Dynamic Bit Selection in the FPGA.
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@ -13,58 +13,52 @@
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* GNSS-SDR is a Global Navigation Satellite System software-defined receiver.
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* This file is part of GNSS-SDR.
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*
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* Copyright (C) 2010-2020 (see AUTHORS file for a list of contributors)
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* Copyright (C) 2010-2023 (see AUTHORS file for a list of contributors)
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* SPDX-License-Identifier: GPL-3.0-or-later
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*
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* -----------------------------------------------------------------------------
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*/
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#include "fpga_dynamic_bit_selection.h"
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#include "uio_fpga.h"
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#include <glog/logging.h>
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#include <fcntl.h> // for open, O_RDWR, O_SYNC
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#include <iostream> // for cout
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#include <sys/mman.h> // for mmap
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Fpga_dynamic_bit_selection::Fpga_dynamic_bit_selection(const std::string &device_name1, const std::string &device_name2)
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Fpga_dynamic_bit_selection::Fpga_dynamic_bit_selection(uint32_t num_freq_bands)
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: d_num_freq_bands(num_freq_bands)
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{
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// dynamic bits selection corresponding to frequency band 1
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if ((d_device_descriptor1 = open(device_name1.c_str(), O_RDWR | O_SYNC)) == -1)
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d_map_base = std::vector<volatile unsigned *>(d_num_freq_bands);
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d_device_descriptors = std::vector<int>(d_num_freq_bands);
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d_shift_out_bits = std::vector<uint32_t>(d_num_freq_bands);
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for (uint32_t k = 0; k < d_num_freq_bands; k++)
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{
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LOG(WARNING) << "Cannot open deviceio" << device_name1;
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// find the uio device file corresponding to the dynamic bit selector 0 module.
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std::string device_name;
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if (find_uio_dev_file_name(device_name, dyn_bit_sel_device_name, 0) < 0)
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{
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std::cerr << "Cannot find the FPGA uio device file corresponding to device name " << dyn_bit_sel_device_name << '\n';
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return;
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}
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d_map_base1 = reinterpret_cast<volatile unsigned *>(mmap(nullptr, FPGA_PAGE_SIZE,
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PROT_READ | PROT_WRITE, MAP_SHARED, d_device_descriptor1, 0));
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// dynamic bits selection corresponding to frequency band 1
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if ((d_device_descriptors[k] = open(device_name.c_str(), O_RDWR | O_SYNC)) == -1)
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{
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LOG(WARNING) << "Cannot open deviceio" << device_name;
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}
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d_map_base[k] = reinterpret_cast<volatile unsigned *>(mmap(nullptr, FPGA_PAGE_SIZE,
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PROT_READ | PROT_WRITE, MAP_SHARED, d_device_descriptors[k], 0));
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if (d_map_base1 == reinterpret_cast<void *>(-1))
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if (d_map_base[k] == reinterpret_cast<void *>(-1))
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{
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LOG(WARNING) << "Cannot map the FPGA dynamic bit selection module in frequency band 1 into tracking memory";
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std::cout << "Could not map dynamic bit selection memory corresponding to frequency band 1.\n";
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}
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// dynamic bits selection corresponding to frequency band 2
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if ((d_device_descriptor2 = open(device_name2.c_str(), O_RDWR | O_SYNC)) == -1)
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{
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LOG(WARNING) << "Cannot open deviceio" << device_name2;
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}
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d_map_base2 = reinterpret_cast<volatile unsigned *>(mmap(nullptr, FPGA_PAGE_SIZE,
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PROT_READ | PROT_WRITE, MAP_SHARED, d_device_descriptor2, 0));
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if (d_map_base2 == reinterpret_cast<void *>(-1))
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{
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LOG(WARNING) << "Cannot map the FPGA dynamic bit selection module in frequency band 2 into tracking memory";
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std::cout << "Could not map dynamic bit selection memory corresponding to frequency band 2.\n";
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}
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// initialize default bit selection
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shift_out_bits_band1 = shift_out_bits_default;
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shift_out_bits_band2 = shift_out_bits_default;
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// init bit selection corresopnding to frequency band 1
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d_map_base1[0] = shift_out_bits_band1;
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// init bit selection corresponding to frequency band 2
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d_map_base2[0] = shift_out_bits_band2;
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d_shift_out_bits[k] = shift_out_bits_default;
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d_map_base[k][0] = d_shift_out_bits[k];
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}
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DLOG(INFO) << "Dynamic bit selection FPGA class created";
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}
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@ -77,65 +71,42 @@ Fpga_dynamic_bit_selection::~Fpga_dynamic_bit_selection()
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void Fpga_dynamic_bit_selection::bit_selection()
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{
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// estimated signal power corresponding to frequency band 1
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uint32_t rx_signal_power1 = d_map_base1[1];
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// estimated signal power corresponding to frequency band 2
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uint32_t rx_signal_power2 = d_map_base2[1];
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for (uint32_t k = 0; k < d_num_freq_bands; k++)
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{
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// estimated signal power
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uint32_t rx_signal_power = d_map_base[k][1];
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// dynamic bit selection corresponding to frequency band 1
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if (rx_signal_power1 > Power_Threshold_High)
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// dynamic bit selection
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if (rx_signal_power > Power_Threshold_High)
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{
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if (shift_out_bits_band1 < shift_out_bit_max)
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if (d_shift_out_bits[k] < shift_out_bit_max)
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{
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shift_out_bits_band1 = shift_out_bits_band1 + 1;
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d_shift_out_bits[k] = d_shift_out_bits[k] + 1;
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}
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}
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else if (rx_signal_power1 < Power_Threshold_Low)
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else if (rx_signal_power < Power_Threshold_Low)
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{
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if (shift_out_bits_band1 > shift_out_bits_min)
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if (d_shift_out_bits[k] > shift_out_bits_min)
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{
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shift_out_bits_band1 = shift_out_bits_band1 - 1;
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}
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}
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// dynamic bit selection corresponding to frequency band 2
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if (rx_signal_power2 > Power_Threshold_High)
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{
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if (shift_out_bits_band2 < shift_out_bit_max)
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{
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shift_out_bits_band2 = shift_out_bits_band2 + 1;
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}
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}
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else if (rx_signal_power2 < Power_Threshold_Low)
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{
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if (shift_out_bits_band2 > shift_out_bits_min)
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{
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shift_out_bits_band2 = shift_out_bits_band2 - 1;
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d_shift_out_bits[k] = d_shift_out_bits[k] - 1;
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}
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}
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// update bit selection corresopnding to frequency band 1
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d_map_base1[0] = shift_out_bits_band1;
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// udpate bit selection corresponding to frequency band 2
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d_map_base2[0] = shift_out_bits_band2;
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d_map_base[k][0] = d_shift_out_bits[k];
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}
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}
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void Fpga_dynamic_bit_selection::close_devices()
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{
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auto *aux = const_cast<unsigned *>(d_map_base1);
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for (uint32_t k = 0; k < d_num_freq_bands; k++)
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{
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auto *aux = const_cast<unsigned *>(d_map_base[k]);
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if (munmap(static_cast<void *>(aux), FPGA_PAGE_SIZE) == -1)
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{
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std::cout << "Failed to unmap memory uio\n";
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}
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aux = const_cast<unsigned *>(d_map_base2);
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if (munmap(static_cast<void *>(aux), FPGA_PAGE_SIZE) == -1)
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{
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std::cout << "Failed to unmap memory uio\n";
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close(d_device_descriptors[k]);
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}
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close(d_device_descriptor1);
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close(d_device_descriptor2);
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}
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@ -25,6 +25,7 @@
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#include <cstddef>
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#include <cstdint>
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#include <string>
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#include <vector>
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/** \addtogroup Signal_Source
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* \{ */
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@ -42,7 +43,7 @@ public:
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/*!
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* \brief Constructor
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*/
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explicit Fpga_dynamic_bit_selection(const std::string& device_name1, const std::string& device_name2);
|
||||
explicit Fpga_dynamic_bit_selection(uint32_t num_freq_bands);
|
||||
|
||||
/*!
|
||||
* \brief Destructor
|
||||
@ -52,12 +53,12 @@ public:
|
||||
/*!
|
||||
* \brief This function configures the switch in th eFPGA
|
||||
*/
|
||||
// void set_switch_position(int32_t switch_position);
|
||||
void bit_selection(void);
|
||||
|
||||
private:
|
||||
const std::string switch_device_name = std::string("AXIS_Switch_v1_0_0"); // Switch UIO device name
|
||||
const std::string dyn_bit_sel_device_name = std::string("dynamic_bits_selector"); // Switch dhnamic bit selector device name
|
||||
static const size_t FPGA_PAGE_SIZE = 0x1000;
|
||||
|
||||
static const uint32_t Num_bits_ADC = 12; // Number of bits in the ADC
|
||||
static const uint32_t Num_bits_FPGA = 4; // Number of bits after the bit selection
|
||||
static const uint32_t shift_out_bits_default = Num_bits_ADC - Num_bits_FPGA; // take the most significant bits by default
|
||||
@ -70,14 +71,11 @@ private:
|
||||
|
||||
void close_devices(void);
|
||||
|
||||
uint32_t shift_out_bits_band1; // number of bits to shift for frequency band 1
|
||||
uint32_t shift_out_bits_band2; // number of bits to shift for frequency band 2
|
||||
std::vector<volatile unsigned*> d_map_base;
|
||||
std::vector<int> d_device_descriptors;
|
||||
std::vector<uint32_t> d_shift_out_bits;
|
||||
|
||||
volatile unsigned* d_map_base1; // driver memory map corresponding to frequency band 1
|
||||
int d_device_descriptor1; // driver descriptor corresponding to frequency band 1
|
||||
|
||||
volatile unsigned* d_map_base2; // driver memory map corresponding to frequency band 2
|
||||
int d_device_descriptor2; // driver descriptor corresponding to frequency band 2
|
||||
uint32_t d_num_freq_bands; // number of frequency bands
|
||||
};
|
||||
|
||||
|
||||
|
@ -279,7 +279,11 @@ void gnss_sdr_fpga_sample_counter::wait_for_interrupt() const
|
||||
|
||||
// enable interrupts
|
||||
int32_t reenable = 1;
|
||||
write(fd, reinterpret_cast<void *>(&reenable), sizeof(int32_t));
|
||||
const ssize_t nbytes = TEMP_FAILURE_RETRY(write(fd, reinterpret_cast<void *>(&reenable), sizeof(int32_t)));
|
||||
if (nbytes != sizeof(int32_t))
|
||||
{
|
||||
std::cerr << "Error re-enabling FPGA sample counter interrupt.\n";
|
||||
}
|
||||
|
||||
// wait for interrupt
|
||||
nb = read(fd, &irq_count, sizeof(irq_count));
|
||||
|
Loading…
Reference in New Issue
Block a user