mirrors/gnss-sdr
1
0
Fork 0
mirror of https://github.com/gnss-sdr/gnss-sdr synced 2024-12-14 20:20:35 +00:00
Code Issues Releases Wiki Activity

Merge branch 'next' of https://github.com/gnss-sdr/gnss-sdr into next

Browse Source
This commit is contained in:
Carles Fernandez 2019-03-01 10:37:11 +01:00
commit 2026c7f2d1
No known key found for this signature in database
GPG Key ID: 4C583C52B0C3877D
22 changed files with 191 additions and 314 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

168
src/algorithms/acquisition/adapters/gps_l2_m_pcps_acquisition_fpga.cc
View File

@ -52,7 +52,6 @@ GpsL2MPcpsAcquisitionFpga::GpsL2MPcpsAcquisitionFpga(
in_streams_(in_streams), in_streams_(in_streams),
out_streams_(out_streams) out_streams_(out_streams)
{ {
//pcpsconf_t acq_parameters;
pcpsconf_fpga_t acq_parameters; pcpsconf_fpga_t acq_parameters;
configuration_ = configuration; configuration_ = configuration;
std::string default_item_type = "gr_complex"; std::string default_item_type = "gr_complex";
@ -61,33 +60,17 @@ GpsL2MPcpsAcquisitionFpga::GpsL2MPcpsAcquisitionFpga(
LOG(INFO) << "role " << role; LOG(INFO) << "role " << role;
item_type_ = configuration_->property(role + ".item_type", default_item_type); item_type_ = configuration_->property(role + ".item_type", default_item_type);
//float pfa = configuration_->property(role + ".pfa", 0.0);
int64_t fs_in_deprecated = configuration_->property("GNSS-SDR.internal_fs_hz", 2048000); int64_t fs_in_deprecated = configuration_->property("GNSS-SDR.internal_fs_hz", 2048000);
fs_in_ = configuration_->property("GNSS-SDR.internal_fs_sps", fs_in_deprecated); fs_in_ = configuration_->property("GNSS-SDR.internal_fs_sps", fs_in_deprecated);
acq_parameters.fs_in = fs_in_; acq_parameters.fs_in = fs_in_;
//if_ = configuration_->property(role + ".if", 0);
//acq_parameters.freq = if_;
//dump_ = configuration_->property(role + ".dump", false);
//acq_parameters.dump = dump_;
//blocking_ = configuration_->property(role + ".blocking", true);
//acq_parameters.blocking = blocking_;
doppler_max_ = configuration->property(role + ".doppler_max", 5000); doppler_max_ = configuration->property(role + ".doppler_max", 5000);
if (FLAGS_doppler_max != 0) doppler_max_ = FLAGS_doppler_max; if (FLAGS_doppler_max != 0) doppler_max_ = FLAGS_doppler_max;
acq_parameters.doppler_max = doppler_max_; acq_parameters.doppler_max = doppler_max_;
//bit_transition_flag_ = configuration_->property(role + ".bit_transition_flag", false);
//acq_parameters.bit_transition_flag = bit_transition_flag_;
//use_CFAR_algorithm_flag_ = configuration_->property(role + ".use_CFAR_algorithm", true); //will be false in future versions
//acq_parameters.use_CFAR_algorithm_flag = use_CFAR_algorithm_flag_;
//max_dwells_ = configuration_->property(role + ".max_dwells", 1);
//acq_parameters.max_dwells = max_dwells_;
//dump_filename_ = configuration_->property(role + ".dump_filename", default_dump_filename);
//acq_parameters.dump_filename = dump_filename_;
//--- Find number of samples per spreading code -------------------------
//code_length_ = std::round(static_cast<double>(fs_in_) / (GPS_L2_M_CODE_RATE_HZ / static_cast<double>(GPS_L2_M_CODE_LENGTH_CHIPS)));
acq_parameters.sampled_ms = 20; acq_parameters.sampled_ms = 20;
unsigned code_length = std::round(static_cast<double>(fs_in_) / (GPS_L2_M_CODE_RATE_HZ / static_cast<double>(GPS_L2_M_CODE_LENGTH_CHIPS))); unsigned int code_length = std::round(static_cast<double>(fs_in_) / (GPS_L2_M_CODE_RATE_HZ / static_cast<double>(GPS_L2_M_CODE_LENGTH_CHIPS)));
acq_parameters.code_length = code_length; acq_parameters.code_length = code_length;
// The FPGA can only use FFT lengths that are a power of two. // The FPGA can only use FFT lengths that are a power of two.
float nbits = ceilf(log2f((float)code_length)); float nbits = ceilf(log2f((float)code_length));
@ -114,10 +97,9 @@ GpsL2MPcpsAcquisitionFpga::GpsL2MPcpsAcquisitionFpga(
{ {
gps_l2c_m_code_gen_complex_sampled(code, PRN, fs_in_); gps_l2c_m_code_gen_complex_sampled(code, PRN, fs_in_);
// fill in zero padding // fill in zero padding
for (int s = code_length; s < nsamples_total; s++) for (unsigned int s = code_length; s < nsamples_total; s++)
{ {
code[s] = std::complex<float>(0.0, 0.0); code[s] = std::complex<float>(0.0, 0.0);
//code[s] = 0;
} }
memcpy(fft_if->get_inbuf(), code, sizeof(gr_complex) * nsamples_total); // copy to FFT buffer memcpy(fft_if->get_inbuf(), code, sizeof(gr_complex) * nsamples_total); // copy to FFT buffer
fft_if->execute(); // Run the FFT of local code fft_if->execute(); // Run the FFT of local code
@ -156,47 +138,9 @@ GpsL2MPcpsAcquisitionFpga::GpsL2MPcpsAcquisitionFpga(
doppler_step_ = 0; doppler_step_ = 0;
gnss_synchro_ = nullptr; gnss_synchro_ = nullptr;
// vector_length_ = code_length_;
//
// if (bit_transition_flag_)
// {
// vector_length_ *= 2;
// }
// code_ = new gr_complex[vector_length_];
//
// if (item_type_.compare("cshort") == 0)
// {
// item_size_ = sizeof(lv_16sc_t);
// }
// else
// {
// item_size_ = sizeof(gr_complex);
// }
//acq_parameters.samples_per_ms = static_cast<int>(std::round(static_cast<double>(fs_in_) * 0.001));
//acq_parameters.samples_per_code = code_length_;
//acq_parameters.it_size = item_size_;
//acq_parameters.sampled_ms = 20;
//acq_parameters.num_doppler_bins_step2 = configuration_->property(role + ".second_nbins", 4);
//acq_parameters.doppler_step2 = configuration_->property(role + ".second_doppler_step", 125.0);
//acq_parameters.make_2_steps = configuration_->property(role + ".make_two_steps", true);
//acquisition_ = pcps_make_acquisition(acq_parameters);
DLOG(INFO) << "acquisition(" << acquisition_fpga_->unique_id() << ")"; DLOG(INFO) << "acquisition(" << acquisition_fpga_->unique_id() << ")";
// stream_to_vector_ = gr::blocks::stream_to_vector::make(item_size_, vector_length_);
// DLOG(INFO) << "stream_to_vector(" << stream_to_vector_->unique_id() << ")";
//
// if (item_type_.compare("cbyte") == 0)
// {
// cbyte_to_float_x2_ = make_complex_byte_to_float_x2();
// float_to_complex_ = gr::blocks::float_to_complex::make();
// }
// channel_ = 0;
threshold_ = 0.0; threshold_ = 0.0;
// doppler_step_ = 0;
// gnss_synchro_ = 0;
} }
@ -221,23 +165,8 @@ void GpsL2MPcpsAcquisitionFpga::set_channel(unsigned int channel)
void GpsL2MPcpsAcquisitionFpga::set_threshold(float threshold) void GpsL2MPcpsAcquisitionFpga::set_threshold(float threshold)
{ {
// float pfa = configuration_->property(role_ + std::to_string(channel_) + ".pfa", 0.0); threshold_ = threshold;
//
// if (pfa == 0.0)
// {
// pfa = configuration_->property(role_ + ".pfa", 0.0);
// }
// if (pfa == 0.0)
// {
// threshold_ = threshold;
// }
// else
// {
// threshold_ = calculate_threshold(pfa);
// }
DLOG(INFO) << "Channel " << channel_ << " Threshold = " << threshold_; DLOG(INFO) << "Channel " << channel_ << " Threshold = " << threshold_;
acquisition_fpga_->set_threshold(threshold_); acquisition_fpga_->set_threshold(threshold_);
} }
@ -301,99 +230,26 @@ void GpsL2MPcpsAcquisitionFpga::set_state(int state)
} }
//float GpsL2MPcpsAcquisitionFpga::calculate_threshold(float pfa)
//{
// //Calculate the threshold
// unsigned int frequency_bins = 0;
// for (int doppler = static_cast<int>(-doppler_max_); doppler <= static_cast<int>(doppler_max_); doppler += doppler_step_)
// {
// frequency_bins++;
// }
// DLOG(INFO) << "Channel " << channel_ << " Pfa = " << pfa;
// unsigned int ncells = vector_length_ * frequency_bins;
// double exponent = 1.0 / static_cast<double>(ncells);
// double val = pow(1.0 - pfa, exponent);
// double lambda = double(vector_length_);
// boost::math::exponential_distribution<double> mydist(lambda);
// float threshold = static_cast<float>(quantile(mydist, val));
//
// return threshold;
//}
void GpsL2MPcpsAcquisitionFpga::connect(gr::top_block_sptr top_block) void GpsL2MPcpsAcquisitionFpga::connect(gr::top_block_sptr top_block)
{ {
// if (item_type_.compare("gr_complex") == 0) if (top_block)
// { { /* top_block is not null */
// top_block->connect(stream_to_vector_, 0, acquisition_, 0); };
// } // Nothing to connect
// else if (item_type_.compare("cshort") == 0)
// {
// top_block->connect(stream_to_vector_, 0, acquisition_, 0);
// }
// else if (item_type_.compare("cbyte") == 0)
// {
// top_block->connect(cbyte_to_float_x2_, 0, float_to_complex_, 0);
// top_block->connect(cbyte_to_float_x2_, 1, float_to_complex_, 1);
// top_block->connect(float_to_complex_, 0, stream_to_vector_, 0);
// top_block->connect(stream_to_vector_, 0, acquisition_, 0);
// }
// else
// {
// LOG(WARNING) << item_type_ << " unknown acquisition item type";
// }
// nothing to connect
} }
void GpsL2MPcpsAcquisitionFpga::disconnect(gr::top_block_sptr top_block) void GpsL2MPcpsAcquisitionFpga::disconnect(gr::top_block_sptr top_block)
{ {
// if (item_type_.compare("gr_complex") == 0) if (top_block)
// { { /* top_block is not null */
// top_block->disconnect(stream_to_vector_, 0, acquisition_, 0); };
// } // Nothing to diconnect
// else if (item_type_.compare("cshort") == 0)
// {
// top_block->disconnect(stream_to_vector_, 0, acquisition_, 0);
// }
// else if (item_type_.compare("cbyte") == 0)
// {
// // Since a byte-based acq implementation is not available,
// // we just convert cshorts to gr_complex
// top_block->disconnect(cbyte_to_float_x2_, 0, float_to_complex_, 0);
// top_block->disconnect(cbyte_to_float_x2_, 1, float_to_complex_, 1);
// top_block->disconnect(float_to_complex_, 0, stream_to_vector_, 0);
// top_block->disconnect(stream_to_vector_, 0, acquisition_, 0);
// }
// else
// {
// LOG(WARNING) << item_type_ << " unknown acquisition item type";
// }
// nothing to disconnect
} }
gr::basic_block_sptr GpsL2MPcpsAcquisitionFpga::get_left_block() gr::basic_block_sptr GpsL2MPcpsAcquisitionFpga::get_left_block()
{ {
// if (item_type_.compare("gr_complex") == 0)
// {
// return stream_to_vector_;
// }
// else if (item_type_.compare("cshort") == 0)
// {
// return stream_to_vector_;
// }
// else if (item_type_.compare("cbyte") == 0)
// {
// return cbyte_to_float_x2_;
// }
// else
// {
// LOG(WARNING) << item_type_ << " unknown acquisition item type";
// return nullptr;
// }
return nullptr; return nullptr;
} }

7
src/algorithms/acquisition/gnuradio_blocks/pcps_acquisition.cc
View File

@ -187,6 +187,7 @@ pcps_acquisition::pcps_acquisition(const Acq_Conf& conf_) : gr::block("pcps_acqu
} }
} }
pcps_acquisition::~pcps_acquisition() pcps_acquisition::~pcps_acquisition()
{ {
if (d_num_doppler_bins > 0) if (d_num_doppler_bins > 0)
@ -227,6 +228,7 @@ void pcps_acquisition::set_resampler_latency(uint32_t latency_samples)
acq_parameters.resampler_latency_samples = latency_samples; acq_parameters.resampler_latency_samples = latency_samples;
} }
void pcps_acquisition::set_local_code(std::complex<float>* code) void pcps_acquisition::set_local_code(std::complex<float>* code)
{ {
// reset the intermediate frequency // reset the intermediate frequency
@ -912,6 +914,7 @@ void pcps_acquisition::acquisition_core(uint64_t samp_count)
} }
} }
// Called by gnuradio to enable drivers, etc for i/o devices. // Called by gnuradio to enable drivers, etc for i/o devices.
bool pcps_acquisition::start() bool pcps_acquisition::start()
{ {
@ -919,8 +922,10 @@ bool pcps_acquisition::start()
return true; return true;
} }
int pcps_acquisition::general_work(int noutput_items __attribute__((unused)), int pcps_acquisition::general_work(int noutput_items __attribute__((unused)),
gr_vector_int& ninput_items, gr_vector_const_void_star& input_items, gr_vector_int& ninput_items,
gr_vector_const_void_star& input_items,
gr_vector_void_star& output_items __attribute__((unused))) gr_vector_void_star& output_items __attribute__((unused)))
{ {
/* /*

3
src/algorithms/acquisition/gnuradio_blocks/pcps_acquisition_fpga.cc
View File

@ -253,7 +253,8 @@ void pcps_acquisition_fpga::set_active(bool active)
int pcps_acquisition_fpga::general_work(int noutput_items __attribute__((unused)), int pcps_acquisition_fpga::general_work(int noutput_items __attribute__((unused)),
gr_vector_int& ninput_items, gr_vector_const_void_star& input_items, gr_vector_int& ninput_items __attribute__((unused)),
gr_vector_const_void_star& input_items __attribute__((unused)),
gr_vector_void_star& output_items __attribute__((unused))) gr_vector_void_star& output_items __attribute__((unused)))
{ {
// the general work is not used with the acquisition that uses the FPGA // the general work is not used with the acquisition that uses the FPGA

18
src/algorithms/acquisition/libs/fpga_acquisition.cc
View File

@ -87,8 +87,10 @@ void Fpga_Acquisition::write_local_code()
Fpga_Acquisition::Fpga_Acquisition(std::string device_name, Fpga_Acquisition::Fpga_Acquisition(std::string device_name,
uint32_t nsamples, uint32_t nsamples,
uint32_t doppler_max, uint32_t doppler_max,
uint32_t nsamples_total, int64_t fs_in, uint32_t nsamples_total,
uint32_t sampled_ms, uint32_t select_queue, int64_t fs_in,
uint32_t sampled_ms __attribute__((unused)),
uint32_t select_queue,
lv_16sc_t *all_fft_codes, lv_16sc_t *all_fft_codes,
uint32_t excludelimit) uint32_t excludelimit)
{ {
@ -193,7 +195,11 @@ void Fpga_Acquisition::run_acquisition(void)
// enable interrupts // enable interrupts
int32_t reenable = 1; int32_t reenable = 1;
int32_t disable_int = 0; int32_t disable_int = 0;
write(d_fd, reinterpret_cast<void *>(&reenable), sizeof(int32_t)); ssize_t nbytes = TEMP_FAILURE_RETRY(write(d_fd, reinterpret_cast<void *>(&reenable), sizeof(int32_t)));
if (nbytes != sizeof(int32_t))
{
std::cerr << "Error enabling run in the FPGA." << std::endl;
}
// launch the acquisition process // launch the acquisition process
d_map_base[8] = LAUNCH_ACQUISITION; // writing a 1 to reg 8 launches the acquisition process d_map_base[8] = LAUNCH_ACQUISITION; // writing a 1 to reg 8 launches the acquisition process
@ -208,7 +214,11 @@ void Fpga_Acquisition::run_acquisition(void)
std::cout << "acquisition module Interrupt number " << irq_count << std::endl; std::cout << "acquisition module Interrupt number " << irq_count << std::endl;
} }
write(d_fd, reinterpret_cast<void *>(&disable_int), sizeof(int32_t)); nbytes = TEMP_FAILURE_RETRY(write(d_fd, reinterpret_cast<void *>(&disable_int), sizeof(int32_t)));
if (nbytes != sizeof(int32_t))
{
std::cerr << "Error disabling interruptions in the FPGA." << std::endl;
}
} }

6
src/algorithms/libs/gnss_sdr_fpga_sample_counter.cc
View File

@ -269,7 +269,11 @@ uint32_t gnss_sdr_fpga_sample_counter::wait_for_interrupt_and_read_counter()
// enable interrupts // enable interrupts
int32_t reenable = 1; int32_t reenable = 1;
write(fd, reinterpret_cast<void *>(&reenable), sizeof(int32_t)); ssize_t nbytes = TEMP_FAILURE_RETRY(write(fd, reinterpret_cast<void *>(&reenable), sizeof(int32_t)));
if (nbytes != sizeof(int32_t))
{
std::cerr << "Error enabling interruptions in the FPGA." << std::endl;
}
// wait for interrupt // wait for interrupt
nb = read(fd, &irq_count, sizeof(irq_count)); nb = read(fd, &irq_count, sizeof(irq_count));

2
src/algorithms/telemetry_decoder/gnuradio_blocks/glonass_l1_ca_telemetry_decoder_cc.cc
View File

@ -279,7 +279,7 @@ int glonass_l1_ca_telemetry_decoder_cc::general_work(int noutput_items __attribu
d_flag_preamble = false; d_flag_preamble = false;
if (d_symbol_history.size() == d_symbols_per_preamble) if (static_cast<int32_t>(d_symbol_history.size()) == d_symbols_per_preamble)
{ {
// ******* preamble correlation ******** // ******* preamble correlation ********
int i = 0; int i = 0;

18
src/algorithms/tracking/adapters/galileo_e1_dll_pll_veml_tracking_fpga.cc
View File

@ -135,16 +135,15 @@ GalileoE1DllPllVemlTrackingFpga::GalileoE1DllPllVemlTrackingFpga(
uint32_t code_samples_per_chip = 2; uint32_t code_samples_per_chip = 2;
d_ca_codes = static_cast<int32_t*>(volk_gnsssdr_malloc(static_cast<int32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS) * code_samples_per_chip * GALILEO_E1_NUMBER_OF_CODES * sizeof(int32_t), volk_gnsssdr_get_alignment())); d_ca_codes = static_cast<int32_t*>(volk_gnsssdr_malloc(static_cast<int32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS) * code_samples_per_chip * GALILEO_E1_NUMBER_OF_CODES * sizeof(int32_t), volk_gnsssdr_get_alignment()));
float* ca_codes_f; float* ca_codes_f;
float* data_codes_f; float* data_codes_f = nullptr;
if (d_track_pilot)
if (trk_param_fpga.track_pilot)
{ {
d_data_codes = static_cast<int32_t*>(volk_gnsssdr_malloc((static_cast<uint32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS)) * code_samples_per_chip * GALILEO_E1_NUMBER_OF_CODES * sizeof(int32_t), volk_gnsssdr_get_alignment())); d_data_codes = static_cast<int32_t*>(volk_gnsssdr_malloc((static_cast<uint32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS)) * code_samples_per_chip * GALILEO_E1_NUMBER_OF_CODES * sizeof(int32_t), volk_gnsssdr_get_alignment()));
} }
ca_codes_f = static_cast<float*>(volk_gnsssdr_malloc(static_cast<int32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS) * code_samples_per_chip * sizeof(float), volk_gnsssdr_get_alignment())); ca_codes_f = static_cast<float*>(volk_gnsssdr_malloc(static_cast<int32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS) * code_samples_per_chip * sizeof(float), volk_gnsssdr_get_alignment()));
if (trk_param_fpga.track_pilot) if (d_track_pilot)
{ {
data_codes_f = static_cast<float*>(volk_gnsssdr_malloc((static_cast<uint32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS)) * code_samples_per_chip * sizeof(float), volk_gnsssdr_get_alignment())); data_codes_f = static_cast<float*>(volk_gnsssdr_malloc((static_cast<uint32_t>(GALILEO_E1_B_CODE_LENGTH_CHIPS)) * code_samples_per_chip * sizeof(float), volk_gnsssdr_get_alignment()));
} }
@ -152,7 +151,7 @@ GalileoE1DllPllVemlTrackingFpga::GalileoE1DllPllVemlTrackingFpga(
for (uint32_t PRN = 1; PRN <= GALILEO_E1_NUMBER_OF_CODES; PRN++) for (uint32_t PRN = 1; PRN <= GALILEO_E1_NUMBER_OF_CODES; PRN++)
{ {
char data_signal[3] = "1B"; char data_signal[3] = "1B";
if (trk_param_fpga.track_pilot) if (d_track_pilot)
{ {
char pilot_signal[3] = "1C"; char pilot_signal[3] = "1C";
galileo_e1_code_gen_sinboc11_float(ca_codes_f, pilot_signal, PRN); galileo_e1_code_gen_sinboc11_float(ca_codes_f, pilot_signal, PRN);
@ -176,9 +175,9 @@ GalileoE1DllPllVemlTrackingFpga::GalileoE1DllPllVemlTrackingFpga(
} }
delete[] ca_codes_f; delete[] ca_codes_f;
if (trk_param_fpga.track_pilot) if (d_track_pilot)
{ {
delete[] data_codes_f; volk_gnsssdr_free(data_codes_f);
} }
trk_param_fpga.ca_codes = d_ca_codes; trk_param_fpga.ca_codes = d_ca_codes;
trk_param_fpga.data_codes = d_data_codes; trk_param_fpga.data_codes = d_data_codes;
@ -200,6 +199,7 @@ GalileoE1DllPllVemlTrackingFpga::~GalileoE1DllPllVemlTrackingFpga()
} }
} }
void GalileoE1DllPllVemlTrackingFpga::start_tracking() void GalileoE1DllPllVemlTrackingFpga::start_tracking()
{ {
tracking_fpga_sc->start_tracking(); tracking_fpga_sc->start_tracking();
@ -227,7 +227,7 @@ void GalileoE1DllPllVemlTrackingFpga::connect(gr::top_block_sptr top_block)
if (top_block) if (top_block)
{ /* top_block is not null */ { /* top_block is not null */
}; };
//nothing to connect, now the tracking uses gr_sync_decimator // nothing to connect, now the tracking uses gr_sync_decimator
} }
@ -236,7 +236,7 @@ void GalileoE1DllPllVemlTrackingFpga::disconnect(gr::top_block_sptr top_block)
if (top_block) if (top_block)
{ /* top_block is not null */ { /* top_block is not null */
}; };
//nothing to disconnect, now the tracking uses gr_sync_decimator // nothing to disconnect, now the tracking uses gr_sync_decimator
} }

1
src/algorithms/tracking/adapters/galileo_e1_dll_pll_veml_tracking_fpga.h
View File

@ -3,7 +3,6 @@
* \brief Adapts a DLL+PLL VEML (Very Early Minus Late) tracking loop block * \brief Adapts a DLL+PLL VEML (Very Early Minus Late) tracking loop block
* to a TrackingInterface for Galileo E1 signals for the FPGA * to a TrackingInterface for Galileo E1 signals for the FPGA
* \author Marc Majoral, 2019. mmajoral(at)cttc.cat * \author Marc Majoral, 2019. mmajoral(at)cttc.cat
* \author Luis Esteve, 2012. luis(at)epsilon-formacion.com
* *
* Code DLL + carrier PLL according to the algorithms described in: * Code DLL + carrier PLL according to the algorithms described in:
* K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen, * K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen,

10
src/algorithms/tracking/adapters/galileo_e5a_dll_pll_tracking_fpga.cc
View File

@ -2,15 +2,7 @@
* \file galileo_e5a_dll_pll_tracking_fpga.cc * \file galileo_e5a_dll_pll_tracking_fpga.cc
* \brief Adapts a code DLL + carrier PLL * \brief Adapts a code DLL + carrier PLL
* tracking block to a TrackingInterface for Galileo E5a signals for the FPGA * tracking block to a TrackingInterface for Galileo E5a signals for the FPGA
* \brief Adapts a PCPS acquisition block to an AcquisitionInterface for * \author Marc Majoral, 2019. mmajoral(at)cttc.cat
* Galileo E5a data and pilot Signals for the FPGA
* \author Marc Sales, 2014. marcsales92(at)gmail.com
* \based on work from:
* <ul>
* <li> Marc Majoral, 2019. mmajoral(at)cttc.cat
* <li> Javier Arribas, 2011. jarribas(at)cttc.es
* <li> Luis Esteve, 2012. luis(at)epsilon-formacion.com
* </ul>
* *
* ------------------------------------------------------------------------- * -------------------------------------------------------------------------
* *

10
src/algorithms/tracking/adapters/galileo_e5a_dll_pll_tracking_fpga.h
View File

@ -2,15 +2,7 @@
* \file galileo_e5a_dll_pll_tracking_fpga.h * \file galileo_e5a_dll_pll_tracking_fpga.h
* \brief Adapts a code DLL + carrier PLL * \brief Adapts a code DLL + carrier PLL
* tracking block to a TrackingInterface for Galileo E5a signals for the FPGA * tracking block to a TrackingInterface for Galileo E5a signals for the FPGA
* \brief Adapts a PCPS acquisition block to an AcquisitionInterface for * \author Marc Majoral, 2019. mmajoral(at)cttc.cat
* Galileo E5a data and pilot Signals for the FPGA
* \author Marc Sales, 2014. marcsales92(at)gmail.com
* \based on work from:
* <ul>
* <li> Marc Majoral, 2019. mmajoral(at)cttc.cat
* <li> Javier Arribas, 2011. jarribas(at)cttc.es
* <li> Luis Esteve, 2012. luis(at)epsilon-formacion.com
* </ul>
* *
* ------------------------------------------------------------------------- * -------------------------------------------------------------------------
* *

2
src/algorithms/tracking/adapters/gps_l1_ca_dll_pll_tracking_fpga.cc
View File

@ -3,8 +3,6 @@
* \brief Implementation of an adapter of a DLL+PLL tracking loop block * \brief Implementation of an adapter of a DLL+PLL tracking loop block
* for GPS L1 C/A to a TrackingInterface for the FPGA * for GPS L1 C/A to a TrackingInterface for the FPGA
* \author Marc Majoral, 2019, mmajoral(at)cttc.es * \author Marc Majoral, 2019, mmajoral(at)cttc.es
* Carlos Aviles, 2010. carlos.avilesr(at)googlemail.com
* Javier Arribas, 2011. jarribas(at)cttc.es
* *
* Code DLL + carrier PLL according to the algorithms described in: * Code DLL + carrier PLL according to the algorithms described in:
* K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen, * K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen,

2
src/algorithms/tracking/adapters/gps_l1_ca_dll_pll_tracking_fpga.h
View File

@ -3,8 +3,6 @@
* \brief Interface of an adapter of a DLL+PLL tracking loop block * \brief Interface of an adapter of a DLL+PLL tracking loop block
* for GPS L1 C/A to a TrackingInterface for the FPGA * for GPS L1 C/A to a TrackingInterface for the FPGA
* \author Marc Majoral, 2019, mmajoral(at)cttc.es * \author Marc Majoral, 2019, mmajoral(at)cttc.es
* Carlos Aviles, 2010. carlos.avilesr(at)googlemail.com
* Javier Arribas, 2011. jarribas(at)cttc.es
* *
* Code DLL + carrier PLL according to the algorithms described in: * Code DLL + carrier PLL according to the algorithms described in:
* K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen, * K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen,

6
src/algorithms/tracking/adapters/gps_l2_m_dll_pll_tracking_fpga.cc
View File

@ -1,8 +1,8 @@
/*! /*!
* \file gps_l2_m_dll_pll_tracking.cc * \file gps_l2_m_dll_pll_tracking_fpga.cc
* \brief Implementation of an adapter of a DLL+PLL tracking loop block * \brief Implementation of an adapter of a DLL+PLL tracking loop block
* for GPS L1 C/A to a TrackingInterface * for GPS L2C to a TrackingInterface
* \author Javier Arribas, 2015. jarribas(at)cttc.es * \author Javier Arribas, 2019. jarribas(at)cttc.es
* *
* Code DLL + carrier PLL according to the algorithms described in: * Code DLL + carrier PLL according to the algorithms described in:
* K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen, * K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen,

7
src/algorithms/tracking/adapters/gps_l2_m_dll_pll_tracking_fpga.h
View File

@ -1,9 +1,8 @@
/*! /*!
* \file gps_l2_m_dll_pll_tracking.h * \file gps_l2_m_dll_pll_tracking_fpga.h
* \brief Interface of an adapter of a DLL+PLL tracking loop block * \brief Interface of an adapter of a DLL+PLL tracking loop block
* for GPS L1 C/A to a TrackingInterface * for GPS L2C to a TrackingInterface
* \author Carlos Aviles, 2010. carlos.avilesr(at)googlemail.com * \author Marc Majoral, 2019, mmajoral(at)cttc.es
* Javier Arribas, 2011. jarribas(at)cttc.es
* *
* Code DLL + carrier PLL according to the algorithms described in: * Code DLL + carrier PLL according to the algorithms described in:
* K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen, * K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen,

24
src/algorithms/tracking/adapters/gps_l5_dll_pll_tracking_fpga.cc
View File

@ -1,9 +1,9 @@
/*! /*!
* \file gps_l5_dll_pll_tracking.cc * \file gps_l5_dll_pll_tracking_fpga.cc
* \brief Interface of an adapter of a DLL+PLL tracking loop block * \brief Interface of an adapter of a DLL+PLL tracking loop block
* for GPS L5 to a TrackingInterface * for GPS L5 to a TrackingInterface
* \author Marc Majoral, 2019. mmajoral(at)cttc.cat * \author Marc Majoral, 2019. mmajoral(at)cttc.cat
* \author Javier Arribas, 2017. jarribas(at)cttc.es * Javier Arribas, 2019. jarribas(at)cttc.es
* *
* Code DLL + carrier PLL according to the algorithms described in: * Code DLL + carrier PLL according to the algorithms described in:
* K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen, * K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen,
@ -135,37 +135,39 @@ GpsL5DllPllTrackingFpga::GpsL5DllPllTrackingFpga(
auto code_length_chips = static_cast<uint32_t>(GPS_L5I_CODE_LENGTH_CHIPS); auto code_length_chips = static_cast<uint32_t>(GPS_L5I_CODE_LENGTH_CHIPS);
float *tracking_code; float *tracking_code;
float *data_code; float *data_code = nullptr;
tracking_code = static_cast<float *>(volk_gnsssdr_malloc(code_length_chips * sizeof(float), volk_gnsssdr_get_alignment())); tracking_code = static_cast<float *>(volk_gnsssdr_malloc(code_length_chips * sizeof(float), volk_gnsssdr_get_alignment()));
if (trk_param_fpga.track_pilot) if (track_pilot)
{ {
data_code = static_cast<float *>(volk_gnsssdr_malloc(code_length_chips * sizeof(float), volk_gnsssdr_get_alignment())); data_code = static_cast<float *>(volk_gnsssdr_malloc(code_length_chips * sizeof(float), volk_gnsssdr_get_alignment()));
for (uint32_t i = 0; i < code_length_chips; i++)
{
data_code[i] = 0.0;
}
} }
d_ca_codes = static_cast<int32_t *>(volk_gnsssdr_malloc(static_cast<int32_t>(code_length_chips * NUM_PRNs) * sizeof(int32_t), volk_gnsssdr_get_alignment())); d_ca_codes = static_cast<int32_t *>(volk_gnsssdr_malloc(static_cast<int32_t>(code_length_chips * NUM_PRNs) * sizeof(int32_t), volk_gnsssdr_get_alignment()));
if (trk_param_fpga.track_pilot) if (track_pilot)
{ {
d_data_codes = static_cast<int32_t *>(volk_gnsssdr_malloc((static_cast<uint32_t>(code_length_chips)) * NUM_PRNs * sizeof(int32_t), volk_gnsssdr_get_alignment())); d_data_codes = static_cast<int32_t *>(volk_gnsssdr_malloc((static_cast<uint32_t>(code_length_chips)) * NUM_PRNs * sizeof(int32_t), volk_gnsssdr_get_alignment()));
} }
for (uint32_t PRN = 1; PRN <= NUM_PRNs; PRN++) for (uint32_t PRN = 1; PRN <= NUM_PRNs; PRN++)
{ {
if (trk_param_fpga.track_pilot) if (track_pilot)
{ {
gps_l5q_code_gen_float(tracking_code, PRN); gps_l5q_code_gen_float(tracking_code, PRN);
gps_l5i_code_gen_float(data_code, PRN); gps_l5i_code_gen_float(data_code, PRN);
for (uint32_t s = 0; s < code_length_chips; s++) for (uint32_t s = 0; s < code_length_chips; s++)
{ {
d_ca_codes[static_cast<int32_t>(code_length_chips) * (PRN - 1) + s] = static_cast<int32_t>(tracking_code[s]); d_ca_codes[static_cast<int32_t>(code_length_chips) * (PRN - 1) + s] = static_cast<int32_t>(tracking_code[s]);
d_data_codes[static_cast<int32_t>(code_length_chips) * (PRN - 1) + s] = static_cast<int32_t>(data_code[s]); d_data_codes[static_cast<int32_t>(code_length_chips) * (PRN - 1) + s] = static_cast<int32_t>(data_code[s]);
} }
} }
else else
{ {
gps_l5i_code_gen_float(tracking_code, PRN); gps_l5i_code_gen_float(tracking_code, PRN);
@ -176,10 +178,10 @@ GpsL5DllPllTrackingFpga::GpsL5DllPllTrackingFpga(
} }
} }
delete[] tracking_code; volk_gnsssdr_free(tracking_code);
if (trk_param_fpga.track_pilot) if (track_pilot)
{ {
delete[] data_code; volk_gnsssdr_free(data_code);
} }
trk_param_fpga.ca_codes = d_ca_codes; trk_param_fpga.ca_codes = d_ca_codes;
trk_param_fpga.data_codes = d_data_codes; trk_param_fpga.data_codes = d_data_codes;

4
src/algorithms/tracking/adapters/gps_l5_dll_pll_tracking_fpga.h
View File

@ -1,9 +1,9 @@
/*! /*!
* \file gps_l5_dll_pll_tracking.h * \file gps_l5_dll_pll_tracking_fpga.h
* \brief Interface of an adapter of a DLL+PLL tracking loop block * \brief Interface of an adapter of a DLL+PLL tracking loop block
* for GPS L5 to a TrackingInterface * for GPS L5 to a TrackingInterface
* \author Marc Majoral, 2019. mmajoral(at)cttc.cat * \author Marc Majoral, 2019. mmajoral(at)cttc.cat
* \author Javier Arribas, 2017. jarribas(at)cttc.es * Javier Arribas, 2019. jarribas(at)cttc.es
* *
* Code DLL + carrier PLL according to the algorithms described in: * Code DLL + carrier PLL according to the algorithms described in:
* K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen, * K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen,

30
src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.cc
View File

@ -2,8 +2,7 @@
* \file dll_pll_veml_tracking_fpga.cc * \file dll_pll_veml_tracking_fpga.cc
* \brief Implementation of a code DLL + carrier PLL tracking block using an FPGA * \brief Implementation of a code DLL + carrier PLL tracking block using an FPGA
* \author Marc Majoral, 2019. marc.majoral(at)cttc.es * \author Marc Majoral, 2019. marc.majoral(at)cttc.es
* \author Antonio Ramos, 2018 antonio.ramosdet(at)gmail.com * \author Javier Arribas, 2019. jarribas(at)cttc.es
* \author Javier Arribas, 2018. jarribas(at)cttc.es
* *
* Code DLL + carrier PLL according to the algorithms described in: * Code DLL + carrier PLL according to the algorithms described in:
* [1] K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen, * [1] K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, and S.H.Jensen,
@ -315,7 +314,6 @@ dll_pll_veml_tracking_fpga::dll_pll_veml_tracking_fpga(const Dll_Pll_Conf_Fpga &
d_prompt_data_shift = &d_local_code_shift_chips[1]; d_prompt_data_shift = &d_local_code_shift_chips[1];
} }
if (trk_parameters.extend_correlation_symbols > 1) if (trk_parameters.extend_correlation_symbols > 1)
{ {
d_enable_extended_integration = true; d_enable_extended_integration = true;
@ -498,7 +496,6 @@ void dll_pll_veml_tracking_fpga::start_tracking()
std::cout << "Tracking of " << systemName << " " << signal_pretty_name << " signal started on channel " << d_channel << " for satellite " << Gnss_Satellite(systemName, d_acquisition_gnss_synchro->PRN) << std::endl; std::cout << "Tracking of " << systemName << " " << signal_pretty_name << " signal started on channel " << d_channel << " for satellite " << Gnss_Satellite(systemName, d_acquisition_gnss_synchro->PRN) << std::endl;
DLOG(INFO) << "Starting tracking of satellite " << Gnss_Satellite(systemName, d_acquisition_gnss_synchro->PRN) << " on channel " << d_channel; DLOG(INFO) << "Starting tracking of satellite " << Gnss_Satellite(systemName, d_acquisition_gnss_synchro->PRN) << " on channel " << d_channel;
multicorrelator_fpga->set_local_code_and_taps(d_local_code_shift_chips, d_prompt_data_shift, d_acquisition_gnss_synchro->PRN); multicorrelator_fpga->set_local_code_and_taps(d_local_code_shift_chips, d_prompt_data_shift, d_acquisition_gnss_synchro->PRN);
// enable tracking pull-in // enable tracking pull-in
d_state = 1; d_state = 1;
@ -677,7 +674,6 @@ void dll_pll_veml_tracking_fpga::run_dll_pll()
// New carrier Doppler frequency estimation // New carrier Doppler frequency estimation
d_carrier_doppler_hz = d_acq_carrier_doppler_hz + d_carr_error_filt_hz; d_carrier_doppler_hz = d_acq_carrier_doppler_hz + d_carr_error_filt_hz;
// ################## DLL ########################################################## // ################## DLL ##########################################################
// DLL discriminator // DLL discriminator
if (d_veml) if (d_veml)
@ -753,7 +749,6 @@ void dll_pll_veml_tracking_fpga::update_tracking_vars()
d_rem_carr_phase_rad += static_cast<float>(d_carrier_phase_step_rad * static_cast<double>(d_current_prn_length_samples) + 0.5 * d_carrier_phase_rate_step_rad * static_cast<double>(d_current_prn_length_samples) * static_cast<double>(d_current_prn_length_samples)); d_rem_carr_phase_rad += static_cast<float>(d_carrier_phase_step_rad * static_cast<double>(d_current_prn_length_samples) + 0.5 * d_carrier_phase_rate_step_rad * static_cast<double>(d_current_prn_length_samples) * static_cast<double>(d_current_prn_length_samples));
d_rem_carr_phase_rad = fmod(d_rem_carr_phase_rad, PI_2); d_rem_carr_phase_rad = fmod(d_rem_carr_phase_rad, PI_2);
// carrier phase accumulator // carrier phase accumulator
d_acc_carrier_phase_rad -= (d_carrier_phase_step_rad * static_cast<double>(d_current_prn_length_samples) + 0.5 * d_carrier_phase_rate_step_rad * static_cast<double>(d_current_prn_length_samples) * static_cast<double>(d_current_prn_length_samples)); d_acc_carrier_phase_rad -= (d_carrier_phase_step_rad * static_cast<double>(d_current_prn_length_samples) + 0.5 * d_carrier_phase_rate_step_rad * static_cast<double>(d_current_prn_length_samples) * static_cast<double>(d_current_prn_length_samples));
@ -1021,7 +1016,6 @@ int32_t dll_pll_veml_tracking_fpga::save_matfile()
auto *aux2 = new double[num_epoch]; auto *aux2 = new double[num_epoch];
auto *PRN = new uint32_t[num_epoch]; auto *PRN = new uint32_t[num_epoch];
try try
{ {
if (dump_file.is_open()) if (dump_file.is_open())
@ -1249,15 +1243,23 @@ void dll_pll_veml_tracking_fpga::stop_tracking()
d_state = 0; d_state = 0;
} }
int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((unused)), gr_vector_int &ninput_items,
gr_vector_const_void_star &input_items, gr_vector_void_star &output_items) void dll_pll_veml_tracking_fpga::reset(void)
{
multicorrelator_fpga->unlock_channel();
}
int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((unused)),
gr_vector_int &ninput_items __attribute__((unused)),
gr_vector_const_void_star &input_items __attribute__((unused)),
gr_vector_void_star &output_items)
{ {
auto **out = reinterpret_cast<Gnss_Synchro **>(&output_items[0]); auto **out = reinterpret_cast<Gnss_Synchro **>(&output_items[0]);
Gnss_Synchro current_synchro_data = Gnss_Synchro(); Gnss_Synchro current_synchro_data = Gnss_Synchro();
d_current_prn_length_samples = d_next_prn_length_samples; d_current_prn_length_samples = d_next_prn_length_samples;
switch (d_state) switch (d_state)
{ {
case 0: // Standby - Consume samples at full throttle, do nothing case 0: // Standby - Consume samples at full throttle, do nothing
@ -1300,7 +1302,6 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
current_synchro_data.Tracking_sample_counter = absolute_samples_offset; current_synchro_data.Tracking_sample_counter = absolute_samples_offset;
d_sample_counter_next = d_sample_counter; d_sample_counter_next = d_sample_counter;
// Signal alignment (skip samples until the incoming signal is aligned with local replica) // Signal alignment (skip samples until the incoming signal is aligned with local replica)
// Doppler effect Fd = (C / (C + Vr)) * F // Doppler effect Fd = (C / (C + Vr)) * F
@ -1477,6 +1478,7 @@ int dll_pll_veml_tracking_fpga::general_work(int noutput_items __attribute__((un
return 0; return 0;
} }
void dll_pll_veml_tracking_fpga::run_state_2(Gnss_Synchro &current_synchro_data) void dll_pll_veml_tracking_fpga::run_state_2(Gnss_Synchro &current_synchro_data)
{ {
d_sample_counter = d_sample_counter_next; d_sample_counter = d_sample_counter_next;
@ -1649,9 +1651,3 @@ void dll_pll_veml_tracking_fpga::run_state_2(Gnss_Synchro &current_synchro_data)
} }
} }
} }
void dll_pll_veml_tracking_fpga::reset(void)
{
multicorrelator_fpga->unlock_channel();
}

3
src/algorithms/tracking/gnuradio_blocks/dll_pll_veml_tracking_fpga.h
View File

@ -2,8 +2,7 @@
* \file dll_pll_veml_tracking_fpga.h * \file dll_pll_veml_tracking_fpga.h
* \brief Implementation of a code DLL + carrier PLL tracking block using an FPGA. * \brief Implementation of a code DLL + carrier PLL tracking block using an FPGA.
* \author Marc Majoral, 2019. marc.majoral(at)cttc.es * \author Marc Majoral, 2019. marc.majoral(at)cttc.es
* \author Javier Arribas, 2018. jarribas(at)cttc.es * \author Javier Arribas, 2019. jarribas(at)cttc.es
* \author Antonio Ramos, 2018 antonio.ramosdet(at)gmail.com
* *
* ------------------------------------------------------------------------- * -------------------------------------------------------------------------
* *

151
src/algorithms/tracking/libs/fpga_multicorrelator.cc
View File

@ -1,12 +1,12 @@
/*! /*!
* \file fpga_multicorrelator_8sc.cc * \file fpga_multicorrelator.cc
* \brief High optimized FPGA vector correlator class * \brief FPGA vector correlator class
* \authors <ul> * \authors <ul>
* <li> Marc Majoral, 2019. mmajoral(at)cttc.cat * <li> Marc Majoral, 2019. mmajoral(at)cttc.cat
* <li> Javier Arribas, 2015. jarribas(at)cttc.es * <li> Javier Arribas, 2019. jarribas(at)cttc.es
* </ul> * </ul>
* *
* Class that controls and executes a high optimized vector correlator * Class that controls and executes a highly optimized vector correlator
* class in the FPGA * class in the FPGA
* *
* ------------------------------------------------------------------------- * -------------------------------------------------------------------------
@ -67,70 +67,6 @@
#define TEST_REGISTER_TRACK_WRITEVAL 0x55AA #define TEST_REGISTER_TRACK_WRITEVAL 0x55AA
uint64_t Fpga_Multicorrelator_8sc::read_sample_counter()
{
uint64_t sample_counter_tmp, sample_counter_msw_tmp;
sample_counter_tmp = d_map_base[SAMPLE_COUNTER_REG_ADDR_LSW];
sample_counter_msw_tmp = d_map_base[SAMPLE_COUNTER_REG_ADDR_MSW];
sample_counter_msw_tmp = sample_counter_msw_tmp << 32;
sample_counter_tmp = sample_counter_tmp + sample_counter_msw_tmp; // 2^32
return sample_counter_tmp;
}
void Fpga_Multicorrelator_8sc::set_initial_sample(uint64_t samples_offset)
{
d_initial_sample_counter = samples_offset;
d_map_base[INITIAL_COUNTER_VALUE_REG_ADDR_LSW] = (d_initial_sample_counter & 0xFFFFFFFF);
d_map_base[INITIAL_COUNTER_VALUE_REG_ADDR_MSW] = (d_initial_sample_counter >> 32) & 0xFFFFFFFF;
}
void Fpga_Multicorrelator_8sc::set_local_code_and_taps(float *shifts_chips, float *prompt_data_shift, int32_t PRN)
{
d_shifts_chips = shifts_chips;
d_prompt_data_shift = prompt_data_shift;
Fpga_Multicorrelator_8sc::fpga_configure_tracking_gps_local_code(PRN);
}
void Fpga_Multicorrelator_8sc::set_output_vectors(gr_complex *corr_out, gr_complex *Prompt_Data)
{
d_corr_out = corr_out;
d_Prompt_Data = Prompt_Data;
}
void Fpga_Multicorrelator_8sc::update_local_code(float rem_code_phase_chips)
{
d_rem_code_phase_chips = rem_code_phase_chips;
Fpga_Multicorrelator_8sc::fpga_compute_code_shift_parameters();
Fpga_Multicorrelator_8sc::fpga_configure_code_parameters_in_fpga();
}
void Fpga_Multicorrelator_8sc::Carrier_wipeoff_multicorrelator_resampler(
float rem_carrier_phase_in_rad, float phase_step_rad,
float carrier_phase_rate_step_rad,
float rem_code_phase_chips, float code_phase_step_chips,
float code_phase_rate_step_chips,
int32_t signal_length_samples)
{
update_local_code(rem_code_phase_chips);
d_rem_carrier_phase_in_rad = rem_carrier_phase_in_rad;
d_code_phase_step_chips = code_phase_step_chips;
d_phase_step_rad = phase_step_rad;
d_correlator_length_samples = signal_length_samples;
Fpga_Multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga();
Fpga_Multicorrelator_8sc::fpga_configure_signal_parameters_in_fpga();
Fpga_Multicorrelator_8sc::fpga_launch_multicorrelator_fpga();
int32_t irq_count;
ssize_t nb;
nb = read(d_device_descriptor, &irq_count, sizeof(irq_count));
if (nb != sizeof(irq_count))
{
std::cout << "Tracking_module Read failed to retrieve 4 bytes!" << std::endl;
std::cout << "Tracking_module Interrupt number " << irq_count << std::endl;
}
Fpga_Multicorrelator_8sc::read_tracking_gps_results();
}
Fpga_Multicorrelator_8sc::Fpga_Multicorrelator_8sc(int32_t n_correlators, Fpga_Multicorrelator_8sc::Fpga_Multicorrelator_8sc(int32_t n_correlators,
std::string device_name, uint32_t device_base, int32_t *ca_codes, int32_t *data_codes, uint32_t code_length_chips, bool track_pilot, std::string device_name, uint32_t device_base, int32_t *ca_codes, int32_t *data_codes, uint32_t code_length_chips, bool track_pilot,
uint32_t multicorr_type, uint32_t code_samples_per_chip) uint32_t multicorr_type, uint32_t code_samples_per_chip)
@ -186,6 +122,77 @@ Fpga_Multicorrelator_8sc::~Fpga_Multicorrelator_8sc()
} }
uint64_t Fpga_Multicorrelator_8sc::read_sample_counter()
{
uint64_t sample_counter_tmp, sample_counter_msw_tmp;
sample_counter_tmp = d_map_base[SAMPLE_COUNTER_REG_ADDR_LSW];
sample_counter_msw_tmp = d_map_base[SAMPLE_COUNTER_REG_ADDR_MSW];
sample_counter_msw_tmp = sample_counter_msw_tmp << 32;
sample_counter_tmp = sample_counter_tmp + sample_counter_msw_tmp; // 2^32
return sample_counter_tmp;
}
void Fpga_Multicorrelator_8sc::set_initial_sample(uint64_t samples_offset)
{
d_initial_sample_counter = samples_offset;
d_map_base[INITIAL_COUNTER_VALUE_REG_ADDR_LSW] = (d_initial_sample_counter & 0xFFFFFFFF);
d_map_base[INITIAL_COUNTER_VALUE_REG_ADDR_MSW] = (d_initial_sample_counter >> 32) & 0xFFFFFFFF;
}
void Fpga_Multicorrelator_8sc::set_local_code_and_taps(float *shifts_chips, float *prompt_data_shift, int32_t PRN)
{
d_shifts_chips = shifts_chips;
d_prompt_data_shift = prompt_data_shift;
Fpga_Multicorrelator_8sc::fpga_configure_tracking_gps_local_code(PRN);
}
void Fpga_Multicorrelator_8sc::set_output_vectors(gr_complex *corr_out, gr_complex *Prompt_Data)
{
d_corr_out = corr_out;
d_Prompt_Data = Prompt_Data;
}
void Fpga_Multicorrelator_8sc::update_local_code(float rem_code_phase_chips)
{
d_rem_code_phase_chips = rem_code_phase_chips;
Fpga_Multicorrelator_8sc::fpga_compute_code_shift_parameters();
Fpga_Multicorrelator_8sc::fpga_configure_code_parameters_in_fpga();
}
void Fpga_Multicorrelator_8sc::Carrier_wipeoff_multicorrelator_resampler(
float rem_carrier_phase_in_rad,
float phase_step_rad,
float carrier_phase_rate_step_rad __attribute__((unused)),
float rem_code_phase_chips,
float code_phase_step_chips __attribute__((unused)),
float code_phase_rate_step_chips __attribute__((unused)),
int32_t signal_length_samples)
{
update_local_code(rem_code_phase_chips);
d_rem_carrier_phase_in_rad = rem_carrier_phase_in_rad;
d_code_phase_step_chips = code_phase_step_chips;
d_phase_step_rad = phase_step_rad;
d_correlator_length_samples = signal_length_samples;
Fpga_Multicorrelator_8sc::fpga_compute_signal_parameters_in_fpga();
Fpga_Multicorrelator_8sc::fpga_configure_signal_parameters_in_fpga();
Fpga_Multicorrelator_8sc::fpga_launch_multicorrelator_fpga();
int32_t irq_count;
ssize_t nb;
nb = read(d_device_descriptor, &irq_count, sizeof(irq_count));
if (nb != sizeof(irq_count))
{
std::cout << "Tracking_module Read failed to retrieve 4 bytes!" << std::endl;
std::cout << "Tracking_module Interrupt number " << irq_count << std::endl;
}
Fpga_Multicorrelator_8sc::read_tracking_gps_results();
}
bool Fpga_Multicorrelator_8sc::free() bool Fpga_Multicorrelator_8sc::free()
{ {
// unlock the channel // unlock the channel
@ -424,8 +431,11 @@ void Fpga_Multicorrelator_8sc::fpga_launch_multicorrelator_fpga(void)
{ {
// enable interrupts // enable interrupts
int32_t reenable = 1; int32_t reenable = 1;
write(d_device_descriptor, reinterpret_cast<void *>(&reenable), sizeof(int32_t)); ssize_t nbytes = TEMP_FAILURE_RETRY(write(d_device_descriptor, reinterpret_cast<void *>(&reenable), sizeof(int32_t)));
if (nbytes != sizeof(int32_t))
{
std::cerr << "Error launching the FPGA multicorrelator" << std::endl;
}
// writing 1 to reg 14 launches the tracking // writing 1 to reg 14 launches the tracking
d_map_base[START_FLAG_ADDR] = 1; d_map_base[START_FLAG_ADDR] = 1;
} }
@ -459,6 +469,7 @@ void Fpga_Multicorrelator_8sc::unlock_channel(void)
d_map_base[STOP_TRACKING_REG_ADDR] = 1; // set the tracking module back to idle d_map_base[STOP_TRACKING_REG_ADDR] = 1; // set the tracking module back to idle
} }
void Fpga_Multicorrelator_8sc::close_device() void Fpga_Multicorrelator_8sc::close_device()
{ {
auto *aux = const_cast<uint32_t *>(d_map_base); auto *aux = const_cast<uint32_t *>(d_map_base);

8
src/algorithms/tracking/libs/fpga_multicorrelator.h
View File

@ -1,12 +1,12 @@
/*! /*!
* \file fpga_multicorrelator_8sc.h * \file fpga_multicorrelator.h
* \brief High optimized FPGA vector correlator class * \brief FPGA vector correlator class
* \authors <ul> * \authors <ul>
* <li> Marc Majoral, 2019. mmajoral(at)cttc.cat * <li> Marc Majoral, 2019. mmajoral(at)cttc.cat
* <li> Javier Arribas, 2016. jarribas(at)cttc.es * <li> Javier Arribas, 2019. jarribas(at)cttc.es
* </ul> * </ul>
* *
* Class that controls and executes a high optimized vector correlator * Class that controls and executes a highly optimized vector correlator
* class in the FPGA * class in the FPGA
* *
* ------------------------------------------------------------------------- * -------------------------------------------------------------------------

12
src/tests/unit-tests/signal-processing-blocks/acquisition/gps_l1_ca_pcps_acquisition_test_fpga.cc
View File

@ -102,7 +102,11 @@ void thread_acquisition_send_rx_samples(gr::top_block_sptr top_block,
pointer_float = (float *)&buffer_float[0]; pointer_float = (float *)&buffer_float[0];
for (int k = 0; k < file_length; k = k + FLOAT_SIZE) for (int k = 0; k < file_length; k = k + FLOAT_SIZE)
{ {
fread(buffer_float, FLOAT_SIZE, 1, rx_signal_file); size_t result = fread(buffer_float, FLOAT_SIZE, 1, rx_signal_file);
if (result != FLOAT_SIZE)
{
std::cerr << "Error reading buffer" << std::endl;
}
if (fabs(pointer_float[0]) > max) if (fabs(pointer_float[0]) > max)
{ {
@ -152,7 +156,11 @@ void thread_acquisition_send_rx_samples(gr::top_block_sptr top_block,
for (int t = 0; t < transfer_size; t++) for (int t = 0; t < transfer_size; t++)
{ {
fread(buffer_float, FLOAT_SIZE, 1, rx_signal_file); size_t result = fread(buffer_float, FLOAT_SIZE, 1, rx_signal_file);
if (result != FLOAT_SIZE)
{
std::cerr << "Error reading buffer" << std::endl;
}
// specify (float) (int) for a quantization maximizing the dynamic range // specify (float) (int) for a quantization maximizing the dynamic range
buffer_DMA[t] = static_cast<signed char>((pointer_float[0] * (RX_SIGNAL_MAX_VALUE - 1) / max)); buffer_DMA[t] = static_cast<signed char>((pointer_float[0] * (RX_SIGNAL_MAX_VALUE - 1) / max));

13
src/tests/unit-tests/signal-processing-blocks/tracking/gps_l1_ca_dll_pll_tracking_test_fpga.cc
View File

@ -102,7 +102,11 @@ void send_tracking_gps_input_samples(FILE *rx_signal_file,
} }
if (num_remaining_samples > DMA_TRACK_TRANSFER_SIZE) if (num_remaining_samples > DMA_TRACK_TRANSFER_SIZE)
{ {
fread(buffer_DMA, DMA_TRACK_TRANSFER_SIZE, 1, rx_signal_file); size_t result = fread(buffer_DMA, DMA_TRACK_TRANSFER_SIZE, 1, rx_signal_file);
if (result != DMA_TRACK_TRANSFER_SIZE)
{
std::cerr << "Error reading from DMA" << std::endl;
}
assert(DMA_TRACK_TRANSFER_SIZE == write(dma_descr, &buffer_DMA[0], DMA_TRACK_TRANSFER_SIZE)); assert(DMA_TRACK_TRANSFER_SIZE == write(dma_descr, &buffer_DMA[0], DMA_TRACK_TRANSFER_SIZE));
num_remaining_samples = num_remaining_samples - DMA_TRACK_TRANSFER_SIZE; num_remaining_samples = num_remaining_samples - DMA_TRACK_TRANSFER_SIZE;
@ -110,8 +114,11 @@ void send_tracking_gps_input_samples(FILE *rx_signal_file,
} }
else else
{ {
fread(buffer_DMA, num_remaining_samples, 1, rx_signal_file); size_t result = fread(buffer_DMA, num_remaining_samples, 1, rx_signal_file);
if (static_cast<int>(result) != num_remaining_samples)
{
std::cerr << "Error reading from DMA" << std::endl;
}
assert(num_remaining_samples == write(dma_descr, &buffer_DMA[0], num_remaining_samples)); assert(num_remaining_samples == write(dma_descr, &buffer_DMA[0], num_remaining_samples));
num_samples_transferred = num_samples_transferred + num_remaining_samples; num_samples_transferred = num_samples_transferred + num_remaining_samples;
num_remaining_samples = 0; num_remaining_samples = 0;