mirror of
https://github.com/gnss-sdr/gnss-sdr
synced 2024-12-13 03:30:33 +00:00
133 lines
3.5 KiB
C
133 lines
3.5 KiB
C
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/*
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* Code from: USRP - Universal Software Radio Peripheral (GNU Radio)
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*
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* Initial modifications by:
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*
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* Stephan Esterhuizen, Aerospace Engineering Sciences
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* University of Colorado at Boulder
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* Boulder CO, USA
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*
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* Further modifications for use with the SiGe USB module to accompany
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* the textbook: "A Software-Defined GPS and Galileo Receiver: A
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* Single-Frequency Approach" by Kai Borre, Dennis Akos, et.al. by:
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*
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* Marcus Junered, GNSS Research Group
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* Lulea University of Technology
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* Lulea, Sweden
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*
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* http://ccar.colorado.edu/gnss
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*
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* ---------------------------------------------------------------------
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*
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* GN3S - GNSS IF Streamer for Windows
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* Copyright (C) 2006 Marcus Junered
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "usrp_common.h"
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/* If wordwide is defined, will grab 16 bits, otherwise only
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* bits 7-0 is used */
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#undef wordwide
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void init_usrp(void)
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{
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CPUCS = bmCLKSPD1; // CPU runs @ 48 MHz
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CKCON = 0; // MOVX takes 2 cycles
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IFCONFIG = bmIFGPIF;
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//IFCONFIG = bmIFGPIF|bmIFCLKSRC|bmIFCLKOE;//|bm3048MHZ;
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//IFCONFIG = bmIFGPIF|bmIFCLKSRC;
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SYNCDELAY;
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//REVCTL = bmDYN_OUT | bmENH_PKT; // highly recommended by docs
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//SYNCDELAY;
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// configure end points
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EP1OUTCFG = bmVALID | bmBULK;
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SYNCDELAY;
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EP1INCFG = bmVALID | bmBULK | bmIN;
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SYNCDELAY;
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// 512 quad bulk OUT
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//EP2CFG = bmVALID | bmBULK ; //| bmQUADBUF;
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EP2CFG = 0;
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SYNCDELAY;
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// disabled
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EP4CFG = 0;
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SYNCDELAY;
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// 512 quad bulk IN
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EP6CFG = bmVALID | bmBULK | bmQUADBUF | bmIN;
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SYNCDELAY;
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// disabled
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EP8CFG = 0;
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SYNCDELAY;
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// reset FIFOs
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FIFORESET = bmNAKALL;
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SYNCDELAY;
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//FIFORESET = 2;
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//SYNCDELAY;
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// FIFORESET = 4; SYNCDELAY;
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FIFORESET = 6;
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SYNCDELAY;
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// FIFORESET = 8; SYNCDELAY;
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FIFORESET = 0;
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SYNCDELAY;
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// configure end point FIFOs
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// let core see 0 to 1 transistion of autoout bit
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#ifdef wordwide
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EP2FIFOCFG = 0x00;
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EP6FIFOCFG = bmZEROLENIN | bmAUTOIN | bmWORDWIDE;
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#else
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EP2FIFOCFG = 0x00;
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EP4FIFOCFG = 0x00;
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EP6FIFOCFG = bmZEROLENIN | bmAUTOIN;
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EP8FIFOCFG = 0x00;
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#endif
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SYNCDELAY;
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EP0BCH = 0;
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SYNCDELAY;
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// arm EP1OUT so we can receive "out" packets (TRM pg 8-8)
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EP1OUTBC = 0;
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SYNCDELAY;
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//EP2GPIFFLGSEL = 0x01;
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//SYNCDELAY; // For EP2OUT, GPIF uses EF flag
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EP6GPIFFLGSEL = 0x02;
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SYNCDELAY; // For EP6IN, GPIF uses FF flag
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/* waveform DONE when FF/EF flags get set */
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EP6GPIFPFSTOP=0x01; SYNCDELAY;
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//EP2GPIFPFSTOP=0x01; SYNCDELAY;
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EP6AUTOINLENH = (512) >> 8;
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SYNCDELAY; // this is the length for high speed
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EP6AUTOINLENL = (512) & 0xff;
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SYNCDELAY;
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}
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